On Tue, 13 Oct 2026 at 12:05, Philippe Mathieu-Daudé <[email protected]> wrote: > > On 13/10/26 10:38, Peter Maydell wrote: > > We put the definitions of GICv5 IRS registers and guest-memory data > > structures directly into arm_gicv5.c. It turns out that there are a > > few cases where we would like them outside that file (for instance > > register reset is handled in arm_gicv5_common.c). > > > > Move the definitions to their own header file. > > There are pre-existing typo worth fixing before moving IMO.
Yep, good idea. (None of these are in registers the current code is using, so they're harmless right now and don't need a stable backport.) > > Signed-off-by: Peter Maydell <[email protected]> > > --- > > hw/intc/arm_gicv5.c | 270 +---------------------------- > > include/hw/intc/arm_gicv5_regs.h | 286 +++++++++++++++++++++++++++++++ > > 2 files changed, 287 insertions(+), 269 deletions(-) > > create mode 100644 include/hw/intc/arm_gicv5_regs.h > > > > -REG64(IRS_VPE_SELR, 0x240) > > - FIELD(IRS_VPE_SELR, VM_ID, 0, 16) > > - FIELD(IRS_VPE_SELR, VPE_ID, 32, 16) > > - FIELD(IRS_VPE_SELR, S, 63, 1) > > - > > -REG64(IRS_VPE_DBR, 0x248) > > - FIELD(IRS_VPE_DBR, INTID, 0, 24) > > - FIELD(IRS_VPE_DBR, DBPM, 32, 5) > > - FIELD(IRS_VPE_DBR, REQ_DB, 62, 1) > > - FIELD(IRS_VPE_DBR, DBV, 63, 1) > > - > > -REG32(IRS_VPE_HPPIR, 0x250) > > Pre-existing (or maybe that changed since previous releases) > this register is 64-bit. I think I must have just copy-pasted it wrong. > > - FIELD(IRS_VPE_HPPIR, ID, 0, 24) > > - FIELD(IRS_VPE_HPPIR, TYPE, 29, 3) > > - FIELD(IRS_VPE_HPPIR, HPPIV, 32, 1) > > (thus the expanded HPPIV definitions might be wrong). Luckily FIELD() doesn't depend on the REG32 vs REG64 macro The only difference between REG32 and REG64 is how they define the R_FOO constants, which I don't use in this series, which is why this typo didn't have any visible effects. thanks -- PMM
