Andy Chandler wrote: > As for the accelerator, I think I remember seeing that in > action. Am I right in thinking it affected the screen refresh > slightly and there was the odd line across the screen, > possibly where the ASIC didn't gain access to the video RAM > in time? (I'm pretending to know how Simon's design worked!)
Something like that. We weren't handling wait states right because the clock for the external processor and the internal processor weren't sync'ed up correctly. So we were contending the bus when video data was going back and forth. I can't remember if we were also screwing up the data writes, but we might have been. Next step would have been to design a system to handle the differences in the clock, probably using a PAL to do it... That way, the wait states would be correctly honored at the right time, and there would have been no video glitches. Si
