Re: gEDA-user: GEDA code sprint reminder -- one week from today!
On Monday 25 September 2006 12:10, Giorgenes Gelatti wrote: That's great. I'd like to participate, but, unfortunally, I'm too new to geda and electronics. Maybe next year. There are lots of ways to contribute. Coding is one of the least important. If you really are too new. how about working on beginner documentation? You can also help a lot be answering beginner questions on the email lists. These are jobs that experienced people, who know it too well, really have a hard time with. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gnetlist complains of unconnected pins
Hi Ales, On Wednesday 27 September 2006 00:14, Ales Hvezda wrote: share/gEDA/sym/supervisor/adm707.sym share/gEDA/sym/opto/hcpl-4534-1.sym I'm going to fix them. Thanks for fixing these symbols Werner. Certainly enhancing gsymcheck to catch such errors would be quite handy. I've filed a feature request on SF: http://sourceforge.net/tracker/index.php?func=detailaid=1565593group_id=161080atid=818429 Any volunteer? Regards Werner ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB missing grid on far side?
Hi Dan, On Wednesday 27 September 2006 00:03, Dan McMahill wrote: Werner Hoch wrote: The checking for gdImage... requires the libjpeg-devel rpm which was not in the buildrequires of the rpmspec-file yet. but shouldn't it be in the requirement for gdlib not for pcb directly? Yes, in SuSE 10.1 the dependancies are ok: gd-devel requires libjpeg-devel libfreetype2-devel and libpng-devel, ... on 10.0 they missed: libjpeg-devel on 9.3 they missed: libjpeg-devel and libfreetype2-devel Looks to me like the rpm for gdlib is broken. For example I'll bet if you do ldd /path/to/libgd.so you'll see that -lgd requires -ljpeg. your right. [...] I'll file a bug report on the Novell tracker, but it's not very likely that they will fix the old rpm packages. regards Werner ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem: how to connect signals between sheets?
Hello everyone: Sorry, but I'm having a little trouble figuring this one out. My circuit diagram is on two sheets. I need to connect a small number of signals between them. I found the symbols input-1 and output-1 which looked just like the ones that people use for this purpose. I added them to the circuit and designated them IO1 through IO6. One one board, IO1 through IO3 were inputs and IO4 through IO6 were outputs, on the other, vice versa. Of course the net list does not generate correctly; I have to edit it by hand to merge the twelve nets with IO designators in them. Also I ended up defining slots, since gschem didn't like the duplicate designators. So now the program complains about incomplete slot definitions. I'm sure there's something I'm missing. Is there a special property or something I can define for these symbols so this works correctly? Thanks! Vaughn T ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
There's no special symbol for connections between sheets: just attach a netname= attribute to each net you want to connect. All nets with the same netname wind up connected together in the netlist. On Sep 27, 2006, at 7:36 AM, Vaughn Treude wrote: Hello everyone: Sorry, but I'm having a little trouble figuring this one out. My circuit diagram is on two sheets. I need to connect a small number of signals between them. I found the symbols input-1 and output-1 which looked just like the ones that people use for this purpose. I added them to the circuit and designated them IO1 through IO6. One one board, IO1 through IO3 were inputs and IO4 through IO6 were outputs, on the other, vice versa. Of course the net list does not generate correctly; I have to edit it by hand to merge the twelve nets with IO designators in them. Also I ended up defining slots, since gschem didn't like the duplicate designators. So now the program complains about incomplete slot definitions. I'm sure there's something I'm missing. Is there a special property or something I can define for these symbols so this works correctly? Thanks! Vaughn T ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user John Doty Noqsi Aerospace, Ltd. [EMAIL PROTECTED] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GEDA code sprint reminder -- one week from today!
Harry Eaton wrote: I have been sprinting on my own quite a bit recently solving the long-standing problem of dead copper in polygons. Special applause from me for this effort! :-) It's in a cvs branch tag named clipper. I'll test it with my next project. Will be in about 2 weeks... ---(kaimartin)--- -- Kai-Martin Knaak [EMAIL PROTECTED] http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GEDA code sprint reminder -- one week from today!
If you really are too new. how about working on beginner documentation? You can also help a lot be answering beginner questions on the email lists. Or usability. That kind of feedback works well in interactive settings. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Clearance in polygons
Where is this default clearance set? Under Route Style there's just a clearance, set at 10 mil. That's it. Note that clearance is defined as what you add to thickness to get the cut thickness. I.e. for a 5 mil gap, you need a 10 mil clearance. For a 6 mil gap, you'd need a 12 mil clearance, etc. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote: I also hadn't yet figured out how to connect Vcc to +5V and Vss to ground. Googling I found a reference to using netname for this purpose. So I added the netname Vcc to one of the +5V symbols and Vss to one of the ground symbols, and yet these aren't hooking up either. I wonder if there's something else I might be missing. You are probably using schematic symbols with embedded power pins that have names that differ from your netnames. Use a text editor and look for the net attributes in the symbols you are using. If you search the list you will see various discussions of embedded power pins. It is best to Just say no! to embedded power pins ;-) (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Clearance in polygons
Peter Baxendale wrote: Where is this default clearance set? Under Route Style there's just a clearance, set at 10 mil. The Route Style dialog refers to the current style. Chose a different style and Route Style dialog will allow you to change its default properties. Couldn't see any reference to polygon clearance anywhere else. Clearance track-polygon is the same as clearance track-track. ---(kaimartin)--- -- Kai-Martin Knaak [EMAIL PROTECTED] http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Clearance in polygons
DJ Delorie wrote: That's it. Note that clearance is defined as what you add to thickness to get the cut thickness. I.e. for a 5 mil gap, you need a 10 mil clearance. For a 6 mil gap, you'd need a 12 mil clearance, etc. This makes me nervous. My fab requires 6 mil minimum distance. I routed my board with clearence=10mil on all route styles. Yet, the DRC feels fine with minimum copper distance set to 6 mil... Just measured with the help of [ctrl-m]: 6 mil clearance translates to 6 mil gap from copper to copper (phew!). ---(kaimartin)--- -- Kai-Martin Knaak [EMAIL PROTECTED] http://lilalaser.de/blog ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Clearance in polygons
Now I'm confused. I've ended up with some of the tracks showing a polygon clearance of 10 mil (in an object report) whilst others show 5 mil. After a little experimentation it seems that if I draw a track manually using the signal style (with clearance set to 10 mil and line width set to 10 mil) I get 10 mil spacing between the edge of my track and the polygon. If I autoroute using the same style I get 5 mil spacing between the edge of the track and the polygon. Should they be different, and if so, why? On Wed, 2006-09-27 at 10:45 -0400, DJ Delorie wrote: Where is this default clearance set? Under Route Style there's just a clearance, set at 10 mil. That's it. Note that clearance is defined as what you add to thickness to get the cut thickness. I.e. for a 5 mil gap, you need a 10 mil clearance. For a 6 mil gap, you'd need a 12 mil clearance, etc. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Clearance in polygons
This makes me nervous. My fab requires 6 mil minimum distance. I routed my board with clearence=10mil on all route styles. Yet, the DRC feels fine with minimum copper distance set to 6 mil... Just measured with the help of [ctrl-m]: 6 mil clearance translates to 6 mil gap from copper to copper (phew!). Hmmm... maybe the dialog box converts, then. I know in the .pcb file itself it's the way I described. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On Wed, 2006-09-27 at 07:48, John Luciani wrote: On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote: I also hadn't yet figured out how to connect Vcc to +5V and Vss to ground. Googling I found a reference to using netname for this purpose. So I added the netname Vcc to one of the +5V symbols and Vss to one of the ground symbols, and yet these aren't hooking up either. I wonder if there's something else I might be missing. You are probably using schematic symbols with embedded power pins that have names that differ from your netnames. Use a text editor and look for the net attributes in the symbols you are using. If you search the list you will see various discussions of embedded power pins. I've opened the different IC symbols and displayed the details. Some use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a +5V symbol and the other two to the ground symbol. Didn't help, sad to say. It is best to Just say no! to embedded power pins ;-) Sorry, I'm a newbie, I don't know how to do that. If it involves redesigning existing symbols, I don't have time to change them all. If there is another way to do it, I'm open to suggestions. Vaughn (* jcl *) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GEDA code sprint reminder -- one week from today!
Harry - These are very welcome additions to PCB. (6) especially will save me literally hours of manual checking. Thanks! Joe T Harry Eaton wrote: Unfortunately, I have family commitments so I won't be able to participate in the code sprint. I have been sprinting on my own quite a bit recently solving the long-standing problem of dead copper in polygons. I have alpha-quality code up on sourceforge now and it could use some testing, so if you're fairly skilled with pcb and would like to help find all the new bugs I know must be lurking, give it a spin. It's in a cvs branch tag named clipper. Some features it has: (1) Gerbers are always positive-only, which should increase the number of fab vendors that are happy with them. (2) Thermals can be diagonal or horizontal/vertical or solid to the plane (shift-click with the thermal tool to cycle through the styles) (3) Thermal fingers are user-editable. Treat them like normal lines in the layout. (4) Any dead copper in polygons is automatically removed. Select check polygons in the settings to view an outline of removed copper) (5) The rats-nest will no longer believe objects connected to polyogn islands are still connected to the polygon. (6) Thermal fingers are checked for DRC violations. There is still a little work to be done to complete the DRC code, but it should mostly be functional. There is no need to concentrate on testing the features above - the changes affected many areas of the code, so bugs may well exist in operations that appear to be unrelated to these features. Cheers, harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
On Wed, 2006-09-27 at 07:48, John Luciani wrote:
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
I also hadn't yet figured out how to connect Vcc to +5V and Vss to
ground. Googling I found a reference to using netname for this
purpose. So I added the netname Vcc to one of the +5V symbols and Vss
to one of the ground symbols, and yet these aren't hooking up either.
I wonder if there's something else I might be missing.
You are probably using schematic symbols with embedded power pins that have
names that differ from your netnames. Use a text editor and look for the net
attributes in the symbols you are using. If you search the list you
will see various discussions of embedded power pins.
I've opened the different IC symbols and displayed the details. Some
use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a
+5V symbol and the other two to the ground symbol. Didn't help, sad to
say.
You should be able to connect these. Create a *simple* schematic using
embedded symbols and post it. To get embedded symbols select the
Embed component in schematic option in the Select component
window.
It is best to Just say no! to embedded power pins ;-)
Sorry, I'm a newbie, I don't know how to do that. If it involves
redesigning existing symbols, I don't have time to change them all. If
there is another way to do it, I'm open to suggestions.
The script below will create a symbol without embedded power connections
for each symbol file found in the current working directory. See the script
for usage information. Backup your files in the CWD just in case.
(* jcl *)
-
http://www.luciani.org
#!/usr/bin/perl
# Copyright (C) 2006 John C. Luciani Jr.
# This program may be distributed or modified under the terms of
# version 0.2 of the No-Fee Software License published by
# John C. Luciani Jr.
# A copy of the license is at the end of this file.
#
# For each symbol in the current directory this script creates a new
# symbol without the embedded power connections and a new symbol with
# only the power pins. The symbol without the power pins has an _np
# suffix. The symbol containing only the power pins has a _pwr
# suffix. Since many symbols contain the same pinout for power pins
# the power pin symbol is a symlink to a generic symbol.
# This script only works for symbols with one power net and one
# ground. The routine that creates the power pin symbols has
# specifications for only two pins.
use strict;
use warnings;
use Carp;
use IO::File;
# @Power_pins ... each element of this array is an anonymous hash containing
# the filename, Vcc pin number, and GND pin number.
# @Net_names names of the power nets to remove.
# @Files all of the symbol files in the current directory.
my @Net_names = $#ARGV == -1 ? qw(Vcc GND) : @ARGV;
my @Files = *.sym;
my @Power_pins;
# To find the power pins we look for a text line followed by a
# net=NET_NAME line where NET_NAME is an element in the array
# @Net_names
foreach my $filename (@Files) {
# skip the files that were created by this script.
next if $filename =~ /_np.sym$/; # already done
next if $filename =~ /^pwr/; # generic power symbol
next if $filename =~ /_pwr.sym$/; # power symbol symlink
print $filename\n;
@ARGV = ($filename);
my $np_filename = $filename;
$np_filename =~ s/\.sym/_np.sym/;
my %pins; # contains the filename and power pins for the current symbol
open(OUT, $np_filename) || croak Could not open $np_filename
for output: $!;
while () {
print(OUT), next unless /^\s*T/;
# Found a text line.
my $text = $_;
my $line = ;
my $power_net_p;
foreach my $net_name (@Net_names) {
next unless $line =~ /^\s*net\s*=\s*$net_name\s*:\s*(\d+)/;
$pins{$net_name} = $1;
$power_net_p = 1;
last;
}
print(OUT $text, $line) unless defined $power_net_p;
}
close(OUT) || croak Could not close $np_filename;
push @Power_pins, { filename = $filename, %pins };
}
# gschem constants --- DO NOT CHANGE THESE
use constant NORMAL_PIN = 0;
use constant FIRST_POINT_ACTIVE = 0;
use constant VISIBLE = 1;
use constant SHOW_VALUE = 1;
use constant ANCHOR_SW = 0;
use constant ANCHOR_NW = 2;
use constant ANCHOR_N = 5;
use constant ANCHOR_S = 3;
use constant ANCHOR_SE = 6;
use constant ANCHOR_NE = 8;
use constant TEXT_FORMAT = T %i %i %i %i %i %i %i %i %i\n%s\n;
# Change these constants and values in the %Pin_param
# hash to change the power symbol appearance.
use constant REFDES_X2_OFFSET = -25;
use constant REFDES_Y2_OFFSET = 25;
use constant REFDES_ALIGN = ANCHOR_SE;
use constant TEXT_COLOR = 5;
use constant TEXT_SIZE = 6;
use constant PIN_LENGTH = 100;
use constant PIN_SPACING = 300;
use constant PIN_COLOR = 5;
use constant SYM_OFFSET = 100;
# hash key 0 corresponds to the first power net.
#
Re: gEDA-user: gschem: how to connect signals between sheets?
On Wed, 2006-09-27 at 09:59, John Luciani wrote:
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
On Wed, 2006-09-27 at 07:48, John Luciani wrote:
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
I also hadn't yet figured out how to connect Vcc to +5V and Vss to
ground. Googling I found a reference to using netname for this
purpose. So I added the netname Vcc to one of the +5V symbols and Vss
to one of the ground symbols, and yet these aren't hooking up either.
I wonder if there's something else I might be missing.
You are probably using schematic symbols with embedded power pins that
have
names that differ from your netnames. Use a text editor and look for the
net
attributes in the symbols you are using. If you search the list you
will see various discussions of embedded power pins.
I've opened the different IC symbols and displayed the details. Some
use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a
+5V symbol and the other two to the ground symbol. Didn't help, sad to
say.
You should be able to connect these. Create a *simple* schematic using
embedded symbols and post it. To get embedded symbols select the
Embed component in schematic option in the Select component
window.
Does it only work when all the components are embedded? Sounds like
that could make the resulting file pretty big.
I've attached the SCH file rather than putting it in line - hope that's
OK. I've embedded all the components, and it still doesn't consolidate
+5V and Vcc.
I'm using gschem version 20060123. Do any of the versions have known
bugs in this respect?
Vaughn T
It is best to Just say no! to embedded power pins ;-)
Sorry, I'm a newbie, I don't know how to do that. If it involves
redesigning existing symbols, I don't have time to change them all. If
there is another way to do it, I'm open to suggestions.
The script below will create a symbol without embedded power connections
for each symbol file found in the current working directory. See the script
for usage information. Backup your files in the CWD just in case.
(* jcl *)
-
http://www.luciani.org
#!/usr/bin/perl
# Copyright (C) 2006 John C. Luciani Jr.
# This program may be distributed or modified under the terms of
# version 0.2 of the No-Fee Software License published by
# John C. Luciani Jr.
# A copy of the license is at the end of this file.
#
# For each symbol in the current directory this script creates a new
# symbol without the embedded power connections and a new symbol with
# only the power pins. The symbol without the power pins has an _np
# suffix. The symbol containing only the power pins has a _pwr
# suffix. Since many symbols contain the same pinout for power pins
# the power pin symbol is a symlink to a generic symbol.
# This script only works for symbols with one power net and one
# ground. The routine that creates the power pin symbols has
# specifications for only two pins.
use strict;
use warnings;
use Carp;
use IO::File;
# @Power_pins ... each element of this array is an anonymous hash containing
# the filename, Vcc pin number, and GND pin number.
# @Net_names names of the power nets to remove.
# @Files all of the symbol files in the current directory.
my @Net_names = $#ARGV == -1 ? qw(Vcc GND) : @ARGV;
my @Files = *.sym;
my @Power_pins;
# To find the power pins we look for a text line followed by a
# net=NET_NAME line where NET_NAME is an element in the array
# @Net_names
foreach my $filename (@Files) {
# skip the files that were created by this script.
next if $filename =~ /_np.sym$/; # already done
next if $filename =~ /^pwr/; # generic power symbol
next if $filename =~ /_pwr.sym$/; # power symbol symlink
print $filename\n;
@ARGV = ($filename);
my $np_filename = $filename;
$np_filename =~ s/\.sym/_np.sym/;
my %pins; # contains the filename and power pins for the current symbol
open(OUT, $np_filename) || croak Could not open $np_filename
for output: $!;
while () {
print(OUT), next unless /^\s*T/;
# Found a text line.
my $text = $_;
my $line = ;
my $power_net_p;
foreach my $net_name (@Net_names) {
next unless $line =~ /^\s*net\s*=\s*$net_name\s*:\s*(\d+)/;
$pins{$net_name} = $1;
$power_net_p = 1;
last;
}
print(OUT $text, $line) unless defined $power_net_p;
}
close(OUT) || croak Could not close $np_filename;
push @Power_pins, { filename = $filename, %pins };
}
# gschem constants --- DO NOT CHANGE THESE
use constant NORMAL_PIN = 0;
use constant FIRST_POINT_ACTIVE = 0;
use constant VISIBLE = 1;
use constant SHOW_VALUE = 1;
use constant ANCHOR_SW = 0;
use constant ANCHOR_NW = 2;
use constant ANCHOR_N = 5;
use constant ANCHOR_S =
Re: gEDA-user: gschem: how to connect signals between sheets?
Hi Vaughn, Vaughn Treude wrote: I've opened the different IC symbols and displayed the details. Some use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a +5V symbol and the other two to the ground symbol. Didn't help, I've embedded all the components, and it still doesn't consolidate +5V and Vcc. John was only meaning embedding symbols in a .sch file for purposes of sharing it with us. I'm using gschem version 20060123. Do any of the versions have known bugs in this respect? Not that I know...this is a feature vs. bug issue. This feature of gschem and the existing libraries means you will have to learn to edit your own symbols to suit your style. If you use embedded power pins you are forced to make each symbol unique for the power names you are using in all pages of your schematics because gschem and gnetlist make and use flat netlists where signal names (attribute=netname) are connected across pages. It is best to Just say no! to embedded power pins ;-) Sorry, I'm a newbie, I don't know how to do that. If it involves redesigning existing symbols, I don't have time to change them all. If there is another way to do it, I'm open to suggestions. John is suggesting you Just say no in a wholesale way right now before you get bogged down in them by using his script: John Griessen The script below will create a symbol without embedded power connections for each symbol file found in the current working directory. See the script for usage information. Backup your files in the CWD just in case. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
On Wed, 2006-09-27 at 09:59, John Luciani wrote:
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
On Wed, 2006-09-27 at 07:48, John Luciani wrote:
On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote:
I also hadn't yet figured out how to connect Vcc to +5V and Vss to
ground. Googling I found a reference to using netname for this
purpose. So I added the netname Vcc to one of the +5V symbols and Vss
to one of the ground symbols, and yet these aren't hooking up either.
I wonder if there's something else I might be missing.
You are probably using schematic symbols with embedded power pins that
have
names that differ from your netnames. Use a text editor and look for the
net
attributes in the symbols you are using. If you search the list you
will see various discussions of embedded power pins.
I've opened the different IC symbols and displayed the details. Some
use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a
+5V symbol and the other two to the ground symbol. Didn't help, sad to
say.
You should be able to connect these. Create a *simple* schematic using
embedded symbols and post it. To get embedded symbols select the
Embed component in schematic option in the Select component
window.
Does it only work when all the components are embedded? Sounds like
that could make the resulting file pretty big.
No. Embedding components is useful when sending your schematic to someone
else who may not use the library that you are using.
I've attached the SCH file rather than putting it in line - hope that's
OK. I've embedded all the components, and it still doesn't consolidate
+5V and Vcc.
The problem is that you did not connect your power symbols to their
respective components with a net. You have the pin ends against each other.
If you move the power symbols and use net connections the schematic will
netlist and load into PCB.
The schematic below will netlist and load into PCB (provided that you
update the footprint attributes to match footprints on your system).
(* jcl *)
--
http://www.luciani.org
v 20050313 1
C 6600 83300 1 0 0 EMBEDDEDgnd-1.sym
[
P 6700 83400 6700 83600 1 0 1
{
T 6758 83461 5 4 0 1 0 0 1
pinnumber=1
T 6758 83461 5 4 0 0 0 0 1
pinseq=1
T 6758 83461 5 4 0 1 0 0 1
pinlabel=1
T 6758 83461 5 4 0 1 0 0 1
pintype=pwr
}
L 6600 83400 6800 83400 3 0 0 0 -1 -1
L 6655 83350 6745 83350 3 0 0 0 -1 -1
L 6680 83310 6720 83310 3 0 0 0 -1 -1
T 6900 83350 8 10 0 0 0 0 1
net=GND:1
]
{
T 6600 83300 5 10 1 1 0 0 1
netname=GND
}
C 6700 86900 1 0 0 EMBEDDED5V-plus-1.sym
[
P 6900 86900 6900 87100 1 0 0
{
T 6950 86950 5 6 0 1 0 0 1
pinnumber=1
T 6950 86950 5 6 0 0 0 0 1
pinseq=1
T 6950 86950 5 6 0 1 0 0 1
pinlabel=1
T 6950 86950 5 6 0 1 0 0 1
pintype=pwr
}
L 6750 87100 7050 87100 3 0 0 0 -1 -1
T 6775 87150 9 8 1 0 0 0 1
+5V
T 7000 86900 8 8 0 0 0 0 1
net=+5V:1
]
{
T 6700 86900 5 10 1 1 0 0 1
netname=Vcc
}
N 4700 85400 4400 85400 4
N 4400 85400 4400 85200 4
N 4400 85200 6100 85200 4
N 6100 84500 6100 85200 4
N 4800 84700 4500 84700 4
N 4500 84700 4500 85000 4
N 4500 85000 6500 85000 4
N 6500 85000 6500 85600 4
N 6500 85600 6000 85600 4
C 4700 85100 1 0 0 EMBEDDED7400-1.sym
[
L 5000 85300 5000 85900 3 0 0 0 -1 -1
T 5000 85100 9 8 1 0 0 0 1
7400
L 5000 85900 5400 85900 3 0 0 0 -1 -1
T 5200 86000 5 10 0 0 0 0 1
device=7400
T 5200 86200 5 10 0 0 0 0 1
slot=1
T 5200 86400 5 10 0 0 0 0 1
numslots=4
T 5200 86600 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 5200 86800 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 5200 87000 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 5200 87200 5 10 0 0 0 0 1
slotdef=4:12,13,11
L 5000 85300 5400 85300 3 0 0 0 -1 -1
A 5400 85600 300 270 180 3 0 0 0 -1 -1
V 5750 85600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 5800 85600 6000 85600 1 0 1
{
T 5800 85650 5 8 1 1 0 0 1
pinnumber=3
T 5800 85550 5 8 0 1 0 2 1
pinseq=3
T 5650 85600 9 8 0 1 0 6 1
pinlabel=Y
T 5650 85600 5 8 0 1 0 8 1
pintype=out
}
P 5000 85400 4700 85400 1 0 1
{
T 4900 85450 5 8 1 1 0 6 1
pinnumber=2
T 4900 85350 5 8 0 1 0 8 1
pinseq=2
T 5050 85400 9 8 0 1 0 0 1
pinlabel=B
T 5050 85400 5 8 0 1 0 2 1
pintype=in
}
P 5000 85800 4700 85800 1 0 1
{
T 4900 85850 5 8 1 1 0 6 1
pinnumber=1
T 4900 85750 5 8 0 1 0 8 1
pinseq=1
T 5050 85800 9 8 0 1 0 0 1
pinlabel=A
T 5050 85800 5 8 0 1 0 2 1
pintype=in
}
T 5200 87350 5 10 0 0 0 0 1
footprint=DIP14
T 5200 87550 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 5200 87950 5 10 0 0 0 0 1
net=Vcc:14
T 5200 88150 5 10 0 0 0 0 1
net=GND:7
T 5200 87750 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
]
{
T 5000 86000 5 10 1 1 0 0 1
refdes=U1
T 4700 85100 5 10 0 0 0 0 1
slot=1
T 4700 85100 5 10 0 0 0 0 1
footprint=DIP-14-300
}
C 6600 84700 1 270 0 EMBEDDEDresistor-1.sym
[
L 6800 84100 6600 84200 3 0 0 0 -1 -1
L 6600 84200 6800 84300 3 0 0 0 -1 -1
L 6800 84300 6600 84400 3 0 0 0 -1 -1
L 6600 84400 6800 84500 3 0 0 0 -1 -1
T 7000 84400 5 10 0 0 270 0 1
device=RESISTOR
L
Re: gEDA-user: gschem: how to connect signals between sheets?
Hi Vaughn, I've opened your schematic and used the en command to make symbol attributes visible and I see net=GND:7 net=Vcc:14 on the nand gates in yellow, meaning it is an attached attribute. you will have to change that to use your chosen names, or remove them with John's script, then use djboxsym to create a symbol with pins 7 GND 14 +5V place that symbol in your schematic with the same U? to define power pins other way is to edit the symbol with gschem and change attached net=Vcc:14 to be net=+5V:14 do the et command and give it 0 save, maybe rename, put in a local library of your own. John G Vaughn Treude wrote: I've attached the SCH file rather than putting it in line - hope that's OK. I've embedded all the components, ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On 9/27/06, John Griessen [EMAIL PROTECTED] wrote: you will have to change that to use your chosen names, or remove them with John's script, then use djboxsym to create a symbol with pins 7 GND 14 +5V My script creates these power pin symbols automatically. I forgot to include the following notes in my original email I created a script that takes a logic symbol with embedded Vcc and GND nets and creates (1) a new symbol with the power nets removed and (2) a new symbol with two power pins. My plan is to place power symbols (and decoupling caps) for each IC in a separate section of my schematic. Since many symbols contain the same pinout for power pins the power pin symbol is a symlink to a generic symbol. The new symbol without power pins have a _np suffix. The symbol containing the power pins has a _pwr suffix. For example the 7400-1.sym (with Vcc at pin 14, GND at pin 7) would produce the files --- 7400-1_np.sym 7400.sym without power pins pwr_Vcc_14_GND_7.sym refdes, power pin, ground pin 7400-1_pwr.symsymlink to pwr_Vcc_14_GND_7.sym (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
snip Does it only work when all the components are embedded? Sounds like that could make the resulting file pretty big. No. Embedding components is useful when sending your schematic to someone else who may not use the library that you are using. I've attached the SCH file rather than putting it in line - hope that's OK. I've embedded all the components, and it still doesn't consolidate +5V and Vcc. The problem is that you did not connect your power symbols to their respective components with a net. You have the pin ends against each other. If you move the power symbols and use net connections the schematic will netlist and load into PCB. The schematic below will netlist and load into PCB (provided that you update the footprint attributes to match footprints on your system). (* jcl *) You're right, I goofed. :-) It's easy to miss that because the red square goes away making it look like the two components connected. I did a netlist of the modified file and it looked the same as the previous one I had. Perhaps it gets modified when it's sucked into PCB. I'm not actually averse to creating custom devices; In the last couple of weeks I've created about a dozen gschem symbols and at least that many pcb footprints. It's just that I'm getting tired of all the work! :-) I'm beginning to think it may be worthwhile to convert the 14 or so devices on my existing schematic to a no embedded net format. Your script would make that easier; I was afraid I'd have to do it manually. I like the idea of having the +5 and ground connections shown with the decoupling capacitor. It's unfortunate it requires a separate symbol, but I don't think there's any really clean way to approach it, considering that the power pins don't fit into the slot concept. I did something similar when I created a symbol for the 2013 open-collector driver device. There's a pin for a common pull up (which does not connect directly to the power), and I didn't really know how to implement the embedded nets, so I just created a separate triangular buffer symbol which had an extra pin on it, and put just one instance of that on my schematic. Thanks to you, and to John G., for all your help! Vaughn ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem: how to connect signals between sheets?
On Wed, 2006-09-27 at 14:54, John Luciani wrote: On 9/27/06, Vaughn Treude [EMAIL PROTECTED] wrote: snip Does it only work when all the components are embedded? Sounds like that could make the resulting file pretty big. No. Embedding components is useful when sending your schematic to someone else who may not use the library that you are using. I've attached the SCH file rather than putting it in line - hope that's OK. I've embedded all the components, and it still doesn't consolidate +5V and Vcc. The problem is that you did not connect your power symbols to their respective components with a net. You have the pin ends against each other. If you move the power symbols and use net connections the schematic will netlist and load into PCB. The schematic below will netlist and load into PCB (provided that you update the footprint attributes to match footprints on your system). (* jcl *) You're right, I goofed. :-) It's easy to miss that because the red square goes away making it look like the two components connected. I did a netlist of the modified file and it looked the same as the previous one I had. Perhaps it gets modified when it's sucked into PCB. I'm not actually averse to creating custom devices; In the last couple of weeks I've created about a dozen gschem symbols and at least that many pcb footprints. It's just that I'm getting tired of all the work! :-) Managing a component library is a fair amount of work that is not much fun to do. There is no way around it. For schematic symbols you need to verify that the symbols match the manufacturer specification sheet. For PCB footprints you need to verify that the footprints match the manufacturerspecifications and your manufacturing process. I am surprised that you needed to create that many footprints since there are quite a few already created. Have you checked out gedasymbols.org and my website http://www.luciani.org/geda/pcb/pcb-footprint-list.html I did not know you had such a big collection of footprints! It would have saved me some work. My circuit has a few off-beat components on it, but I was surprised to see that a number of standard SMD components were not in there, and I ended up creating them. I'm beginning to think it may be worthwhile to convert the 14 or so devices on my existing schematic to a no embedded net format. Your script would make that easier; I was afraid I'd have to do it manually. I like the idea of having the +5 and ground connections shown with the decoupling capacitor. It's unfortunate it requires a separate symbol, but I don't think there's any really clean way to approach it, considering that the power pins don't fit into the slot concept. Having a separate symbol is a little more work but is not too bad. We have discussed (at the Freedog meetings) having multiple types of slots in a component symbol. I hate to be a pest on this issue, but I never did get gnetlist to handle the embedded nets correctly. Not that I mind that much changing the symbols to eliminate embedded power pins (I'll do whatever works) but I don't know how else to handle the connections between the sheets of the schematic. I can't afford the time to keep manually correcting the netlists. I don't know what version of gnetlist I'm using, as the usage message didn't seem to include version info. But am I correct in using the -g PCB flag? I don't see what I'm doing wrong, but there must be something. When I netlist the modified SCH file you sent me still does not consolidate the +5V and Vcc nets. I get the following result: +5V R1-1 unnamed_net3U1-10 R1-2 R2-1 GND R2-2 U1-7 Vcc U1-14 unnamed_net2U1-6 U1-2 unnamed_net1U1-9 U1-4 U1-3 Besides gnetlist, is there some other way to generate a netlist? Thanks again, Vaughn Thanks to you, and to John G., for all your help! Your welcome. (* jcl *) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
