Re: gEDA-user: thermals on layer groups
With my setting of having the polygons on an extra layer I'm not able to place thermals. When trying this, the command is simply ignored. The thermal tool places thermals to the active layer. You need to have the layer that the polygon is actually on as the active layer in order to place a thermal.The thermal is a feature of the polygon, not of the pin/via. If the command is being ignored, it is because the polygon is not on the actual layer (not just group) that is active for drawing. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Funny pad rotation
I thought it was a very well-known feature; it was reported in 2007 ([1]http://sourceforge.net/tracker/?func=detailaid=1800872group_id =73743atid=538811); Yes, but that bug report came with a request explicitly asking that it not be fixed! References 1. http://sourceforge.net/tracker/?func=detailaid=1800872group_id=73743atid=538811 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: toporouter update
Can you guys keep this on the geda-dev list in future.. it is always fun to see how things are progressing. Certainly, if Anthony and I discuss anything now that GSoc is not to be. Previously, I couldn't subscribe or send to the geda-dev list (or user for that matter). That's why Anthony and I were discussing off list. It was a comcast thing. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter Update
I'm not going to stop working on the toporouter (greenlight?) just because Google didn't fund us. If people keep hassling me, I'll probably find the time for small commits here and there.. e.g., most of my work last year was an answer to some scathing criticism from Harry.. I *had* to do something after that =) Gosh, I was thinking about making a parody of your website comparing the two routers in pcb, where I would show test cases where boards had SMD parts on both sides and the toporouter couldn't route it but the autorouter could, then some with some existing hand-routing on the board, one with a ground plane going unused by the toporouter, etc. But I thought that would be mean so I didn't do it. (Even though I figured it would goad you in to fixing those problems). Seriously, I didn't think my criticisms were scathing, they were meant to be helpful. In any event, I'm still happy to give my blunt assessment and crazy ideas going forward. Cheers, harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: geda-user Digest, Vol 46, Issue 27
I submitted my first PCB bug report to SF last month (#2946254), and shortly after added a patch that fixed the problem. I must admit that the lack of response was discouraging - but I fully appreciate that the developers are time poor (I am also!). BTW thank you to Rikster, for taking the time to try the patch confirm that it fixes the bug, and posting the result back to SF :-) ... The patch looks good to me (although I've only skimmed it). It might warrant a definition of what a freckle is, if that term isn't use elsewhere. The optimisation is probably fine to add. A complete fix would address the issue in the auto-router as well. I'm happy to apply the patch, but I'm heading home now, as its getting late. Someone bug me to apply the patch! It looks to me like the SQ() macro risks integer overflow when squaring the lengths. I too only glanced at the patch so maybe I'm wrong. This is one of the difficulties in getting patches on a fast track. The internals of pcb are ugly and hard to understand in a lot of ways, and even many of the developers don't fully understand them (myself included these days!!). pcb has a huge amount of cruft from its 20 year life. It is extremely easy to create a patch that on its face looks good, appears to fix the problem at hand and passes certain tests, BUT, introduces ugly lurking bugs that can be a nightmare to find and resolve. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb doesn't find my pins
On Fri, 2010-03-05 at 00:28 +, Kai-Martin Knaak wrote: On Wed, 03 Mar 2010 20:40:54 +, Peter Clifton wrote: Perhaps the pin identifier U102-J1-1 is causing issues. So this may be another incarnation of the hyphen-nastiness? Would it be possible to fix this tendency to misinterpret hyphens in names once and for all? So is this supposed to be element U102-J1 's pin 1, or is the element U102 's pin J1-1. The point is that we chose to use - as a name/number separator. It is reasonable to choose a single reserved character for that purpose in a lightweight protocol like our netlist format. We could of course allow the escape that -- becomes a literal hyphen in the string (which I don't think we've done). That won't solve the instant problem until both the netlister and netlist reader are changed to add that facility. Frankly I don't see it as much of a problem to just treat it as a reserved character and leave the code alone. But there are always people that want to put / in their filenames and name their variable if in C code. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: can't route to TSSOP
Hi, First time using TSSOP48. All rats, except those to/from TSSOP48, were successfully autorouted. Is this a limitation in version 20080202 of pcb, or am I missing something? Stan The most likely reason is that the pins themselves are violating the spacing rule that you've allowed the autorouter. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: arcs in pcb
Is there any way to get better resolution? One degree is 25 mils at my radius. Sure, draw yourself a nice short straight segment. If your arc is extra ordinarily thick, draw a trapezoidal polygon instead. The point here is that even a 1 degree arc at your radius is virtually indistinguishable from a 25mil straight line (the worst case centerline is +/- 0.11 mils from the straight approximation) unless it is extremely thick in which case it is virtually indistinguishable from a trapezoid. Smaller angles are even more like straight lines. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blackboxing pcb
Hi! Do you mean that you want the simple PCB to be a fragment which gets inserted into other designs? (option 2). This one. Pcb can load a .pcb file with the load element to buffer command, which you can thing rotate, move to the other side, etc and then paste wherever you like (again and again). You'll still have a problem getting the netlist to see that collection as a component. That will be trouble: the netlist would need to be flattened (probably meaning the schematic symbol will need to understand the internals) and then you have to have a decent means of getting the right unique element names both in the netlist and the pcb elements. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: little slivers
Is there some way I can easily get rid of the little slivers of copper left between traces when doing pours? Not without adjusting the clearance on the adjacent lines to squeeze out the slivers. I've considered several times how to fix this, and I can see options for doing in in a post-processing step, but that's not really in line with PCB's other polygon updates,which are all done live. Works with my pours branch (which does island removal), but that isn't ready for merge yet. The main branch already removes islands (at least its supposed to), so I presume the concern here is with fingers connecting to the main polygon. At present there isn't a way to enforce (or check for that matter) DRC on the polygons. This is something that needs to be done. I plan to take this on once I have some time to work on the code again, but that might be over a year away. My basic idea for DRC enforcement is to subtract appropriate lines along the border of the polygon (and its holes), remove the islands, then add back lines along the new contour. This should make too-thin fingers, sharp bends and pointy protrusions disappear. Such an operation would be too expensive to do with every polygon edit operation so it would be as separate step done during DRC or when manually invoked. In the mean time, if you plan to flood fill a region of many tracks, then I recommend that you either fill it manually, or fixup the problems manually. Cheers, harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: tiny slivers
Okay, so, how can I increase the clearance on all holes without doing each and every one individually? Select whatever you need larger clearances around, then do :ChangeClearSize(selected,+x,mil) where x is the amount of extra clearance you need (in mils) to make the slivers disappear. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb flip-sides
Can you confirm that version still works as you wanted? It does -- sort of. The command pcb -x eps --action-string 'DISPLAY(Value)' --eps-file foo.eps bar.pcb does indeed output a layout with values displayed, even if the last saved version of pcb showed refdeses. However, not all actions have the expected effect with the export eps export HID. For example, --action-string 'SwapSides()' does not seem to change the output in any way. This particular action string option works fine if I present it to the GTK HID. My version of the patch showed the same room for improvement. Does the action itself know whether or not the current HID is a GUI? You need to use a V argument, i.e. SwapSides(V). With no argument, the lesstif gui does an x-ray view, effectively only altering the layer stackup. The lesstiff gui supports 4 ways to SwapSides. The GTK hid should support them as well, but it doesn't. h. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: .pcb viewer
Does geda have a .pcb file viewer, such as is output by the ExpressPCB free software for windows? I've got a small tabletop milling machine, and have been asked to do a board that is about half the size of a postage stamp. And, if so, can it convert a .pcb into a couple of .ngc's for feeding a milling machine, one for each side of the board? I think there may be some misunderstanding what you are asking here. I interpret your question to be The windows program ExpressPCB has created a .pcb file. Does geda have a viewer for this file? Now I don't know anything about ExpressPCB, but it probably creates files in its own (probably proprietary) format and gives them a .pcb suffix. Geda has a program for designing boards called pcb, and it is common practice to use a .pcb suffix for files it produces in its (open) native format. It is highly unlikely that there is any reasonable similarirty between the two file formats. So if you have a design created with ExpressPCB that you want to work with, I think Peter's answer won't help you. You could instead redesign the board using geda's pcb (I can't believe I typed that) and then use Peter's suggestions. Cheers, harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: autorouter enhancements: net characteristics
Stefan Salewski m...@ssalewski.de wrote: I wonder if the PCB autorouter should be more closely bound to the gschem schematics. For example, in the schematics we may specify priority of nets (fast signals, power, ...), trace width or clearance for net segments. Maybe by attributes? I have no idea how commercial EDA software handles this. This is the point of (6) use routing styles in the netlist to have per-net routing styles. It doesn't provide priority (whatever that is), but it allows you to specify a routing style for each net which includes trace width, clearance, and via parameters. This is a feature that pcb's netlist-file format (and auto-router) has supported for many years now. It makes sense for the gschem netlist generator to support it; I'm supposing from your comment that it doesn't already. That is not the fault of the autorouter, it came first. One major drawback at the moment is that all of the net is expected to have the same characteristics, so if for example you make a power net style that is 20 mils wide with 15 mil clearance, it won't be able to connect to a fine-pitch part because the constraints can't be met due to the part characteristics, but it will route what it can. If you manually create breakouts that the autorouter can connect to without violating constraints, it can then make the connections. Be sure that any such breakouts have either vertically or horizontally oriented lines or a via where you want the connection made because the autorouter will not connect to any diagonal copper. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: autorouter fixes and enhancements
A bunch of fixes and enhancements to the original pcb autorouter
should now be available in the git repository. Here is a short how-to
for using the autorouter
(1) turn off visibility of any layers you don't want the router using
(2) turn of via visibility if you don't want it to use any new vias
(3) Use only plain rectangles for power/ground planes that you want
the router to use [use the rectangle tool!]
(4) Make at least one connection from any plane you want the router to
use to the net you want it to connect to.
(5) draw continuous lines (on all routing layers) to outline keep-out
zones if desired
(6) use routing styles in the netlist to have per-net routing styles
(7) set the current routing style to whatever you'd like the router to
use for any nets not having a defined route style in the netlist
(8) disable any nets that you don't want the autorouter to route
(double-click them in the netlist window to add/remove the *)
NOTE: If you will be manually routing these later not using
planes, it is usually better to let the autorouter route them then rip
them up yourself afterwards. If you plan to use a ground/power plane
manually, consider making it from one or more pure rectangles and
letting the autorouter have a go at it.
(9) create a fresh rat's nest. ('E' the 'W')
(10) select show autorouter trials in the settings menu if you want
to watch what's happening
(11) Choose autoroute all rats in the connection menu.
[12] if you really want to muck with the router because you have a
special design, e.g. all through-hole components you can mess with
layer directional costs by editing the autoroute.c source file and
changing the directional costs in lines 929-940. and try again. Even
more mucking about with costs is possible in lines 4540-4569, but it's
probably not such a good idea unless you really just want to
experiment.
In keeping with the tradition of nothing good being said about the
router, let the complaints flow.
harry
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Re: gEDA-user: Pads do not clear polygons
--- Ben Jackson [EMAIL PROTECTED] wrote: ... The code that tries to walk around creating the joined contour doesn't find a starting point, so the combination is nothing and thus the hole vanishes. I've fixed it (and probably a couple of other related degenerate touching conditions) in cvs. Interestingly, this bug is in the algorithm description in the original paper. Thanks for digging into this Ben, I wouldn't have solved it so quickly otherwise. Never miss a thing. Make Yahoo your home page. http://www.yahoo.com/r/hs ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Setting component coordinates in GUI?
--- steve manley [EMAIL PROTECTED] wrote: Is there a hotkey or other technique to manually set a X Y coordinate for a part, or via, without editing the main PCB source file? There doesn't appear to be anything obvious in either the manual or the FAQ, but that doesn't mean it's not there. :-) Use the : command MoveObject(x,y) with the cursor over the part or via. x and y can be absolute or relative (proceeded with a +/- character) and you can optionally provide a 3rd argument of mil, or mm. Shape Yahoo! in your own image. Join our Network Research Panel today! http://surveylink.yahoo.com/gmrs/yahoo_panel_invite.asp?a=7 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: Pcb Rectangle funnies
Hi Ralf, Try again. I did fix one error with the previous patch; now the other is fixed too. Your test example works now (at least for me). harry --- [EMAIL PROTECTED] wrote: Thank you for looking into it. Hmm, updating CVS fond this in polygon.c: Well, it is still happening. test.pcb.gz attached. Ralf __ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dead copper removal
The PolyArea is value specifies the minimum area a poly region must have to survive a MorphPolygon() operation. Use the :MorphPolygon(Object) command to restore the dead copper areas larger than PolyArea to the board. This command converts the disjoint copper areas into separate polygons. The object that the cursor must be over is the remaining (i.e. non-removed) portion of the polygon. I don't remember if I implemented the selected argument for the command, but if I didn't I'm sure you know how to. h. --- DJ Delorie [EMAIL PROTECTED] wrote: Can this be disabled on a per-board or per-poly basis? I'm trying to use it to preserve etchant, but it's difficult to get enough coverage without getting too close to the traces and such. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user Looking for earth-friendly autos? Browse Top Cars by Green Rating at Yahoo! Autos' Green Center. http://autos.yahoo.com/green_center/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dead copper removal
--- DJ Delorie [EMAIL PROTECTED] wrote: Does it convert them to independent polygon objects, or just tag it to be not-split? In this case, it would be better to leave it as a big rectangle and do the clearance on the fly, so one could edit the board and have the polygon follow it (like pre-clipper). MorphPolygon converts them to independent polygon objects. Presently there is no other way to accomplish what you want. It would take a modest amount of code in many modules to do what you are asking. I would recommend that you save the design before morphing, then select all and morph just prior to generating gerbers. You can view what regions will be restored by the morph with the check polygons setting. I think the most practical way to do what you're asking is to have an option in the gerber generator to include dead copper. That option would then perform the tasks I describe above. It would be simple for you to make a key macro that selected all, morphed selected, generate gerbers, then undo. That would act like what I'm describing. h. 8:00? 8:25? 8:40? Find a flick in no time with the Yahoo! Search movie showtime shortcut. http://tools.search.yahoo.com/shortcuts/#news ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dead copper removal
The clearances can be tweaked while observing them using the check polygons setting. There is no all that involved in the tweaking process. There is a danger to morphing and directly exporting a gerber however: A restored region could intersect multiple joined line and thus cause a change in the topology. --- DJ Delorie [EMAIL PROTECTED] wrote: That's similar to what I do for teardrops, but it helps to be able to tweak the poly clearances without having to go through all that. Finding fabulous fares is fun. Let Yahoo! FareChase search your favorite travel sites to find flight and hotel bargains. http://farechase.yahoo.com/promo-generic-14795097 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA vs commercial product
--- Peter Clifton [EMAIL PROTECTED] wrote: Does anyone care to comment / speculate how much a standard can cover by Copyright? Whether symbols looking similar (or the same, even) are in breach of Copyright? If one symbol on its own isn't, is there some literary work in the database (ie. the list of symbols). It would be very difficult to reproduce a library of symbols without copying or referring to that. The scenes a faire doctrine should allow a free implementation of something similar. However given that the IEC is litigous, it would probably mean a court fight including an appeal. I would expect to win in the end provided the symbols just looked really similar and weren't actually coppied, but who wants to pay for the fight. See http://www.ivanhoffman.com/scenes.html for more info on the doctrine. Get your own web address. Have a HUGE year through Yahoo! Small Business. http://smallbusiness.yahoo.com/domains/?p=BESTDEAL ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb program
I've fixed the problem in rats.c; Just grab the latest cvs. h. --- Seb James [EMAIL PROTECTED] wrote: In that case I have the changes you made, and I am still seeing the rats nest problem. No need to miss a message. Get email on-the-go with Yahoo! Mail for Mobile. Get started. http://mobile.yahoo.com/mail ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb program
I noticed the problem is occuring during an extremely high zoom in. pcb used to have code to clip the zoomed lines to the screen in order to prevent integer overflow. With the advent of hid that was removed and now zooming in runs the risk of overflow with its unlimited zoom capability. It's very severe with rats because all rats seem to be being drawn, even those that should not be visible at all - thus virtually all of them are overflowing. First recommendation is don't zoom in so close with rats on. Second thing is we should fix the drawing so that it only draws the visible rats. I thought it already did that. Third is it's time to put proper clipping into the hid drawing routines. Interesting polygons are the only structures being properly clipped at the moment. The polygon clipping is slow when the polygons have many thousands of verticies. I'll be improving this situation this spring by (a) reducing a circle's vertice count to 20 from 36 (this is still more than many commercial packages). (b) cacheing the diced polygons used for rendering and (c) Modifying the file format to store the clipped polygon data so that file loading is fast if the clip information is saved. h. TV dinner still cooling? Check out Tonight's Picks on Yahoo! TV. http://tv.yahoo.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to move PCB element to layer??
Ok, wart city. Why is it 'Edit|Move selected to current layer' for some things and 'Select|Move selected elements to other side' for elements? Why is there moving to layer, mirror and flip? Why is mirror only for things buffers, moving only for lines and text and flip only for elements? Conceptually components only exist on the surface layers, much like the silkscreen. Interestingly I recently designed a circuit at work that required buried components, so I can see that there is the very rare need to do this. But I think your question is more along the lines of why are their differening commands? since I doubt you are trying to bury a component. The short answer is because pcb can't handle buried components and therefore components are either on the top or bottom, and they must be mirror imaged to be on the bottom, so that's why they have a special command - it goes to the layer you want (i.e. the other surface) without your having to be working on that layer, and it auto-mirror as it must. It works with a single keystroke so it's pretty easy to use regardless of what layer you're on. It is very rare that traces etc. should be mirrored and usually you want a whole group mirrored, so we haven't provided a convenience function for doing that outside a buffer, but it would be trivial to implement; back before the hid was introduced single key macros were really easy to implement (they still are with lesstif) and you could easily make a key macro to mirror one single object on the board. Traces (lines and arcs), and polygons can be on any layer so they have a move-to-layer function. If you're trying to move a whole layout region from front to back of your board, trying cutting the region to a buffer, then *view* the opposite side of the board and paste. Viola' everything is done for you. It wouldn't be too hard to have some special-case code for the move-to-layer function to check if you've tried to perform it on an element, and if you have and the layer is a surface layer then perform the flip instead. You should write it. h. Any questions? Get answers on any topic at www.Answers.yahoo.com. Try it now. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next step questions
--- Craig Niederberger [EMAIL PROTECTED] wrote: 1. Is it possible when autorouting traces in PCB to have some automatically set to one set of thicknesses, drill hole sizes, etc. and others automatically set to another set of thicknesses, drill hole sizes, etc? Or must I always select traces by hand to be autorouted to a specific set of thicknesses, drill hole sizes, etc? Yes, you can assign a route style to each net. This is normally done in the netlist file. The format is: netname [stylename] elname-pinnum elname2-pinnum ... where [] means an optional entry. You can manually edit your netlist file to add styles to each net. The autorouter honors each net's style including thickness, via characteristics and keepaway. 2. I noticed in examining the PCB design after autorouting that extra nubbins occasionally appeared on traces. I deleted these by hand, which was somewhat painstaking. I also noticed one unconnected trace--it went almost all the way to the pad, but didn't connect. I fixed that by hand. Has anyone else experienced these occasional oddities? I introduced the bug that caused the fail to connect some time back, but it fixed it in December. The latest snapshot release should never go almost all the way but fail to connect. It should leave a lot fewer nubbins (perhaps none) as well. DJ's optimizer might be able to automatically remove the nubbins. It's here! Your new message! Get new email alerts with the free Yahoo! Toolbar. http://tools.search.yahoo.com/toolbar/features/mail/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: ratsnest and auto DRC also a bit about poly features was www.66each.com
--- Ben Jackson [EMAIL PROTECTED] wrote: ... I would like the ratsnesting to work in a sane fashion and I'd like auto DRC to let me actually draw traces to pads in the same net... Please explain what is not sane about the rats nest. The auto DRC prevents making connections that alter the network so it will stop you from connecting nets that aren't already connected (with a rat line). pcb doesn't work like a lot of tools and it is intended to be that way. Many people use it without ever creating a netlist for example. It will let you draw arbitrary copper whever you like. It does not mode you in nearly as much as most commercial offerings. It doesn't absolutely require a high end computer to be useful - some people use it successfully on 10 year old computers. These things have their disadvantages as well as their advantages. I'd like to see the feature set have the best of both worlds. I like the idea of having a command to assign a polygon to a net for example ( automagically setting thermals, joins and clearances of objects within it), but I don't want it to be *required* in order to place a polygon. Do you Yahoo!? Everyone is raving about the all-new Yahoo! Mail beta. http://new.mail.yahoo.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb-20070208 snapshot
--- Dan McMahill [EMAIL PROTECTED] wrote: Hello, I have uploaded a new pcb snapshot to sourceforge. The change list fails to mention one of the new features is a change of cursor shape to visually indicate when the arrow tool will grab the end-point of a line before you grab it. Any questions? Get answers on any topic at www.Answers.yahoo.com. Try it now. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Rotations, rotations, rotations.
--- Lares Moreau [EMAIL PROTECTED] wrote: No! it's not implemented yet. This is what I have started to implement. Let me know what you think. I think before putting much effort in to this, the patch contributed to sourceforge should be evaluated. From my looking at the patch itself I think the author covered almost everything that matters. Running it through Dan's test cases would be an important first step. I think that the autorouter will be unable to route to rotated pads unless the rotation is very small. It would be foolish to reinvent the wheel if it's mostly working. We won't tell. Get more on shows you hate to love (and love to hate): Yahoo! TV's Guilty Pleasures list. http://tv.yahoo.com/collections/265 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
- That's one. Another is that the rats for a net don't go away unless you can get your line to end exactly the right place, which doesn't work for me even with snap to pad. That's pretty hard to believe. The connectivity is checked by a rigurous intersection test, no particular points are required, any touching will do. Implied in your statment is that after making a connection and optimizing the rats nest (o key), a rat line suggests the connection you just made is not making connection. I'd really like to see a test case because I've never seen this behavior ever. Also, the rat wire should give visual feedback as you route a net -- rats to routed pads should disappear as you place tracks that complete segments. Originally it took a fair amount of compute resources to trace the connectivity - it still can with very large boards so updating the whole rats nest automatically was never really considered. I think that most computers are fast enough now that its a viable idea to add an optional setting to optimize the rats nest after every move, track addition, track deletion etc. That would make the rat disappear as soon as the connection was made. As for the DRC, I've played with a few boards. Each time I end up with at least one rat wire going between two pads which I can't route because the auto-DRC won't let me onto the second pad. This might be related to the fact that my wire didn't start at the right place, despite it starting on the snap point that caused the new line to exactly cover the rat... This sounds like a bug. Send me a test case and I will solve it. Do the source and target turn green when you start the trace? Come to think of it this coupled with your rats nest failure above strongly suggests your layers aren't assigned the way you think they are. There was a release where some default layer names (which are nothing more than names and could well be foo and bar) were something like component and solder while they were actually grouped to the opposite side. Check your layer groupings. There's another thread going on where someone is concerned about trusting a new feature in PCB when fabbing a board. Well, it's all new to me, and I don't know if I trust it yet. Maybe it has fabulous internals and a quirky interface, or maybe the internals are just as quirky... pcb has a long history. For many years it was very stable and very reliable. This past year we have made so many sweeping changes including completely replacing all of the user interfaces and major changes to much of the code internals too. Some level of skeptisism is warranted because of this. With that said I think the latest snapshot release should be pretty stable. Any questions? Get answers on any topic at www.Answers.yahoo.com. Try it now. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: DRC/rat quirks
Because the postscript and pdf prints, on screen, have faint lines between slices, and I didn't know if the DRCbots were going to complain about them. Strange. I'm sure the postscript is drawing those faint lines but they shouldn't be visible since they are on top of or beneath a solid fill. (The slices share a common edge where the line appears.) Does your printed postscript show those lines (or worse gaps)? Don't pick lemons. See all the new 2007 cars at Yahoo! Autos. http://autos.yahoo.com/new_cars.html ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb bug(kinda)
--- DJ Delorie [EMAIL PROTECTED] wrote: Is there a better place to post bugs? There's a sourceforge bug tracker. Both that and the list have pros and cons: list: pro: your bug gets seen. con: your bug gets lost or forgotten tracker: pro: your bug gets remembered. con: you bug might not get seen soon. Of course as has happened many times, one can file a sourceforge bug report *and* e-mail this list. For myself I can say that when I have time to sit down and attack pcb bugs, I generally go through the sourceforge tracker to see which ones I want to tackle. Yahoo! Music Unlimited Access over 1 million songs. http://music.yahoo.com/unlimited ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB- net specific constraint
--- Hans Nieuwenhuis [EMAIL PROTECTED] wrote: Hi, ... - Routestyles can be adjusted on a net level basis in manual and autorouting ... Routestyles: So far I have them working ok just for manual routing, autorouter does not work yet. The autorouter already completely honors per-net route styles. So long as the net is associated with a given route style the autorouter will use all of the width, clearance and via sizes associated with it. There may be an issue that already routed nets (at the time of invocation of the autorouter) do not have their specific style clearance honored, but I'm not sure. The clearance bit however does not work yet and right now I am a bit at a loss how to get it to work if AutoDRC is switched on. Is it possible one of the devs can elaborate me on that point? The AutoDRC uses the DRC rules to establish clearance. For starters, it would have to use style keepaways instead of the DRC clearance rule. Then it would need to treat each potentially intersecting copper with its associated keepaway. That would be done using the callback function in the r_search. Need a quick answer? Get one in minutes from people who know. Ask your question on www.Answers.yahoo.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Label Selection.
--- Tomaz Solc [EMAIL PROTECTED] wrote: After experimenting a bit with this, I found out that the mark is always placed where the select menu currently is. This is probably the point where the user interface last saw the mouse cursor in the viewport. Before the introduction of the HID interface, the only menu that had the convert selection to element was the pop-up menu and it used the location of the click that popped up the menu as the coordinate. Actually there were several items in that menu that used the coordinate, it was a useful feature now lost. The GTK interface does have an ability to request the location for a menu operation, which is really annoying when there is a key shortcut because for that it should use the current crosshair position. Don't get soaked. Take a quick peak at the forecast with the Yahoo! Search weather shortcut. http://tools.search.yahoo.com/shortcuts/#loc_weather ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Some pcb pecularities
--- DJ Delorie [EMAIL PROTECTED] wrote: 1) Long lines do funny things if zoomed in a lot. I've recently seen short lines and arcs get exploded in the lesstif version too, but haven't tracked it down yet. The new GUI drawing code simply scales the line and then converts the (now overflowed coordinated) to short ints and sends them X to render. Before the HID came along, there was clipping code that prevented this coordinate overflow and thus produces correct drawing (usually). But the desire for eye-candy and fluff won out over correctness. Presenly in CVS only *polygons* are always rendered correctly regardless of zoom level. 3) Auto router and manual line drawing tool interpret line clearance differently. If clearance is set to 10 mil for a particular route style, the auto routed lines will punch a 10 mil gap into polygons. With manually drawn lines the gap is just 5 mil. I'd say, the auto router is correct. According to the documentation, clearance is the amount added to the thickness of the line, so a 10 mil clearance should result in a 5 mil gap on each side of the line. At least, that's what the file format spec says. The file specs are for the file. The GUI interface should define clearance as the gap on each side. Just like join is compliment of clear-line, there are some historic strangenesses in the file format, but they should only apply to the file format. I believe the current CVS has the clearance correct for both manual and auto-routed lines. 4) Rubber band move of automatically generated vias results in a mess of tracks. Some tiny tracklets seem to be expanded rather than moved. One end stays where it was and the other moves with the via - the definition of rubber banding. Still, it's not what the user wants. This is already an open bug on the SF tracker. Looking for earth-friendly autos? Browse Top Cars by Green Rating at Yahoo! Autos' Green Center. http://autos.yahoo.com/green_center/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB gerber export problem - update
I'm not sure if this is really fair to call a bug in CircuitCAM. It's a little ambiguous as to whether multiple layers of the same design should have a common aperture definitions. pcb's gerber driver that I wrote (before the HID was introduced) used a common table for all gerber files within the design. The HID gerber driver doesn't seem to do that and I think it should be changed so that it does. The patch makes unique apertures in each file but that quickly uses up apertures. The right way to do it is to have every file use the same D code for the same shape and size. That's the way it used to be. We need to go back to that. harry Do you Yahoo!? Everyone is raving about the all-new Yahoo! Mail beta. http://new.mail.yahoo.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Ground-plane in Pcb
Tuck Hartshorn wrote: (btw, why is there no :DisplayFlag(selected,join) ?) What would you have this command do? You can get a report on any individual track with the ctrl-r key. The actual flag is named clearline and is logically opposite from the join notion that we used to name the command; this is a historical accident because the code feature came first and I was looking for a key to map it to that would have some sensible mnemonic. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Ground-plane in Pcb
Tuck Hartshorn wrote: On Friday 22 December 2006 20:37, DJ Delorie wrote: latest as in cvs? I got cvs but it failed to make completely. The current cvs is missing some .pngs in the ./doc dir, namely puller.png and thermal.png But, I thought the binary might be ok, anyway. And, it does seem to work. Shows version 1.99u instead of 20060822. It seems no better and it did not make isolation islands over existing nets. tuck All of the nets (a misnomer; they are tracks) that you've already drawn apperently already have their join flag set. That is they have been told to touch any polygons they encounter. It seems you wanted to draw them with the new lines arcs clear polygons setting checked. No problem, simply select all lines then enter the command :ChangeFlag(selected,join,0). Now all of the lines are told to clear the polygons. Another (unlikely) possibility is that you have flagged the polygon to not allow anything to make clearances in it. You can't create polygons with that property to begin with, but you can give (and take) that property with the s key. DJ misunderstood your problem. Older versions of pcb were perfectly capable of making clearances in polygons around tracks, it just did not understand that an isolated island created by clearing regions of the polygon was no longer electically connected to the other parts of the polygon. The new version does. Another important point is that the gnd-solder is nothing more than a name. It has no meaning, you can change that name to anything you like and it won't make any difference, except for the two special names route and outline. Pcb has a strange feature allowing grouping of layers into a single physical copper layer; people use that to color-code tracks. When layers are grouped, turning off/on visibility of one layer in the group will do so for all layers in the group. This is one hint that layers are grouped, but you should look at the layer grouping dialog to truly understand which layer is where. If gnd-solder is not grouped with solder then don't expect tracks on the solder layer to clear a polygon on the gnd-solder layer. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: PCB Trim/extend traces
Are there plans to introduce visual handles at the end of the lines? I have checked in changes to the CVS tree that create a cursor change indicating when dragging will move the line end-point. I've also cut the slop range in half, which helps the useability quite a bit too. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Clarifying the License issues for gaf and PCB
Steve Meier wrote: I think at this point, in order to avoid confussion. 1) That gaf and pcb need to state if they consider the distributed symbols and land patterns to be code. I have never considered land patterns to be code. I'd be perfectly happy for a font-like exception being clearly stated for the outputs of pcb (gerber, ps, screen capture etc.) for those (few) symbols/footprints that I've created. The real trouble is that the symbol libraries have been contributed by many different people. It will be very hard to figure out a complete list of who contributed what. I think that there are very few if any footprint/symbol contributors who would object to such a license clarification, but locating them all for verification will probably be quite troublesome. I believe I discussed the issue with Thomas many years ago and he didn't think of the libraries as code either. One solution would be to gut the libraries and start over. That could have the advantage of raising the quality and reliability of the library too (but greatly reducing the count too). For me personally it's never mattered because I've considered the libraries to be so error prone that I've always made my own footprints anyway. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: practical pcb layout-fu
John Griessen wrote: So. with those ideas in mind, a GUI or hotkey set of commands to switch between different weightings of costs for different signal paths would be good. Different rules for RF and short med speed digital paths, and audio and heat dissipating power zones. switch easily between rule sets. In point of fact, the existing auto-router has a set of cost functions, iteration counts etc that really should be available for adjustment at the user interface. Recently I've been making improvements to the autorouter; it produces much more normal looking tracks and generally is performing better. With that said I think that most people have unrealisitic expectation of what an auto router should be able to do, or how simple they are to implement. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: connecting symbols that look nothing like their footprint
DJ Wrote: Have you tried just naming the pins all the same? The autorouter might not do the right thing, but DRC shouldn't complain. Just for clarification, he means NUMBERING the pins the same. Pcb element pins (and pads) have both names and numbers. The numbers are what are used for checking connectivity and they can be arbitrary strings (like S). The names are used only for convenience to describe a pin's function. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bug or feature in recent versions of PCB?
Tomaz Solc wrote: Do you have any idea what application would be stealing the focus? I'm not running anything special - just the stock GNOME installation that comes with Debian. Gschem and other tools don't seem to have any problems with this. I have no idea really, but you might learn something by looking at the event stream. Run xwininfo to determine the window ID of the drawing area, then run xev -ID (with the window id) to see the event stream. On an unrelated note, I seem to have stopped receiving messages from the geda mailing list although I did nothing to unsubscribe or block them. Good luck, harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bug or feature in recent versions of PCB?
Tomaz Solc wrote: As far as I can see lesstif doesn't have this bug. But as I said, this behavior is not deterministic, so maybe it's just less common than in GTK. I don't see this behavior with either gui ever. Here is something I'd like you to try: Go to the pcb/src directory and run: ./pcbtest.sh -gdb at the gdb prompt type: br ghid_pan_idle_cb run Now pcb should be up and running. Now set your settings and start drawing those rectangles. You should never hit the breakpoint unless the cursor leaves the the main drawing area while in the midst of drawing a line (i.e. you drag the drawing line outside past the window edge). The question is this: Do you hit the breakpoint, or do you get the drawing errors without hitting the breakpoint? If the breakpoint is hit (and you haven't moved the mouse pointer outside the drawing window while drawing a line), then I suspect some other application on your system is stealing focus for a moment and then returning it. Let us know the results of the test. Regards, harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gPCB Polygon Best Practices
DJ Delorie wrote: Tips like this really help cut down the learning curve. The curve would be shorter if it just didn't do that, of course. With the current CVS code, it doesn't do that. Is their a way to assign a PCB layer or set of copper to a specific net? So for instance my GND plane or polygon would be assigned to the GND net. Draw the polygon and tie it into the net with a thermal. PCB should figure the rest out from that. Any kind of connection will do - it can be done with a joining line instead of a thermal. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: My board is back -- groundplane (polygon) is missing
Stefan Salewski wrote: Hello, two weeks ago I send my gerbers to board manufacturer www.bilex-lp.com. Just get the board back: Looks fine, but polygons building ground plans on solder side are missing, so board is useless. PNG pictures of pcb layout are available at http://www.ssalewski.de/AVR_USB_gEDA.html.de, gEDA sources at http://www.ssalewski.de/AVR_USB_gEDA-20061016.tar.gz and the gerbers I send to board producer at http://www.ssalewski.de/boarddata.zip For me gerbers are ok if displaying it with gerbv. Is there something wrong with the gerber files? Best regards Stefan Salewski My guess is that your pcb fabricator does not support the gerber rs274x specification. Some don't because they use old equipment made before the specification was adopted. Of course they should tell you that they don't support it. Another possibility is that they could support it, but don't like files with merged layers that pcb used to produce. In that case they should tell you that they won't except the merged layers. Some fabs have a low-cost prototype option where they tell you all of the restrictions on a web page and it is up to you to ensure that you meet them - they will fab regardless of what you send but the responsibility for failing to meet their restrictive requirements is yours. If your fab vendor did not disclose their inability to support polygons or merged layers then I think you should be entitled to a refund. One thing I did find unusual in the gerber file was that at the end, after all of the drawing was done, a clear layer was added where each aperature was selected but no drawing was done. I don't know why pcb would have done that but it doesn't break any rules or change how the image looks. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB polygon rectangle practicalities
Dave N6NZ wrote: In fooling with various practice layouts (partial layouts, actually) I think I have the basics of polygons and rectangles sorted out. Now I'm wondering about the practicalities is adjoining poly's. Here is the situation: In my design, there wants to be a polygon patch of analog ground that will have nothing routed through it, although there will be a few clearance vias and thermal-relief joined vias. This polygon will be on the solder side (2 sided design) and will be an island in what I hope will be a fairly continuous chunk of digital ground plane, although I'm planning the solder side as my Y-axis routing layer, so there will be lots of traces cleared out through it. Anyway the point is, while the analog ground patch is easy to draw as a poly, the digital ground wants to be a simple rectangle with an island in it. I presume that the best way to make that happen is to lay down the AGND poly, and then draw several rectangles/poly's for GND until the composite is the shape I want. So... do I need to overlap the GND poly's so that they will join up? Or can I just turn on the grid and draw to the snaps and count on touching to be enough to actually join them? Are there some gotcha's here that I haven't thought of that I am going to trip over? Manufacturability issues? Touching is sufficient for the polygons to make contact. However, there is no harm in overlapping them a bit. The new polygon clipping code will dice up any polygon that has holes in it into smaller ones that don't have holes and they just touch, they don't overlap. You should be able to create the larger digital ground plane from only two drawn polygons. Another trick you can use would be to just draw a single rectangle over the board, and use clearing lines (and/or arcs) to isolate the analog ground island. If you are routing a lot of tracks through the ground plane, chances are that you will create other unintentional islands too. You can use the MorphPolygon() command to make new polys from the islands (including the analog ground one, and if you do this then after the morph you can remove the tracks originally used to create the isolation). It will be up to you to connect any islands that don't end up connected. I don't think you'll run into any manufacturing issues. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: more on clipping
David Carr wrote: Just curious, How are you handling arcs in the polygons? Are you using line segments as an approximation or are you actually using an arc primitive? If you are using line segments, does the number of segments vary on the diameter or is it fixed? Your 100K vertex comment made me curious. Arcs are approximated by line segments; there is a fixed number - each segment spans 10 degrees. Thus there are 36 segments in a circle (such as a via clearance). Lines have rounded ends so clearance around lines also have 36 segments. h. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: more on clipping
Levente wrote: I think you should morph the polygon into its pieces, then use the f-key to highlight those that are connected This is what I did on the top side, since a big polygon was not drawn. Anyways, thanks for your help, and again, for implementing this clipping thing! I think you may have misunderstood me. When I said morph I mean use the command MorphPolygon(Object) which converts all of the broken polygon pieces into separate polygons for you. On the top side, there is some geometric computation error (that I'm trying to track down) when the polygon covers the whole side. I can't seem to get the error if I cover the side with two overlapping polygons. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: bf1 vs. pcb
Levente, I should point out that bf1.pcb has two identical copies of a self-intersecting polygon (that's bad) at lines 8427 and 8432. I think you want to delete one of the polys and drop the last point in the poly. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: more on clipping
Levente wrote: I've tested this clipping toy for a while. I think the best thing would be if there was a way to recalculate dead areas; hence for example, if you add a via in a dead area, and in the other side if there is some GND present, the area can be again filled. So somehow it should be dynamic. Or it would be nice to have a menu item like Recalculate polygons or something like this. I think you should morph the polygon into its pieces, then use the f-key to highlight those that are connected. If you are able to connect the others, then keep them or delete them if you can't get them connected. The advantage of this is that you don't have to constantly re-compute the one huge polygon with its hundred thousand verticies. It will make working with, and re-loading the design much faster while still accomplishing everything you want. h. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: bf1 vs. pcb
Levente wrote: ... Please find the pcb file via this link. http://web.interware.hu/lekovacs/cuccok/hardware/bf1.pcb What an excellent example of Swiss Cheese! There was a bug in the layer group loop macro using the PCB group settings instead of the one in the file loading. It took a very long time to insert the thousands of holes into the polygons thousands of times, especially since the containing contours got to the point of having about 15,000 verticies! I've got it considerably optimized now, but it will probably still take a minute to load the first time. I recommend that you select all and morph the polygons, then re-save the design. It will load faster after that. It does a nice job of showing all of the floating polygon islands when you do a find connections on the ground net. Fixes are in. Grab the latest CVS and give it a go. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: home-made 4 layer board idea
DJ Delorie wrote: Plus the usual problem of obtaining the thin outer clads, and precise enough drilling. Don't forget the chemicals, tanks, protective gloves, resist, photomask (or equivalent). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: home-made 4 layer board idea
DJ Delorie wrote: Don't forget the chemicals, tanks, protective gloves, resist, photomask (or equivalent). I'm all set on that. I did the two prototypes for the smd challenge myself, for example, that's 6 mil rules. How do you put on your LPI soldermask? Do you use an old turntable to spin it on? :-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB feature wishes
Let's suppose for example I've just drawn a new line and overshot the target. I don't seem to be able to just select that unconnected endpoint and pull it back to where the place where it should connect. Well, actually I CAN select the line, but when I drag it always makes the entire new line move back. Then the line overshoots the connection on the other end. Either I'm doing something wrong, or this feature doesn't work on unconnected line segment ends. Sounds like the line is selected, or you're grabbing the whole line and not the end. Indeed there seems to be a wide-spread misconception that one must select a line in order to move it. You *can* select it and then move it, but it is not necessary. Just grab and drag it with the arrow tool which is faster and easier. In the case of a line end-point you MUST NOT SELECT IT. Selections always moves the entire selection and there is no way to select only an end point. To move the end point you must just drag the end point with the arrow tool on an unselected line. DJ's patch in CVS only improves (restores the original function some versions ago) the slop (inaccuracy) with which you must grab the end point. h. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Trouble with Newlib footprint treaded as M4
Jeff VR wrote: I'm looking for some help in debugging this problem. Is there an intermediate step I can run to try and figure out if the problem is with the footprint or my schematic? What triggers the m4 library to kick in? All elements are loaded through m4, but most newlib elements don't use any macros. The main difference with newlib is that it provides a mechanism to have a list of elements to choose from where that list itself isn't from an m4 macro. h. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: center grip was Re: PCB a bad name ?
Kai-Martin Knaak wrote: On Wed, 20 Sep 2006 21:00:40 +0100, Peter Clifton wrote: You mean grips at the end of tracks when you hover over them? Exactly :-) Next step would be an additional grip in the middle of the track. Drag this grip to keep the ends of the track in place and move the two legs like a rubber band. This leaves you with an additional corner in the track. I used this feature with protel all the time. That would be like the insert point tool. Use all-direction lines mode if you want to bend the lines at any arbitrary angle. All this is to say that the capability exists now although it does require a keystroke to change the tool first. I can see where grabbing at a grip point makes the interface a bit faster. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB a bad name ?
DJ Delorie wrote: No, but gpcb for gnu pcb might. Although, are we really part of the GNU project? We can't just say we're gnu! without getting accepted by them first. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user We are GNU. See http://directory.fsf.org/GNU/pcb.html which clearly I need to get updated. Sorry to disappoint, but I see no reason to change the name. The 3rd hit on Google for pcb will get you there and you can always search for gnu pcb in google to bring it to the first hit. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Re: PCB: Moving the endpoint of a line
Kai-Martin Knaak wrote: in closely the program requires that you grab it more accurately; - the center can be hard to accurately estimate and when zoomed ^^^ Why is this so? It sort of nullifies the benefit of zooming in. The reason is fairly simple. If you zoom in close enough the actual center might be on the far left edge of the screen, or the far right edge of the screen. It would make the zoom meaningless if when you zoom in to get 0.01 mil detail the position of the cursor on the screen represented one point. The way the slop works is that if the crosshair is within 5 screen pixels of an end-point, it considers that you mean the end-point. If you are zoomed in such that the line width is 180 pixels across the screen, you've got to hit the center very precisely. If you are zoomed out such that the line is only 2 pixels wide as seen on the screen then you don't even have to quite be on the line to grab the end. The value 5 is the SLOP constant found in seach.h in the src directory. You can change this and recompile to make it more forgiving. It shouldn't be very hard to visually highlight the circle at the end of the line when the cursor hovers over it for a moment. It's a fine idea that I will probably look into some time. Right now I'm concentrating on solving the dead copper inside polygons issue. harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: n00b confused about track connections
Dave N6NZ wrote: Just getting serious about going for my first layout using pcb. I have done some PC layout before, so my questions are all about how this particular software works, not pc layout in general. I have a test file with two parts and four nets the successfully netlist (yay!) and I can pull them into pcb. When I turn on the ratlines, all nets show up. Good so far... but now sometimes when I try to route a net, it refuses to join a track to existing track for that net. All the pads and track segments light up as part of the net when I select the net in the netlist. But pcb refuses to let the tracks connect. What's up with that? It's like it refuses to believe the tracks/pads are all part of the same net when placing tracks, yet the netlist highlighting is correct. If you are using the auto enforce DRC drawing mode, then you must start the track on a known net in the netlist. The rat lines must be drawn (but you can turn off visibility of the rat layer if you like). When you begin a track, everything that belongs to the net should turn green. You will only be allowed to touch copper that has turned green; the program will force a clearance standoff from all other copper. h. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Barrie Gilbert
Dan McMahill wrote: Bonus points to anyone who can name the real inventor of the mixer in question here. Hint: It wasn't Gilbert even though it's called a Gilbert cell. H. Jones I believe. Bob Widlar didn't design that particular cell structure nor specifically generalize the trans-linear principle early on, but he was among the first to design circuits that actually used the translinear behavior of monolithic transistors. sum( Vbe_cw ) = sum( Vbe_ccw) where Vbe_cw = junctions where the voltage is positive in the clockwise direction and Vbe_ccw = junctions where the voltage is positive in the counter clockwise direction. Now assume all the Is are the same and some simple math shows that product( Ic_cw ) = product( Ic_ccw ) For example, you can build a circuit where I1 * I2 = I3 * I4 Of course the Is's need not be identical, just ratiometrically matched (I know you know that Dan, but maybe not others here). Ratios in Is can be achieved through scaling emitter areas, or more precise retios through paralleling devices. One key point is that this really only works well in a monolothic design where tight thermal and doping matching can be achieved. For non-constant Is, the equation above is just I1/Is1 * I2/Is2 = I3/Is3 * I4/Is4. Cheers, harry ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
