[gem5-dev] Change in gem5/gem5[master]: tests: Add documentation for new testing code

[Jason Lowe-Power (Gerrit)]

Hello Sean Wilson, Gabe Black,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4882

to look at the new patch set (#12).

Change subject: tests: Add documentation for new testing code
..

tests: Add documentation for new testing code

Change-Id: Id62ad8e452e640073079e76c9ce5898cedee
Signed-off-by: Jason Lowe-Power 
---
M CONTRIBUTING.md
A TESTING.md
2 files changed, 218 insertions(+), 7 deletions(-)


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Gerrit-Owner: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[master]: tests: Add a simple example test

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#12) to the change  
originally created by Sean Wilson. (  
https://gem5-review.googlesource.com/4422 )


Change subject: tests: Add a simple example test
..

tests: Add a simple example test

Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Signed-off-by: Sean Wilson 
---
A tests/gem5/hello_se/ref/simerr
A tests/gem5/hello_se/ref/simout
A tests/gem5/hello_se/test_hello_se.py
3 files changed, 65 insertions(+), 0 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: tests: Add Makefiles for hello

[Jason Lowe-Power (Gerrit)]

Hello Sean Wilson,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4883

to look at the new patch set (#12).

Change subject: tests: Add Makefiles for hello
..

tests: Add Makefiles for hello

This adds Makefiles for hello for ARM and x86 by leveraging docker and
dockcross. See https://github.com/dockcross/dockcross for more
information.

These Makefiles also allow for automatic uploading to the correct location
for users to download when running the new tests.

Change-Id: I7085000393cd5283502a7af362c85befda749181
Signed-off-by: Jason Lowe-Power 
---
A tests/test-progs/hello/.gitignore
A tests/test-progs/hello/bin/arm/linux/README
D tests/test-progs/hello/bin/arm/linux/hello
A tests/test-progs/hello/bin/arm/linux/hello
A tests/test-progs/hello/bin/x86/linux/README
D tests/test-progs/hello/bin/x86/linux/hello
A tests/test-progs/hello/bin/x86/linux/hello
D tests/test-progs/hello/bin/x86/linux/hello32
A tests/test-progs/hello/src/Makefile.arm
A tests/test-progs/hello/src/Makefile.x86
10 files changed, 82 insertions(+), 0 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: tests, ext: Add a new testing library proposal

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#12) to the change  
originally created by Sean Wilson. (  
https://gem5-review.googlesource.com/4421 )


Change subject: tests,ext: Add a new testing library proposal
..

tests,ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson 
---
M configs/common/Simulation.py
A ext/testlib/FILES.rst
A ext/testlib/__init__.py
A ext/testlib/config.py
A ext/testlib/fixture.py
A ext/testlib/helper.py
A ext/testlib/loader.py
A ext/testlib/logger.py
A ext/testlib/main.py
A ext/testlib/query.py
A ext/testlib/result.py
A ext/testlib/runner/__init__.py
A ext/testlib/runner/parallel.py
A ext/testlib/runner/runner.py
A ext/testlib/suite.py
A ext/testlib/tee.py
A ext/testlib/terminal.py
A ext/testlib/test.py
A ext/testlib/uid.py
A ext/testlib/util.py
A tests/.gitignore
A tests/credentials.ini
A tests/gem5/__init__.py
A tests/gem5/fixture.py
A tests/gem5/suite.py
A tests/gem5/verifier.py
A tests/legacy-configs/run.py
A tests/main.py
28 files changed, 5,526 insertions(+), 1 deletion(-)


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Gerrit-Owner: Sean Wilson 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: tests: Add explicit build test

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#3). (  
https://gem5-review.googlesource.com/10121 )


Change subject: tests: Add explicit build test
..

tests: Add explicit build test

Change-Id: Ia613ab580b880a463c9cf0dd63f61497db31fe75
Signed-off-by: Jason Lowe-Power 
---
A tests/gem5/test_build/test_build.py
1 file changed, 60 insertions(+), 0 deletions(-)


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Gerrit-Change-Number: 10121
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[gem5-dev] Change in gem5/gem5[master]: tests: Add test for the m5-exit instruction.

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#12) to the change  
originally created by Sean Wilson. (  
https://gem5-review.googlesource.com/4423 )


Change subject: tests: Add test for the m5-exit instruction.
..

tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson 
---
A tests/gem5/m5_util/test_exit.py
A tests/test-progs/m5-exit/.gitignore
A tests/test-progs/m5-exit/src/Makefile.x86
A tests/test-progs/m5-exit/src/m5-exit.c
M util/m5/Makefile.x86
5 files changed, 99 insertions(+), 1 deletion(-)


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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix TempCacheBlock insert

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/11349 )


Change subject: mem-cache: Fix TempCacheBlock insert
..

mem-cache: Fix TempCacheBlock insert

TempCacheBlock insert() had a different signature than the parent class
which caused an error on clang. This matches the signature with default
zero values.

Change-Id: Ic096914497f3d17e88295c9e65a04d76fdddf365
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/11349
Reviewed-by: Nikos Nikoleris 
Maintainer: Nikos Nikoleris 
---
M src/mem/cache/blk.hh
1 file changed, 2 insertions(+), 9 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 48deef5..97e1d42 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -420,15 +420,8 @@
 _addr = MaxAddr;
 }

-/**
- * Set member variables when a block insertion occurs. A TempCacheBlk  
does
- * not have all the information required to regenerate the block's  
address,

- * so it is provided the address itself for easy regeneration.
- *
- * @param addr Block address.
- * @param is_secure Whether the block is in secure space or not.
- */
-void insert(const Addr addr, const bool is_secure)
+void insert(const Addr addr, const bool is_secure,
+const int src_master_ID=0, const uint32_t task_ID=0)  
override

 {
 // Set block address
 _addr = addr;

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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix TempCacheBlock insert

[Jason Lowe-Power (Gerrit)]

Hello Daniel Carvalho, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/11349

to look at the new patch set (#2).

Change subject: mem-cache: Fix TempCacheBlock insert
..

mem-cache: Fix TempCacheBlock insert

TempCacheBlock insert() had a different signature than the parent class
which caused an error on clang. This matches the signature with default
zero values.

Change-Id: Ic096914497f3d17e88295c9e65a04d76fdddf365
Signed-off-by: Jason Lowe-Power 
---
M src/mem/cache/blk.hh
1 file changed, 2 insertions(+), 9 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix TempCacheBlock insert

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/11349



Change subject: mem-cache: Fix TempCacheBlock insert
..

mem-cache: Fix TempCacheBlock insert

TempCacheBlock insert() had a different signature than the parent class
which caused an error on clang. This matches the signature with default
zero values.

Change-Id: Ic096914497f3d17e88295c9e65a04d76fdddf365
Signed-off-by: Jason Lowe-Power 
---
M src/mem/cache/blk.hh
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 48deef5..8dbe44e 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -428,7 +428,8 @@
  * @param addr Block address.
  * @param is_secure Whether the block is in secure space or not.
  */
-void insert(const Addr addr, const bool is_secure)
+void insert(const Addr addr, const bool is_secure,
+const int src_master_ID=0, const uint32_t task_ID=0)  
override

 {
 // Set block address
 _addr = addr;

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Re: [gem5-dev] systemc reviews

[Jason Lowe-Power]

Hey Boris,

I think that gerrit always sends the first message when a patch is uploaded
to the whole list. Then, when adding comments or updating patches gerrit
only sends emails to people that are cc'ed in gerrit. I'm not sure what the
behavior is on merges...

I'm not sure what an easy way to be added to a whole set of changes is. I
don't think gerrit supports it. However you can add yourself as a reviewer
(or cc) to the SystemC changes on a per changeset basis here:
https://gem5-review.googlesource.com/q/topic:%22systemc%22+(status:open%20OR%20status:merged)
.

Cheers,
Jason

On Fri, Jun 15, 2018 at 6:14 AM Boris Shingarov 
wrote:

> > If you also want to be on all the reviews,
> > please let me know. I don't want to unilaterally
> > bomb people's inboxes if they're not interested.
>
> Wait.  I am not sure what you are saying here.
> Are you proposing to *add* so Andreas, Jason and
> Matthias will receive more emails over those review
> emails the dev list is receiving already?
> Or are you proposing to *subtract* so that the dev
> list will no longer receive the systemc reviews like
> we receive now?
> Personally, I am not *that* interested in SystemC
> to *act* on those reviews, but I sure-as-hell enjoy
> *reading* them.
> Are you proposing to make this "lurk mode" unavailable?
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Re: [gem5-dev] systemc reviews

[Jason Lowe-Power]

ut both are in a way
> > > superior to the existing approach (1). However, in order to implement 3
> > > a lot of changes to the code base are required. Implementing these
> > > changes will take some time, so there will probably be two versions of
> > > gem5: a legacy one and the SystemC one. This again produces more work
> in
> > > maintaining the code base. Now I wonder: who is willing to do all this
> > > work?
> > >
> > > While I favour approach 3 for its benefits and the points Matthias
> made,
> > > I still like Gabe's idea very much. It minimizes the changes required
> to
> > > the existing code base while providing many benefits to a broader
> > > community. As Gabe mentioned before, his approach neither breaks with
> > > the existing bridges implemented by me and Matthias, nor does it
> prevent
> > > implementation of approach 3 in the future. To sum it up: there are no
> > > objections from my side.
> > >
> > > Unfortunately, I am not very active in hardware modeling anymore, but I
> > > am very interested in this development and I hope to find the time to
> > > have a look on the patches soon.
> > >
> > > Best,
> > >
> > > Christian
> > >
> > > Matthias Jung  writes:
> > >
> > >> Hi Gabe,
> > >>
> > >> I totally agree with you. SytemC is a standard and the code maintained
> > >> by accellera is just an „example“ of how SystemC could be implemented.
> > >>
> > >> However, that is part of my argument. If I want to use e.g. another
> > >> fancy SystemC kernel (e.g. https://dl.acm.org/citation.cfm?id=2987374
> )
> > >> or a commercial one like the one in the Synopsys toolchains, I cannot
> > >> use gem5 (beside the coupling that is already there, which has also
> > >> several drawbacks). So I like more the separation of simulation models
> > >> and the kernel.
> > >>
> > >> But I also understand it from your side. In Google you don’t have this
> > >> specific need and you want to find quickly a solution with less
> effort.
> > >> Anyway we should discuss if a full switch to SystemC as a kernel might
> > >> be a reasonable long term goal. I think many people would benefit from
> > >> that.
> > >>
> > >> I’m also keen to know Christian’s, Andreas’ and Jason’s opinions.
> > >>
> > >> It’s a pitty that gem5 and SystemC started back at the same time
> > >> and evolved separately...
> > >>
> > >> Best,
> > >> Matthias
> > >>
> > >>> Am 09.06.2018 um 02:34 schrieb Gabe Black :
> > >>>
> > >>> Also, I should point out that the systemc standard defines a set of
> > >>> mechanisms and an interface, not an implementation. The Accellera
> > version
> > >>> of systemc is *not* the standard, it's just an implementation (a very
> > >>> common and important one) of that standard. It's dangerous to
> conflate
> > >>> those two ideas, and it leads to a lot of problems for everybody.
> > >>>
> > >>> Gabe
> > >>>
> > >>> On Fri, Jun 8, 2018 at 12:50 PM Gabe Black 
> > wrote:
> > >>>
> > >>>> Giacomo, if you're proposing linking in the systemc library and then
> > >>>> adding wrappers to somehow plug that into gem5's underlying
> > mechanisms, I'm
> > >>>> not sure that's technically feasible since the existing
> implementation
> > >>>> isn't intended to be built on top of something else. Also a lot of
> the
> > >>>> mechanisms are built into base classes, and so if you change what
> data
> > >>>> members are in the base classes, ie the internal implementation, you
> > break
> > >>>> existing binaries. There isn't much a wrapper can do in that case.
> > >>>>
> > >>>> If you're proposing rebuilding gem5 on top of systemc, there are a
> > variety
> > >>>> of reasons I'm not proposing that which I've gone through
> > exhaustively (at
> > >>>> least I feel exhausted from it) in other places (you didn't miss it,
> > that
> > >>>> was internally at Google).
> > >>>>
> > >>>> This approach addresses best addresses the problem we (Google) are
> > trying
> > >>>> to solve, which 

Re: [gem5-dev] mount host FS in simulation?

[Jason Lowe-Power]

Hi Gabe,

I don't have any recollection that this is supported (though it would be
very cool). Then again, I'm often finding gem5 features that I didn't know
existed, so I could be wrong.

Jason

On Thu, Jun 7, 2018 at 3:09 PM Gabe Black  wrote:

> Hi folks. I should already know the answer to this, but I can't seem to
> find the emails, etc, that I had intended to read later which talked about
> this. Is there a way to mount bits of the host OS within the simulated
> system? I saw an email or maybe a wiki page talking about a technology or
> FS or something which made that work, but now I can't find where that was.
> Any tips would be appreciated.
>
> Gabe
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[gem5-dev] Change in gem5/gem5[master]: ruby: Revamp standalone SLICC script

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/10561 )


Change subject: ruby: Revamp standalone SLICC script
..

ruby: Revamp standalone SLICC script

There was some bitrot in the standalone SLICC script (util/slicc and
src/mem/slicc/main.py). Fix the changes to the SLICC interface and also
add some better documentation.

Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822
Signed-off-by: Jason Lowe-Power 
Reviewed-on: https://gem5-review.googlesource.com/10561
Reviewed-by: Nikos Nikoleris 
---
M src/mem/slicc/main.py
1 file changed, 23 insertions(+), 6 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/src/mem/slicc/main.py b/src/mem/slicc/main.py
index 05a5cdb..f2a4751 100644
--- a/src/mem/slicc/main.py
+++ b/src/mem/slicc/main.py
@@ -32,13 +32,19 @@

 from slicc.parser import SLICC

-usage="%prog [options]  ... "
+usage="%prog [options]  ... "
 version="%prog v0.4"
 brief_copyright='''
 Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
 Copyright (c) 2009 The Hewlett-Packard Development Company
 All Rights Reserved.
 '''
+help_details = '''This is intended to be used to process slicc files as a
+standalone script. This script assumes that it is running in a directory  
under

+gem5/ (e.g., gem5/temp). It takes a single argument: The path to a *.slicc
+file. By default it generates the C++ code in the directory generated/.  
This
+script can also generate the html SLICC output. See src/mem/slicc/main.py  
for

+more details.'''

 def nprint(format, *args):
 pass
@@ -53,6 +59,7 @@
 import optparse

 parser = optparse.OptionParser(usage=usage, version=version,
+   epilog=help_details,
description=brief_copyright)
 parser.add_option("-d", "--debug", default=False, action="store_true",
   help="Turn on PLY debugging")
@@ -60,7 +67,7 @@
   help="Path where C++ code output code goes")
 parser.add_option("-H", "--html-path",
   help="Path where html output goes")
-parser.add_option("-F", "--print-files",
+parser.add_option("-F", "--print-files", action='store_true',
   help="Print files that SLICC will generate")
 parser.add_option("--tb", "--traceback", action='store_true',
   help="print traceback on error")
@@ -72,12 +79,21 @@
 parser.print_help()
 sys.exit(2)

+slicc_file = files[0]
+if not slicc_file.endswith('.slicc'):
+print("Must specify a .slicc file with a list of state machine  
files")

+parser.print_help()
+sys.exit(2)
+
 output = nprint if opts.quiet else eprint

 output("SLICC v0.4")
 output("Parsing...")

-slicc = SLICC(files[0], verbose=True, debug=opts.debug,  
traceback=opts.tb)
+protocol_base =  
os.path.join(os.path.dirname(__file__), '..', 'protocol')
+slicc = SLICC(slicc_file, protocol_base, verbose=True,  
debug=opts.debug,

+  traceback=opts.tb)
+

 if opts.print_files:
 for i in sorted(slicc.files()):
@@ -86,13 +102,14 @@
 output("Processing AST...")
 slicc.process()

-output("Writing C++ files...")
-slicc.writeCodeFiles(opts.code_path)
-
 if opts.html_path:
 output("Writing HTML files...")
 slicc.writeHTMLFiles(opts.html_path)

+output("Writing C++ files...")
+slicc.writeCodeFiles(opts.code_path, [])
+
+
 output("SLICC is Done.")

 if __name__ == "__main__":

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Gerrit-Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822
Gerrit-Change-Number: 10561
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-MessageType: merged
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Re: [gem5-dev] systemc reviews

[Jason Lowe-Power]

I'll have some time next week to dig into this.

Cheers,
Jason

On Fri, Jun 8, 2018, 7:13 AM Dr.-Ing. Matthias Jung 
wrote:

> Hi Giacomo, Gabe,
>
> I'm a large supporter of SystemC because its 'the' IEEE standard for
> simulation, therefore I support always activities towards that direction.
> However I have a similar concern like Giacomo.
>
> I would prefer to just 'use' the SystemC kernel by accellera as kernel for
> gem5 in order to have a proper separation between model and kernel. I think
> its very interesting for many people to use gem5 in their SystemC
> environment also together with commercial IP SystemC models that have a
> closed source. With the current aimed approach it would be required to have
> access to the source code of all used models in the system and commercial
> SystemC tools like Synopsys Platform Architect etc. could not be used.
>
>
> Best,
> Matthias
>
> 8. Juni 2018 15:47, "Giacomo Travaglini" 
> schrieb:
>
> > Hi Gabe,
> >
> > I have had a quick glance at the patches and there's one thing I don't
> understand:
> >
> > It seems to me that you are sort of reimplementing the SystemC runtime
> kernel inside
> >
> > gem5 for scratch.
> >
> > Is there a reason for doing it? Can't we just link to the external
> SystemC library
> >
> > and just write some wrappers?
> >
> > Thanks in advance for the clarifications
> >
> > Giacomo
> >
> > 
> > From: gem5-dev  on behalf of Gabe Black <
> gabebl...@google.com>
> > Sent: 08 June 2018 06:32:52
> > To: gem5 Developer List
> > Subject: [gem5-dev] systemc reviews
> >
> > Hi folks. I've posted a lot of systemc reviews recently, and I expect to
> > keep doing so for the foreseeable future. To keep the pool of pending CLs
> > from growing from a lot to unmanageably a lot please don't let them sit
> too
> > long if you feel comfortable trying to review them. Alot of these earlier
> > ones aren't very interesting, they're just defining header files, stubbed
> > out implementations, or importing code from the Accellera version of
> > SystemC. There are a few that are a little more interesting though, to
> keep
> > you from getting bored ;-)
> >
> > Gabe
> > ___
> > gem5-dev mailing list
> > gem5-dev@gem5.org
> > http://m5sim.org/mailman/listinfo/gem5-dev
> > IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be
> > privileged. If you are not the intended recipient, please notify the
> sender immediately and do not
> > disclose the contents to any other person, use it for any purpose, or
> store or copy the information
> > in any medium. Thank you.
> > ___
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[gem5-dev] Change in gem5/gem5[master]: ruby: Revamp standalone SLICC script

[Jason Lowe-Power (Gerrit)]

Hello Nikos Nikoleris, Bradford Beckmann,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/10561

to look at the new patch set (#2).

Change subject: ruby: Revamp standalone SLICC script
..

ruby: Revamp standalone SLICC script

There was some bitrot in the standalone SLICC script (util/slicc and
src/mem/slicc/main.py). Fix the changes to the SLICC interface and also
add some better documentation.

Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/main.py
1 file changed, 23 insertions(+), 6 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: ruby: Revamp standalone SLICC script

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/10561



Change subject: ruby: Revamp standalone SLICC script
..

ruby: Revamp standalone SLICC script

There was some bitrot in the standalone SLICC script (util/slicc and
src/mem/slicc/main.py). Fix the changes to the SLICC interface and also
add some better documentation.

Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822
Signed-off-by: Jason Lowe-Power 
---
M src/mem/slicc/main.py
1 file changed, 23 insertions(+), 6 deletions(-)



diff --git a/src/mem/slicc/main.py b/src/mem/slicc/main.py
index 05a5cdb..89de38e 100644
--- a/src/mem/slicc/main.py
+++ b/src/mem/slicc/main.py
@@ -32,13 +32,19 @@

 from slicc.parser import SLICC

-usage="%prog [options]  ... "
+usage="%prog [options]  ... "
 version="%prog v0.4"
 brief_copyright='''
 Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
 Copyright (c) 2009 The Hewlett-Packard Development Company
 All Rights Reserved.
 '''
+help_details = '''This is intended to be used to process slicc files as a
+standalone script. This script assumes that it is running in a directory  
under

+gem5/ (e.g., gem5/temp). It takes a single argument: The path to a *.slicc
+file. By default it generates the C++ code in the directory generated/.  
This
+script can also generate the html SLICC output. See src/mem/slicc/main.py  
for

+more details.'''

 def nprint(format, *args):
 pass
@@ -53,6 +59,7 @@
 import optparse

 parser = optparse.OptionParser(usage=usage, version=version,
+   epilog=help_details,
description=brief_copyright)
 parser.add_option("-d", "--debug", default=False, action="store_true",
   help="Turn on PLY debugging")
@@ -60,7 +67,7 @@
   help="Path where C++ code output code goes")
 parser.add_option("-H", "--html-path",
   help="Path where html output goes")
-parser.add_option("-F", "--print-files",
+parser.add_option("-F", "--print-files", action='store_true',
   help="Print files that SLICC will generate")
 parser.add_option("--tb", "--traceback", action='store_true',
   help="print traceback on error")
@@ -72,12 +79,21 @@
 parser.print_help()
 sys.exit(2)

+slicc_file = files[0]
+if not slicc_file.endswith('.slicc'):
+print("Must specify a .slicc file with a list of state machine  
files")

+parser.print_help()
+sys.exit(2)
+
 output = nprint if opts.quiet else eprint

 output("SLICC v0.4")
 output("Parsing...")

-slicc = SLICC(files[0], verbose=True, debug=opts.debug,  
traceback=opts.tb)
+protocol_base =  
os.path.join(os.getcwd(), '..', 'src', 'mem', 'protocol')
+slicc = SLICC(slicc_file, protocol_base, verbose=True,  
debug=opts.debug,

+  traceback=opts.tb)
+

 if opts.print_files:
 for i in sorted(slicc.files()):
@@ -86,13 +102,14 @@
 output("Processing AST...")
 slicc.process()

-output("Writing C++ files...")
-slicc.writeCodeFiles(opts.code_path)
-
 if opts.html_path:
 output("Writing HTML files...")
 slicc.writeHTMLFiles(opts.html_path)

+output("Writing C++ files...")
+slicc.writeCodeFiles(opts.code_path, [])
+
+
 output("SLICC is Done.")

 if __name__ == "__main__":

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[gem5-dev] Change in gem5/gem5[master]: configs, learning-gem5: Fixed hello binary location

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/10521



Change subject: configs,learning-gem5: Fixed hello binary location
..

configs,learning-gem5: Fixed hello binary location

Change-Id: I6da0e3a2ec5801b382f5f76f94a1c0aad492f44c
---
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
4 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/configs/learning_gem5/part1/simple.py  
b/configs/learning_gem5/part1/simple.py

index 5336b44..c9868a3 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -88,7 +88,7 @@
 isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()

 # Run 'hello' and use the compiled ISA to find the binary
-binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
+binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello64-static'

 # Create a process for a simple "Hello World" application
 process = Process()
diff --git a/configs/learning_gem5/part1/two_level.py  
b/configs/learning_gem5/part1/two_level.py

index 51d51c4..214ae1f 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -66,7 +66,7 @@
 isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()

 # Default to running 'hello', use the compiled ISA to find the binary
-binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
+binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello64-static'

 # Check if there was a binary passed in via the command line and error if
 # there are too many arguments
diff --git a/configs/learning_gem5/part2/simple_cache.py  
b/configs/learning_gem5/part2/simple_cache.py

index 98078df..5eb150a 100644
--- a/configs/learning_gem5/part2/simple_cache.py
+++ b/configs/learning_gem5/part2/simple_cache.py
@@ -88,7 +88,7 @@
 process = Process()
 # Set the command
 # cmd is a list which begins with the executable (like argv)
-process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello']
+process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello64-static']
 # Set the cpu to use the process as its workload and create thread contexts
 system.cpu.workload = process
 system.cpu.createThreads()
diff --git a/configs/learning_gem5/part2/simple_memobj.py  
b/configs/learning_gem5/part2/simple_memobj.py

index 066bca0..e58bb2d 100644
--- a/configs/learning_gem5/part2/simple_memobj.py
+++ b/configs/learning_gem5/part2/simple_memobj.py
@@ -86,7 +86,7 @@
 process = Process()
 # Set the command
 # cmd is a list which begins with the executable (like argv)
-process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello']
+process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello64-static']
 # Set the cpu to use the process as its workload and create thread contexts
 system.cpu.workload = process
 system.cpu.createThreads()

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Re: [gem5-dev] RISC-V Full System Support?

[Jason Lowe-Power]

An option is to use "warn_once" to keep the warning, but not spam the
output.

Jason

On Tue, May 22, 2018 at 2:05 AM Robert Scheffel <
robert.scheff...@tu-dresden.de> wrote:

> Hi Hesham,
>
> I just want to clarify, why I changed the panic to a warning:
> In this patch, interrupts aren't supported at all, so an empty
> clearAll() function is sufficient. But I wanted to keep the warning, to
> let users know, that there is something missing and not implemented.
>
> Regards,
> Robert
>
> Am 17.05.2018 um 10:56 schrieb Hesham Almatary:
> > Hi Jason and Alec,
> >
> > Thanks for your replies. I pulled the baremetal patches and created a
> > simple system. It's able to run simple custom bootloader I have. Just
> > had to comment this line [1] as it kept being printed out.
> >
> > [1]
> https://gem5-review.googlesource.com/c/public/gem5/+/9061/4/src/arch/riscv/interrupts.hh#82
> >
> > Best,
> > Hesham
> >
> > On Wed, May 16, 2018 at 4:40 PM, Alec Roelke <ar...@virginia.edu> wrote:
> >> Hi Hesham,
> >>
> >> As Jason mentioned, there is some rudimentary support for FS simulation
> of
> >> RISC-V, but currently it doesn't support RISC-V's privilege modes.
> There
> >> are some additional patches that improve support, but those are also
> >> limited.  They can be found at:
> >>
> >>- https://gem5-review.googlesource.com/c/public/gem5/+/9161,
> together
> >>with https://gem5-review.googlesource.com/c/public/gem5/+/9821/1:
> add
> >>some support for fault handling (note that these patches are a little
> >>out-of-date and may have some conflicts with the latest version of
> gem5)
> >>- https://gem5-review.googlesource.com/c/public/gem5/+/9822/1: add
> >>support for URET, SRET, and MRET instructions
> >>
> >> There is ongoing work on FS support, but, in my case, it is something
> that
> >> I currently have to do on my free time, so I can't give you a good
> estimate
> >> of when it will be completed.
> >>
> >> Regards,
> >> Alec
> >>
> >> On Tue, May 15, 2018 at 1:41 PM, Jason Lowe-Power <ja...@lowepower.com>
> >> wrote:
> >>
> >>> Hi Heshem,
> >>>
> >>> There's a patch on our gerrit review site that has some support for FS
> in
> >>> RISC-V https://gem5-review.googlesource.com/c/public/gem5/+/9061/4. It
> >>> would be great if you could test it to see if it works for your system
> and
> >>> review it on gerrit.
> >>>
> >>> Cheers,
> >>> Jason
> >>>
> >>> On Tue, May 15, 2018 at 2:41 AM Hesham Almatary <
> heshamelmat...@gmail.com>
> >>> wrote:
> >>>
> >>>> Hi,
> >>>>
> >>>> Just wondering what the status of RISC-V full system support is. I'm
> >>>> not particularly interested in running Linux, just need support for M,
> >>>> S, U modes and MMU.
> >>>>
> >>>> If it's not supported, is anyone working on it? If yes, I would
> >>>> appreciate any hints when it might get upstream.
> >>>>
> >>>> Cheers,
> >>>> --
> >>>> Hesham
> >>>> ___
> >>>> gem5-dev mailing list
> >>>> gem5-dev@gem5.org
> >>>> http://m5sim.org/mailman/listinfo/gem5-dev
> >>>
> >>>
> >> ___
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> >> gem5-dev@gem5.org
> >> http://m5sim.org/mailman/listinfo/gem5-dev
> >
> >
> >
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[gem5-dev] Change in gem5/gem5[master]: tests, ext: Add a new testing library proposal

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#11) to the change  
originally created by Sean Wilson. (  
https://gem5-review.googlesource.com/4421 )


Change subject: tests,ext: Add a new testing library proposal
..

tests,ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson <spwils...@wisc.edu>
---
M configs/common/Simulation.py
A ext/testlib/FILES.rst
A ext/testlib/__init__.py
A ext/testlib/config.py
A ext/testlib/fixture.py
A ext/testlib/helper.py
A ext/testlib/loader.py
A ext/testlib/logger.py
A ext/testlib/main.py
A ext/testlib/query.py
A ext/testlib/result.py
A ext/testlib/runner/__init__.py
A ext/testlib/runner/parallel.py
A ext/testlib/runner/runner.py
A ext/testlib/suite.py
A ext/testlib/tee.py
A ext/testlib/terminal.py
A ext/testlib/test.py
A ext/testlib/uid.py
A ext/testlib/util.py
A tests/.gitignore
A tests/credentials.ini
A tests/gem5/__init__.py
A tests/gem5/fixture.py
A tests/gem5/suite.py
A tests/gem5/verifier.py
A tests/legacy-configs/run.py
A tests/main.py
28 files changed, 5,526 insertions(+), 1 deletion(-)


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[gem5-dev] Change in gem5/gem5[master]: tests: Add explicit build test

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/10121 )


Change subject: tests: Add explicit build test
..

tests: Add explicit build test

Change-Id: Ia613ab580b880a463c9cf0dd63f61497db31fe75
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A tests/gem5/test-build/test_build.py
1 file changed, 51 insertions(+), 0 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: tests: Add a simple example test

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#11) to the change  
originally created by Sean Wilson. (  
https://gem5-review.googlesource.com/4422 )


Change subject: tests: Add a simple example test
..

tests: Add a simple example test

Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12
Signed-off-by: Sean Wilson <spwils...@wisc.edu>
---
A tests/gem5/hello_se/ref/simerr
A tests/gem5/hello_se/ref/simout
A tests/gem5/hello_se/test_hello_se.py
3 files changed, 65 insertions(+), 0 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: tests: Add documentation for new testing code

[Jason Lowe-Power (Gerrit)]

Hello Sean Wilson, Gabe Black,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4882

to look at the new patch set (#11).

Change subject: tests: Add documentation for new testing code
..

tests: Add documentation for new testing code

Change-Id: Id62ad8e452e640073079e76c9ce5898cedee
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M CONTRIBUTING.md
A TESTING.md
2 files changed, 222 insertions(+), 7 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: tests: Add test for the m5-exit instruction.

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#11) to the change  
originally created by Sean Wilson. (  
https://gem5-review.googlesource.com/4423 )


Change subject: tests: Add test for the m5-exit instruction.
..

tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson <spwils...@wisc.edu>
---
A tests/gem5/m5_util/test_exit.py
A tests/test-progs/m5-exit/.gitignore
A tests/test-progs/m5-exit/src/Makefile.x86
A tests/test-progs/m5-exit/src/m5-exit.c
M util/m5/Makefile.x86
5 files changed, 99 insertions(+), 1 deletion(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Gerrit-Change-Number: 4423
Gerrit-PatchSet: 11
Gerrit-Owner: Sean Wilson <spwils...@wisc.edu>
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Re: [gem5-dev] RISC-V Full System Support?

[Jason Lowe-Power]

Hi Hesham,

It would be *very* helpful if you made this comment in gerrit. You can
easily create an account on gerrit (our code review system), and after
that, if you click on the line you can add a comment. After adding a
comment, you can click the blue "reply" button at the top of the page to
post it. By commenting on the changeset you help us make a better system!

Cheers,
Jason

On Thu, May 17, 2018 at 1:56 AM Hesham Almatary <heshamelmat...@gmail.com>
wrote:

> Hi Jason and Alec,
>
> Thanks for your replies. I pulled the baremetal patches and created a
> simple system. It's able to run simple custom bootloader I have. Just
> had to comment this line [1] as it kept being printed out.
>
> [1]
> https://gem5-review.googlesource.com/c/public/gem5/+/9061/4/src/arch/riscv/interrupts.hh#82
>
> Best,
> Hesham
>
> On Wed, May 16, 2018 at 4:40 PM, Alec Roelke <ar...@virginia.edu> wrote:
> > Hi Hesham,
> >
> > As Jason mentioned, there is some rudimentary support for FS simulation
> of
> > RISC-V, but currently it doesn't support RISC-V's privilege modes.  There
> > are some additional patches that improve support, but those are also
> > limited.  They can be found at:
> >
> >- https://gem5-review.googlesource.com/c/public/gem5/+/9161, together
> >with https://gem5-review.googlesource.com/c/public/gem5/+/9821/1: add
> >some support for fault handling (note that these patches are a little
> >out-of-date and may have some conflicts with the latest version of
> gem5)
> >- https://gem5-review.googlesource.com/c/public/gem5/+/9822/1: add
> >support for URET, SRET, and MRET instructions
> >
> > There is ongoing work on FS support, but, in my case, it is something
> that
> > I currently have to do on my free time, so I can't give you a good
> estimate
> > of when it will be completed.
> >
> > Regards,
> > Alec
> >
> > On Tue, May 15, 2018 at 1:41 PM, Jason Lowe-Power <ja...@lowepower.com>
> > wrote:
> >
> >> Hi Heshem,
> >>
> >> There's a patch on our gerrit review site that has some support for FS
> in
> >> RISC-V https://gem5-review.googlesource.com/c/public/gem5/+/9061/4. It
> >> would be great if you could test it to see if it works for your system
> and
> >> review it on gerrit.
> >>
> >> Cheers,
> >> Jason
> >>
> >> On Tue, May 15, 2018 at 2:41 AM Hesham Almatary <
> heshamelmat...@gmail.com>
> >> wrote:
> >>
> >>> Hi,
> >>>
> >>> Just wondering what the status of RISC-V full system support is. I'm
> >>> not particularly interested in running Linux, just need support for M,
> >>> S, U modes and MMU.
> >>>
> >>> If it's not supported, is anyone working on it? If yes, I would
> >>> appreciate any hints when it might get upstream.
> >>>
> >>> Cheers,
> >>> --
> >>> Hesham
> >>> ___
> >>> gem5-dev mailing list
> >>> gem5-dev@gem5.org
> >>> http://m5sim.org/mailman/listinfo/gem5-dev
> >>
> >>
> > ___
> > gem5-dev mailing list
> > gem5-dev@gem5.org
> > http://m5sim.org/mailman/listinfo/gem5-dev
>
>
>
> --
> Hesham
>
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Re: [gem5-dev] RISC-V Full System Support?

[Jason Lowe-Power]

Hi Heshem,

There's a patch on our gerrit review site that has some support for FS in
RISC-V https://gem5-review.googlesource.com/c/public/gem5/+/9061/4. It
would be great if you could test it to see if it works for your system and
review it on gerrit.

Cheers,
Jason

On Tue, May 15, 2018 at 2:41 AM Hesham Almatary 
wrote:

> Hi,
>
> Just wondering what the status of RISC-V full system support is. I'm
> not particularly interested in running Linux, just need support for M,
> S, U modes and MMU.
>
> If it's not supported, is anyone working on it? If yes, I would
> appreciate any hints when it might get upstream.
>
> Cheers,
> --
> Hesham
> ___
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Re: [gem5-dev] Fix opengrok or remove the link from gem.org sidebar

[Jason Lowe-Power]

Hi Ciro (and Gabe),

We're working on this... it's just slow. We're weighing our options for how
to manage hosting and hosting providers. This is just something that's
going to take time :).

Cheers,
Jason

On Sun, Apr 22, 2018 at 2:28 PM Ciro Santilli  wrote:

> Who would pay for the service?
>
>
> Does something prevent giving Gabe server access?
>
>
> @Gabe: is there any one you like?
>
> 
> From: gem5-dev  on behalf of Andreas Sandberg <
> andreas.sandb...@arm.com>
> Sent: Wednesday, April 11, 2018 2:41:43 PM
> To: gem5 Developer List; Gabe Black
> Subject: Re: [gem5-dev] Fix opengrok or remove the link from gem.org
> sidebar
>
> How about switching to a hosted service that integrates with our git
> repositories directly?
>
> I have played around with insight.io, but it seems like they require you
> to login to the server using your GitHub credentials to access public
> repos. Something that doesn't require a separate login would be ideal.
> Does anyone know of anything?
>
> Cheers,
> Andreas
>
>
> On 07/04/2018 22:12, Gabe Black wrote:
> > I don't think removing the link is helpful. We should fix the service it
> > links to.
> >
> > Gabe
> >
> > On Sat, Apr 7, 2018 at 1:14 PM, Ciro Santilli 
> wrote:
> >
> >> Ping.
> >>
> >>
> >> Can we remove the link until it gets fixed?
> >>
> >> 
> >> From: gem5-dev  on behalf of Gabe Black <
> >> gabebl...@google.com>
> >> Sent: Tuesday, March 13, 2018 10:33:44 PM
> >> To: gem5 Developer List
> >> Subject: Re: [gem5-dev] Fix opengrok or remove the link from gem.org
> >> sidebar
> >>
> >> For whatever reason, I find that my administrative access on gem5.org
> >> comes
> >> and goes, and has currently went. I think Ali set up opengrok and so
> would
> >> be best placed to fix it. It was useful back when we first set it up,
> and
> >> it would be good to fix it.
> >>
> >> Gabe
> >>
> >> On Tue, Mar 13, 2018 at 5:56 AM, Ciro Santilli 
> >> wrote:
> >>
> >>> Did you manage to fix it? Still seems broken to me.
> >>>
> >>>
> >>> If not, can we just remove the link for now, and put it back up if
> >> someone
> >>> fixes it?
> >>>
> >>>
> >>> Looks bad for the project to have a broken link on the sidebar 
> >>>
> >>> 
> >>> From: gem5-dev  on behalf of Gabe Black <
> >>> gabebl...@google.com>
> >>> Sent: Tuesday, February 27, 2018 12:40:39 AM
> >>> To: gem5 Developer List
> >>> Subject: Re: [gem5-dev] Fix opengrok or remove the link from gem.org
> >>> sidebar
> >>>
> >>> It looks like changing to git would be pretty easy, since that's
> handled
> >> in
> >>> /etc/cron.daily/opengrok:
> >>>
> >>> #!/bin/bash
> >>> cd /var/opengrok/src/gem5
> >>> hg pull
> >>> hg update
> >>> /z/opengrok/bin/OpenGrok update
> >>>
> >>>
> >>> On Mon, Feb 26, 2018 at 4:39 PM, Gabe Black 
> >> wrote:
>  Also it doesn't help that I don't have permission to access any of the
>  logs for tomcat or apache. But looking at the output of ps -ef, I
> don't
> >>> see
>  tomcat running, so I don't think the opengrok server bit is running
> >> which
>  would fit with the other bit of log I was able to access.
> 
>  Also I notice that the source opengrok is indexing is mercurial. It
>  wouldn't be a bad idea to change that over to git.
> 
>  Gabe
> 
>  On Mon, Feb 26, 2018 at 4:30 PM, Gabe Black 
> >>> wrote:
> > I'm not up on how opengrok is hooked into the gem5.org site, but I
> > ssh-ed in and saw this in one of the log files:
> >
> > 2018-02-24 06:42:31.799-0500 INFO t1 Indexer.sendToConfigHost: Send
> > configuration to: localhost:2424
> > 2018-02-24 06:42:31.813-0500 SEVERE t1 Indexer.sendToConfigHost:
> >> Failed
> > to send configuration to localhost:2424 (is web application server
> >>> running
> > with opengrok deploye
> > d?)
> >
> > It looks like some of the config may have been damaged, or some piece
> >> of
> > the setup hasn't been started like it's supposed to be. Without more
> > information about how it's *supposed* to work, it's hard to say.
> >
> > Gabe
> >
> > On Fri, Feb 23, 2018 at 6:08 AM, Ciro Santilli <
> ciro.santi...@arm.com
> > wrote:
> >
> >> On http://gem5.org on the sidebar there is a link "Search Source"
> >> that
> >> points to http://grok.gem5.org/ which gives "Service Unavailable".
> >>
> >>
> >> Can we either fix the instance, or remove the link?
> >>
> >>
> >> Personally, I'd just remove it, GitHub + ctags is enough for me.
> >>
> >>
> >> IMPORTANT NOTICE: The contents of this email and any attachments are
> >> confidential and may also be privileged. If you are not the intended
> >> recipient, please notify the 

Re: [gem5-dev] Collaboration on Patches?

[Jason Lowe-Power]

Hi Alec,

On github you should be using a different branch other than master (say,
riscv-fs). Then, you can just rebase that branch on top of master (or
origin/master if you've got other commits on master). I often use "git
rebase -i master" when doing this. Then, during the rebase you can
squash/fixup and reword commits so they fit the gem5 style guides. After
rebasing, you can simply push to gem5.googlesource.com to create the review
requests :).

With rebasing you do lose the "local" history, but if you want to keep that
you can simply rebase to a branch with a different name (say,
upstream/riscv-fs in this example). I would argue that it's OK to lose the
history in most of these cases as it's really the final cleaned-up commits
that matter.

I hope this is what you were asking :). I should do a write up on what my
git+gem5 workflow is... I'll put that on the (increasingly long) list of
blog posts I need to write.

Cheers,
Jason

On Sat, Apr 21, 2018 at 5:29 PM Alec Roelke <ar...@virginia.edu> wrote:

> That's essentially what I was getting at, but I think you put it better.
> If I do that, then what is the best way to create a patch from the changes?
>
> On Fri, Apr 20, 2018 at 6:15 PM, Jason Lowe-Power <ja...@lowepower.com>
> wrote:
>
> > Hi Alec,
> >
> > What you're describing is *hard* and requires a lot of coordination
> between
> > people. I think the best way to do it today is to use something
> out-of-band
> > like a github mirror and then have one person rebase, etc. and submit to
> > the mainline. That's basically what AMD and ARM do internally. It's
> harder
> > to do with a geographically diverse set of people.
> >
> > If you need hosting and want to use gerrit for code review during
> > development, we can set you up with a repository on
> gem5.googlesource.com.
> > However, I think the path of least resistance is to set up a github repo.
> > E.g., I have a github repo for my research group and that's what we used
> > when I was at Wisconsin, too.
> >
> > Cheers,
> > Jason
> >
> > On Thu, Apr 19, 2018 at 12:02 PM Alec Roelke <ar...@virginia.edu> wrote:
> >
> > > I'm not trying to suggest that there should be an "official" way to
> > > collaborate on patches, since that's probably not a common enough
> > > occurrence to warrant the effort of maintaining such a feature; I was
> > > mostly wondering if there was a way to leverage what's already
> available
> > to
> > > do it.  Downloading and uploading revisions to others' patches is
> clunky
> > > and, as Gabe mentioned, can lead to loss of work.  I was thinking more
> of
> > > something like what Jason mentioned with creating a "riscv-fs" clone of
> > > gem5 in GitHub or similar and creating patches out of commits to it
> > > somehow.  Is that possible?
> > >
> > > I think overall what I'm trying to figure out is proper version control
> > for
> > > patches before they're uploaded to Gerrit so that two or more people
> can
> > > work on one thing without worrying about losing work to conflicts.
> > >
> > > On Wed, Apr 18, 2018 at 8:49 PM, Gabe Black <gabebl...@google.com>
> > wrote:
> > >
> > > > In my past experience with gerrit, anybody can overwrite anybody
> else's
> > > > patch. That may not be true for our instance here, but I suspect it
> is.
> > > All
> > > > you have to do is make sure the Change-Id: field is the same since
> > that's
> > > > how gerrit identifies changes. It's generally something to avoid
> since
> > it
> > > > can be inconvenient for the original author to download your new
> > version
> > > to
> > > > replace their own locally, to make your edits locally, etc., to avoid
> > > > blowing away your changes when they upload their own new version.
> > > >
> > > > I think the linux kernel uses both multiple git repositories and
> > multiple
> > > > git branches within those repositories to separate independent
> > projects.
> > > A
> > > > big problem with that approach is that it takes concerted effort to
> > keep
> > > > all those different threads in sync and make sure they reconverge at
> > all,
> > > > and ideally frequently. They have vastly more developers and projects
> > to
> > > > coordinate than we do, and I don't think the overhead of that
> approach
> > > > makes a lot of sense for us at this point and with our current
> capacity
> > > for
> > > &g

Re: [gem5-dev] Collaboration on Patches?

[Jason Lowe-Power]

Hi Alec,

What you're describing is *hard* and requires a lot of coordination between
people. I think the best way to do it today is to use something out-of-band
like a github mirror and then have one person rebase, etc. and submit to
the mainline. That's basically what AMD and ARM do internally. It's harder
to do with a geographically diverse set of people.

If you need hosting and want to use gerrit for code review during
development, we can set you up with a repository on gem5.googlesource.com.
However, I think the path of least resistance is to set up a github repo.
E.g., I have a github repo for my research group and that's what we used
when I was at Wisconsin, too.

Cheers,
Jason

On Thu, Apr 19, 2018 at 12:02 PM Alec Roelke <ar...@virginia.edu> wrote:

> I'm not trying to suggest that there should be an "official" way to
> collaborate on patches, since that's probably not a common enough
> occurrence to warrant the effort of maintaining such a feature; I was
> mostly wondering if there was a way to leverage what's already available to
> do it.  Downloading and uploading revisions to others' patches is clunky
> and, as Gabe mentioned, can lead to loss of work.  I was thinking more of
> something like what Jason mentioned with creating a "riscv-fs" clone of
> gem5 in GitHub or similar and creating patches out of commits to it
> somehow.  Is that possible?
>
> I think overall what I'm trying to figure out is proper version control for
> patches before they're uploaded to Gerrit so that two or more people can
> work on one thing without worrying about losing work to conflicts.
>
> On Wed, Apr 18, 2018 at 8:49 PM, Gabe Black <gabebl...@google.com> wrote:
>
> > In my past experience with gerrit, anybody can overwrite anybody else's
> > patch. That may not be true for our instance here, but I suspect it is.
> All
> > you have to do is make sure the Change-Id: field is the same since that's
> > how gerrit identifies changes. It's generally something to avoid since it
> > can be inconvenient for the original author to download your new version
> to
> > replace their own locally, to make your edits locally, etc., to avoid
> > blowing away your changes when they upload their own new version.
> >
> > I think the linux kernel uses both multiple git repositories and multiple
> > git branches within those repositories to separate independent projects.
> A
> > big problem with that approach is that it takes concerted effort to keep
> > all those different threads in sync and make sure they reconverge at all,
> > and ideally frequently. They have vastly more developers and projects to
> > coordinate than we do, and I don't think the overhead of that approach
> > makes a lot of sense for us at this point and with our current capacity
> for
> > administrative overhead.
> >
> > If you want to push up your own independent version of somebody's CL for
> > some reason, all you have to do is replace the Change-Id field (delete it
> > and let git recreate it with a new value, for instance) and gerrit will
> > treat it as a new patch even if everything else is the same. There are
> > other ways to put changes up on gerrit which are work in progress sorts
> of
> > things. Those used to be draft changes, but I think they (the gerrit
> > developers) reworked that into one or two similar but different
> features. I
> > think one is actually called a work in progress CL?
> >
> > Gabe
> >
> > On Wed, Apr 18, 2018 at 3:18 PM, Jason Lowe-Power <ja...@lowepower.com>
> > wrote:
> >
> > > Hi Alec,
> > >
> > > First, I'm not sure if collaborating on a single changeset is a common
> > use
> > > case for code review platforms. Though, I have run into a number of
> times
> > > where it would have been useful.
> > >
> > > Am I understanding your suggestion correctly? What you're envisioning
> is
> > > there would be a feature branch (say, riscv-fs) and many people could
> > push
> > > changesets onto that branch. Then, when the feature is working you
> would
> > > merge into master? Or, squash and go through code review? I'm not sure
> > how
> > > the final part would work.
> > >
> > > I'm open to this kind of workflow. We can create branches on gerrit.
> > > Another option is what ARM and AMD are doing which is having their own
> > repo
> > > hosted on gem5.googlesource.com.
> > >
> > > What does the Linux kernel do in this case, I wonder. They have done a
> > good
> > > job working out procedures for massive open source development. They
> are
> >

[gem5-dev] Change in gem5/gem5[master]: tests: Add documentation for new testing code

[Jason Lowe-Power (Gerrit)]

Hello Sean Wilson, Gabe Black,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/4882

to look at the new patch set (#10).

Change subject: tests: Add documentation for new testing code
..

tests: Add documentation for new testing code

Change-Id: Id62ad8e452e640073079e76c9ce5898cedee
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M CONTRIBUTING.md
A TESTING.md
2 files changed, 218 insertions(+), 7 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id62ad8e452e640073079e76c9ce5898cedee
Gerrit-Change-Number: 4882
Gerrit-PatchSet: 10
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Sean Wilson <spwils...@wisc.edu>
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[gem5-dev] Change in gem5/gem5[master]: tests: Add explicit build test

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/10121



Change subject: tests: Add explicit build test
..

tests: Add explicit build test

Change-Id: Ia613ab580b880a463c9cf0dd63f61497db31fe75
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A tests/gem5/test-build/test_build.py
1 file changed, 24 insertions(+), 0 deletions(-)



diff --git a/tests/gem5/test-build/test_build.py  
b/tests/gem5/test-build/test_build.py

new file mode 100644
index 000..e991eed
--- /dev/null
+++ b/tests/gem5/test-build/test_build.py
@@ -0,0 +1,24 @@
+'''
+Test file for simply building gem5
+'''
+import re
+import os
+from testlib import *
+
+functions = []
+for isa in constants.supported_isas:
+for variant in constants.supported_variants:
+
+tags = {
+constants.isa_tag_type: set([isa]),
+constants.variant_tag_type: set([variant]),
+constants.length_tag_type: set([constants.quick_tag]),
+}
+
+name = 'build-{isa}-{var}'.format(isa=isa, var=variant)
+fixture = Gem5Fixture(isa, variant, tags=tags)
+
+function = TestFunction(lambda fixtures: True, name,
+fixtures=[fixture])
+
+TestSuite(name, [function], tags=tags, fail_fast=True)

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia613ab580b880a463c9cf0dd63f61497db31fe75
Gerrit-Change-Number: 10121
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in gem5/gem5[master]: tests: Add test for the m5-exit instruction.

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#10) to the change  
originally created by Sean Wilson. (  
https://gem5-review.googlesource.com/4423 )


Change subject: tests: Add test for the m5-exit instruction.
..

tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson <spwils...@wisc.edu>
---
A tests/gem5/m5_util/test_exit.py
A tests/test-progs/m5-exit/.gitignore
A tests/test-progs/m5-exit/src/Makefile.x86
A tests/test-progs/m5-exit/src/m5-exit.c
M util/m5/Makefile.x86
5 files changed, 71 insertions(+), 1 deletion(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Gerrit-Change-Number: 4423
Gerrit-PatchSet: 10
Gerrit-Owner: Sean Wilson <spwils...@wisc.edu>
Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in gem5/gem5[master]: tests, ext: Add a new testing library proposal

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#10) to the change  
originally created by Sean Wilson. (  
https://gem5-review.googlesource.com/4421 )


Change subject: tests,ext: Add a new testing library proposal
..

tests,ext: Add a new testing library proposal

The new test library is split into two parts: The framework which resides
in ext/, and the gem5 helping components in /tests/gem5.

Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Signed-off-by: Sean Wilson <spwils...@wisc.edu>
---
M configs/common/Simulation.py
A ext/testlib/FILES.rst
A ext/testlib/__init__.py
A ext/testlib/config.py
A ext/testlib/fixture.py
A ext/testlib/helper.py
A ext/testlib/loader.py
A ext/testlib/logger.py
A ext/testlib/main.py
A ext/testlib/query.py
A ext/testlib/result.py
A ext/testlib/runner/__init__.py
A ext/testlib/runner/parallel.py
A ext/testlib/runner/runner.py
A ext/testlib/suite.py
A ext/testlib/tee.py
A ext/testlib/terminal.py
A ext/testlib/test.py
A ext/testlib/uid.py
A ext/testlib/util.py
A tests/.gitignore
A tests/credentials.ini
A tests/gem5/__init__.py
A tests/gem5/fixture.py
A tests/gem5/suite.py
A tests/gem5/verifier.py
A tests/legacy-configs/run.py
A tests/main.py
28 files changed, 4,906 insertions(+), 1 deletion(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9
Gerrit-Change-Number: 4421
Gerrit-PatchSet: 10
Gerrit-Owner: Sean Wilson <spwils...@wisc.edu>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Sean Wilson <spwils...@wisc.edu>
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[gem5-dev] Change in gem5/gem5[master]: docs: Fix power model doxygen

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9981 )


Change subject: docs: Fix power model doxygen
..

docs: Fix power model doxygen

Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/9981
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
---
M src/doc/power_thermal_model.doxygen
M src/sim/power/power_model.hh
M src/sim/power/thermal_model.hh
3 files changed, 5 insertions(+), 0 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/src/doc/power_thermal_model.doxygen  
b/src/doc/power_thermal_model.doxygen

index 8b636ab..8fc3c0d 100644
--- a/src/doc/power_thermal_model.doxygen
+++ b/src/doc/power_thermal_model.doxygen
@@ -126,3 +126,4 @@
   user to define a power model as an equation involving several statistics.
   There's also some automatic (or "magic") variables such as "temp", which
   reports temperature.
+*/
diff --git a/src/sim/power/power_model.hh b/src/sim/power/power_model.hh
index e482b80..97357d2 100644
--- a/src/sim/power/power_model.hh
+++ b/src/sim/power/power_model.hh
@@ -110,6 +110,8 @@
 };

 /**
+ * @sa \ref gem5PowerModel "gem5 Power Model"
+ *
  * A PowerModel is a class containing a power model for a SimObject.
  * The PM describes the power consumption for every power state.
  */
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index b47061d..9a0e452 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -139,6 +139,8 @@


 /**
+ * @sa \ref gem5PowerModel "gem5 Thermal Model"
+ *
  * A ThermalModel is the element which ties all thermal objects
  * together and provides the thermal solver to the system.
  * It is reponsible for updating temperature for all Thermal

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50
Gerrit-Change-Number: 9981
Gerrit-PatchSet: 4
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Anouk Van Laer <anouk.vanl...@arm.com>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-MessageType: merged
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Re: [gem5-dev] Collaboration on Patches?

[Jason Lowe-Power]

Hi Alec,

First, I'm not sure if collaborating on a single changeset is a common use
case for code review platforms. Though, I have run into a number of times
where it would have been useful.

Am I understanding your suggestion correctly? What you're envisioning is
there would be a feature branch (say, riscv-fs) and many people could push
changesets onto that branch. Then, when the feature is working you would
merge into master? Or, squash and go through code review? I'm not sure how
the final part would work.

I'm open to this kind of workflow. We can create branches on gerrit.
Another option is what ARM and AMD are doing which is having their own repo
hosted on gem5.googlesource.com.

What does the Linux kernel do in this case, I wonder. They have done a good
job working out procedures for massive open source development. They are
usually a good inspiration.

Second, as a maintainer, I believe you have enough access to just overwrite
someone else's commit. For instance, if you download a changeset, then
rebase, then push to refs/for/master it will update the review request. So,
as a maintainer, you can make a small change instead of asking the original
author. (I think this is right... I know *I* can modify patches and I think
it's the maintainer flag, not admin. If I'm wrong we can talk about
changing this permission.)

Cheers,
Jason

On Wed, Apr 18, 2018 at 1:02 PM Alec Roelke  wrote:

> Hi Everyone,
>
> Is there a way to allow multiple people to collaborate on a patch?  Right
> now it looks to me like the only person who can make changes to a patch is
> the owner, which means that others' contributions have to be manually
> added.  Would it be possible for a person to create a personal branch of
> gem5 on GitHub or other git repository and then somehow push changes from
> there to Gerrit?
>
> Thanks,
> Alec Roelke
> ___
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[gem5-dev] Change in gem5/gem5[master]: docs: Fix power model doxygen

[Jason Lowe-Power (Gerrit)]

Hello Anouk Van Laer,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/9981

to look at the new patch set (#3).

Change subject: docs: Fix power model doxygen
..

docs: Fix power model doxygen

Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/doc/power_thermal_model.doxygen
M src/sim/power/power_model.hh
M src/sim/power/thermal_model.hh
3 files changed, 5 insertions(+), 0 deletions(-)


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Gerrit-Change-Number: 9981
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Anouk Van Laer <anouk.vanl...@arm.com>
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[gem5-dev] Change in gem5/gem5[master]: docs: Fix power model doxygen

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/9981 )


Change subject: docs: Fix power model doxygen
..

docs: Fix power model doxygen

Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/doc/power_thermal_model.doxygen
M src/sim/power/power_model.hh
M src/sim/power/thermal_model.hh
3 files changed, 5 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50
Gerrit-Change-Number: 9981
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in gem5/gem5[master]: docs: Fix power model doxygen

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/9981



Change subject: docs: Fix power model doxygen
..

docs: Fix power model doxygen

Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/doc/power_thermal_model.doxygen
M src/sim/power/power_model.hh
2 files changed, 3 insertions(+), 0 deletions(-)



diff --git a/src/doc/power_thermal_model.doxygen  
b/src/doc/power_thermal_model.doxygen

index 8b636ab..8fc3c0d 100644
--- a/src/doc/power_thermal_model.doxygen
+++ b/src/doc/power_thermal_model.doxygen
@@ -126,3 +126,4 @@
   user to define a power model as an equation involving several statistics.
   There's also some automatic (or "magic") variables such as "temp", which
   reports temperature.
+*/
diff --git a/src/sim/power/power_model.hh b/src/sim/power/power_model.hh
index e482b80..97357d2 100644
--- a/src/sim/power/power_model.hh
+++ b/src/sim/power/power_model.hh
@@ -110,6 +110,8 @@
 };

 /**
+ * @sa \ref gem5PowerModel "gem5 Power Model"
+ *
  * A PowerModel is a class containing a power model for a SimObject.
  * The PM describes the power consumption for every power state.
  */

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Re: [gem5-dev] Fwd: Make me a collaborator on GitHub to better manage issues

[Jason Lowe-Power]

Definitely dev. gem5-users is primarily for questions about how to use gem5.

Cheers,
Jason

On Tue, Apr 10, 2018 at 7:24 AM Ciro Santilli <ciro.santi...@gmail.com>
wrote:

> Should bugs be reported on gem5-dev or gem5-users? -dev I expect, but
> let's confirm.
>
> On Mon, Apr 9, 2018 at 10:37 PM, Jason Lowe-Power <ja...@lowepower.com>
> wrote:
> > Hi Ciro,
> >
> > I think deactivating the github issues makes sense. And, I'll happily
> sign
> > off on a patch to the CONTRIBUTING document if you want to create a quick
> > review request :).
> >
> > @Ali: Could you add me to the gem5 github group? I can take care of
> > removing the issue tracker and other github admin stuff.
> >
> > Cheers,
> > Jason
> >
> > On Mon, Apr 9, 2018 at 2:17 PM Ciro Santilli <ciro.santi...@gmail.com>
> > wrote:
> >
> >> No problem Jason,
> >>
> >> Do we think we should delete the GitHub issues completely or just
> >> leave it there?
> >>
> >> If not, people will still open issues there, and what should we do about
> >> those?
> >>
> >> An intermediate approach is to add a CONTRIBUTING.md saying that "the
> >> official issue tracker is the mailing list".
> >> ___
> >> gem5-dev mailing list
> >> gem5-dev@gem5.org
> >> http://m5sim.org/mailman/listinfo/gem5-dev
> > ___
> > gem5-dev mailing list
> > gem5-dev@gem5.org
> > http://m5sim.org/mailman/listinfo/gem5-dev
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Re: [gem5-dev] Fwd: Make me a collaborator on GitHub to better manage issues

[Jason Lowe-Power]

Hi Ciro,

I think deactivating the github issues makes sense. And, I'll happily sign
off on a patch to the CONTRIBUTING document if you want to create a quick
review request :).

@Ali: Could you add me to the gem5 github group? I can take care of
removing the issue tracker and other github admin stuff.

Cheers,
Jason

On Mon, Apr 9, 2018 at 2:17 PM Ciro Santilli 
wrote:

> No problem Jason,
>
> Do we think we should delete the GitHub issues completely or just
> leave it there?
>
> If not, people will still open issues there, and what should we do about
> those?
>
> An intermediate approach is to add a CONTRIBUTING.md saying that "the
> official issue tracker is the mailing list".
> ___
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> http://m5sim.org/mailman/listinfo/gem5-dev
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Re: [gem5-dev] Fwd: Make me a collaborator on GitHub to better manage issues

[Jason Lowe-Power]

Hi Ciro,

First of all, we appreciate your efforts to further document gem5 and
answer questions on the gem5 users list!

Right now, we're really just using github as a backup mirror of gem5. I'm
not sure why this was started initially, TBH. It doesn't seem necessary now
that we are hosting the code on Google's cloud. I really don't like the
idea of having a fragmented infrastructure. It would be best if everything
gem5 was in the same place.

As far as an issue tracker goes... the main problem is that we don't have
anyone to actually *solve* any issues/bugs that people find. Almost all of
our contributors are working full time in research positions or as grad
students and cannot be expected to fix bugs unrelated to their research
directions. What I believe happened with the Flyspray (and what I would
expect to happen with any issue tracker) is that a huge number of issues
built up over time. Eventually, it became useless as a place for
documenting issues because no one tracked how commits effected the issues
reported.

The reasons I don't want an issue tracker aren't because of problems with
how it would work, how emails would be sent, spam, etc. It's much more the
question "how will it help the community?" and "will the benefits out
weight the costs?" In this case, costs include time to manage, but also
confusion for new community members on how to communicate with the rest of
the community.

What I believe we need is more infrastructure for gem5. We need people who
can manage an issue tracker, fix bugs, implement shared features, and keep
the general infrastructure up to date. To do this (again, IMO) we need to
two things: 1) money to pay someone to do this, and 2) someone willing to
coordinate/manage everything.

This discussion is related to the problems on gem5.org as well. We've been
trying to move as much of the infrastructure as possible to the cloud
because it's hard to find community members with the time/know how to
manage everything internally. For instance, it seems like it would be good
to get OpenGrok back up, but I don't even know who set it up! It was
probably one of Steve's students who long ago moved on to other things.
Even getting rid of the link is hard... I don't know who has access to
change that page (I don't).

gem5 is a weird project. I really haven't seen anything like it. Most of
the contributors are only around for a few years while they are getting
their PhD then they leave. This churn in contributors is clearly makes some
project management activities very hard.

Sorry for the long message. I wanted to give you (and everyone else
reading) a little bit of context and history.

I (we) are very open to new contributors and people helping out with the
project. If you have ideas on how to make things better we're listening!
Although I argued against using an issue tracker, I'm open to the idea if
I'm convinced that it will help the community.

Thanks again for all of your contributions so far! I look forward to
working with you!

Cheers,
Jason

-------
Jason Lowe-Power
Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
jlowepo...@ucdavis.edu


On Mon, Apr 9, 2018 at 5:41 AM Ciro Santilli <ciro.santi...@gmail.com>
wrote:

> If made collaborator, I commit to keep every spam out. But there is
> little to no spam on GitHub by default anyways.
>
> I feel that if users want to use GitHub issues, which seems to be the
> case, we should cater for their preferred communication mechanism.
>
> Issue trackers have several advantages, notably:
>
> - open close status immediately visible, which I intend to maintain on
> a best effort basis. But it is better than the mailing list, where you
> have to browse N emails before finding out.
> - you can opt in for notifications only from certain threads
> - you can reply to messages even though you weren't subscribed when
> they were made:
>
> https://webapps.stackexchange.com/questions/23197/reply-to-mailman-archived-message
> Notably, if new maintainers come along, they can't mention that some
> old bug was closed.
> - tagging, specially for archs
> - neater markdown formatting
>
> We don't need to make it an official mechanism, but I'd rather let
> people use their preferred method.
>
> Also anyone easily subscribe and unsubscribed to receive an email
> whenever a new issue is created, much like the mailing list.
>
> On Mon, Apr 9, 2018 at 1:29 PM, Andreas Sandberg
> <andreas.sandb...@arm.com> wrote:
> > Hi Everyone,
> >
> > I think the first thing we need to establish is whether we want to use
> > GitHub for issue tracking in the first place. The issue tracker there
> > was left enabled by accident.
> >
> > As some of you may recall, we used to run a Flyspray-based issue tracker
> > a long time ago. If memory serves me right, 

Re: [gem5-dev] Gem5 support for RISC-V 32-bit binaries

[Jason Lowe-Power]

Hi Raul,

Since gem5 is an open source project, you're invited to implement riscv32
support yourself! There's some documentation on how to get started on the
gem5 wiki and in the CONTRIBUTING and MAINTAINERS files.

32-bit RISC-V shouldn't be too much different than the 64-bit
implementation. You should be able to dive into the code in src/arch/riscv
and figure out what's going on. We would love more contributors!!

Cheers,
Jason

On Mon, Mar 26, 2018 at 11:44 AM Raul Garcia 
wrote:

> Hello Robert,
>
>
> Thanks for your reply, some of of us would appreciate the riscv32 support.
>
>
> Regards,
> Raul.
>
>
> 
> From: gem5-dev [gem5-dev-boun...@gem5.org] on behalf of Robert Scheffel [
> robert.scheff...@tu-dresden.de]
> Sent: Monday, March 26, 2018 7:31 PM
> To: gem5-dev@gem5.org
> Subject: Re: [gem5-dev] Gem5 support for RISC-V 32-bit binaries
>
> Hello Raul,
>
> I wanted to start implementing support for rv32 binaries in a couple of
> weeks, but currently I can't estimate the effort. So unfortunately I
> can't tell, when it will be available.
>
> Regards,
> Robert
>
> Am 26.03.2018 um 15:28 schrieb Raul Garcia:
> > Hello All,
> >
> >
> > I would like to simulate a RISCV32 binary generated with the
> riscv32-unknown-elf-gcc compiler.
> > I tried to run this binary on Gem5 but I got an error. According to the
> thread below there is support for 64-bit binaries. I would like to know if
> is there a GEM5 version that supports RISC-V 32-bit binaries, a workaround
> that can be used, or if are there plans in the future to support it.
> >
> >
> > https://www.mail-archive.com/gem5-users@gem5.org/msg13556.html
> >
> >
> > Regards,
> > Raul.
> > ___
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> > gem5-dev@gem5.org
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> >
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[gem5-dev] Change in public/gem5[master]: mem-cache: fix missing overrides in repl policies

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9321 )


Change subject: mem-cache: fix missing overrides in repl policies
..

mem-cache: fix missing overrides in repl policies

Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/9321
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.hh
2 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/cache/replacement_policies/lru_rp.hh  
b/src/mem/cache/replacement_policies/lru_rp.hh

index 3e5efe6..2dd7e86 100644
--- a/src/mem/cache/replacement_policies/lru_rp.hh
+++ b/src/mem/cache/replacement_policies/lru_rp.hh
@@ -62,7 +62,7 @@
  *
  * @param blk Cache block to be touched.
  */
-void touch(CacheBlk *blk);
+void touch(CacheBlk *blk) override;

 /**
  * Reset replacement data for a block. Used when a block is inserted.
@@ -70,7 +70,7 @@
  *
  * @param blk Cache block to be reset.
  */
-void reset(CacheBlk *blk);
+void reset(CacheBlk *blk) override;

 /**
  * Find replacement victim using LRU timestamps.
diff --git a/src/mem/cache/replacement_policies/mru_rp.hh  
b/src/mem/cache/replacement_policies/mru_rp.hh

index d947d7c..fd9a29d 100644
--- a/src/mem/cache/replacement_policies/mru_rp.hh
+++ b/src/mem/cache/replacement_policies/mru_rp.hh
@@ -62,7 +62,7 @@
  *
  * @param blk Cache block to be touched.
  */
-void touch(CacheBlk *blk);
+void touch(CacheBlk *blk) override;

 /**
  * Reset replacement data for a block. Used when a block is inserted.
@@ -70,7 +70,7 @@
  *
  * @param blk Cache block to be reset.
  */
-void reset(CacheBlk *blk);
+void reset(CacheBlk *blk) override;

 /**
  * Find replacement victim using access timestamps.

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81
Gerrit-Change-Number: 9321
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: ruby: Make sure addresses print in hex

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8941 )


Change subject: ruby: Make sure addresses print in hex
..

ruby: Make sure addresses print in hex

Added fix in the invalid transition panic and various places in ruby
random tester.

Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8941
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/cpu/testers/rubytest/Check.cc
M src/mem/slicc/symbols/StateMachine.py
2 files changed, 9 insertions(+), 9 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/src/cpu/testers/rubytest/Check.cc  
b/src/cpu/testers/rubytest/Check.cc

index e68196c..2ce79e7 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -209,7 +209,7 @@
 DPRINTF(RubyTest, "status before action update: %s\n",
 (TesterStatus_to_string(m_status)).c_str());
 m_status = TesterStatus_Action_Pending;
-DPRINTF(RubyTest, "Check %s, State=Action_Pending\n", m_address);
+DPRINTF(RubyTest, "Check %#x, State=Action_Pending\n", m_address);
 } else {
 // If the packet did not issue, must delete
 // Note: No need to delete the data, the packet destructor
@@ -263,7 +263,7 @@
 DPRINTF(RubyTest, "status before check update: %s\n",
 TesterStatus_to_string(m_status).c_str());
 m_status = TesterStatus_Check_Pending;
-DPRINTF(RubyTest, "Check %s, State=Check_Pending\n", m_address);
+DPRINTF(RubyTest, "Check %#x, State=Check_Pending\n", m_address);
 } else {
 // If the packet did not issue, must delete
 // Note: No need to delete the data, the packet destructor
@@ -301,10 +301,10 @@
 m_store_count++;
 if (m_store_count == CHECK_SIZE) {
 m_status = TesterStatus_Ready;
-DPRINTF(RubyTest, "Check %s, State=Ready\n", m_address);
+DPRINTF(RubyTest, "Check %#x, State=Ready\n", m_address);
 } else {
 m_status = TesterStatus_Idle;
-DPRINTF(RubyTest, "Check %s, State=Idle store_count: %d\n",
+DPRINTF(RubyTest, "Check %#x, State=Idle store_count: %d\n",
 m_address, m_store_count);
 }
 DPRINTF(RubyTest, "Action callback return data now %d\n",
@@ -314,7 +314,7 @@
 // Perform load/check
 for (int byte_number=0; byte_number<CHECK_SIZE; byte_number++) {
 if (uint8_t(m_value + byte_number) !=  
data->getByte(byte_number)) {
-panic("Action/check failure: proc: %d address: %s  
data: %s "
+panic("Action/check failure: proc: %d address: %#x  
data: %s "

   "byte_number: %d m_value+byte_number: %d byte: %d %s"
   "Time: %d\n",
   proc, address, data, byte_number,
@@ -329,7 +329,7 @@
 m_tester_ptr->incrementCheckCompletions();

 m_status = TesterStatus_Idle;
-DPRINTF(RubyTest, "Check %s, State=Idle\n", m_address);
+DPRINTF(RubyTest, "Check %#x, State=Idle\n", m_address);
 pickValue();

 } else {
@@ -349,7 +349,7 @@
 assert(m_status == TesterStatus_Idle || m_status ==  
TesterStatus_Ready);

 m_status = TesterStatus_Idle;
 m_address = address;
-DPRINTF(RubyTest, "Check %s, State=Idle\n", m_address);
+DPRINTF(RubyTest, "Check %#x, State=Idle\n", m_address);
 m_store_count = 0;
 }

@@ -367,7 +367,7 @@
 assert(m_status == TesterStatus_Idle || m_status ==  
TesterStatus_Ready);

 m_status = TesterStatus_Idle;
 m_initiatingNode = (random_mt.random(0, m_num_writers - 1));
-DPRINTF(RubyTest, "Check %s, State=Idle, picked initiating node %d\n",
+DPRINTF(RubyTest, "Check %#x, State=Idle, picked initiating node %d\n",
 m_address, m_initiatingNode);
 m_store_count = 0;
 }
diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 3f4e43a..e63f6fc 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1400,7 +1400,7 @@
 code('''
   default:
 panic("Invalid transition\\n"
-  "%s time: %d addr: %s event: %s state: %s\\n",
+  "%s time: %d addr: %#x event: %s state: %s\\n",
   name(), curCycle(), addr, event, state);
 }


--
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[gem5-dev] Change in public/gem5[master]: mem-cache: fix missing overrides in repl policies

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/9321



Change subject: mem-cache: fix missing overrides in repl policies
..

mem-cache: fix missing overrides in repl policies

Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/mem/cache/replacement_policies/lru_rp.hh
M src/mem/cache/replacement_policies/mru_rp.hh
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/mem/cache/replacement_policies/lru_rp.hh  
b/src/mem/cache/replacement_policies/lru_rp.hh

index 3e5efe6..2dd7e86 100644
--- a/src/mem/cache/replacement_policies/lru_rp.hh
+++ b/src/mem/cache/replacement_policies/lru_rp.hh
@@ -62,7 +62,7 @@
  *
  * @param blk Cache block to be touched.
  */
-void touch(CacheBlk *blk);
+void touch(CacheBlk *blk) override;

 /**
  * Reset replacement data for a block. Used when a block is inserted.
@@ -70,7 +70,7 @@
  *
  * @param blk Cache block to be reset.
  */
-void reset(CacheBlk *blk);
+void reset(CacheBlk *blk) override;

 /**
  * Find replacement victim using LRU timestamps.
diff --git a/src/mem/cache/replacement_policies/mru_rp.hh  
b/src/mem/cache/replacement_policies/mru_rp.hh

index d947d7c..fd9a29d 100644
--- a/src/mem/cache/replacement_policies/mru_rp.hh
+++ b/src/mem/cache/replacement_policies/mru_rp.hh
@@ -62,7 +62,7 @@
  *
  * @param blk Cache block to be touched.
  */
-void touch(CacheBlk *blk);
+void touch(CacheBlk *blk) override;

 /**
  * Reset replacement data for a block. Used when a block is inserted.
@@ -70,7 +70,7 @@
  *
  * @param blk Cache block to be reset.
  */
-void reset(CacheBlk *blk);
+void reset(CacheBlk *blk) override;

 /**
  * Find replacement victim using access timestamps.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81
Gerrit-Change-Number: 9321
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-MessageType: newchange
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[gem5-dev] Change in public/gem5[master]: learning_gem5: Add a simple Ruby protocol

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8942 )


Change subject: learning_gem5: Add a simple Ruby protocol
..

learning_gem5: Add a simple Ruby protocol

Adds the MSI protocol from "A Primer on Memory Consistency and Cache
Coherence" by Daniel J. Sorin, Mark D. Hill, and David A. Wood.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

This is meant to be a simple, clean, example of how to make a Ruby
protocol.
Currently, it only works in SE mode.

The next changeset will contain the required configuration files.

Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8942
---
A src/learning_gem5/part3/MSI-cache.sm
A src/learning_gem5/part3/MSI-dir.sm
A src/learning_gem5/part3/MSI-msg.sm
A src/learning_gem5/part3/MSI.slicc
A src/learning_gem5/part3/SConsopts
5 files changed, 1,525 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/learning_gem5/part3/MSI-cache.sm  
b/src/learning_gem5/part3/MSI-cache.sm

new file mode 100644
index 000..3847b53
--- /dev/null
+++ b/src/learning_gem5/part3/MSI-cache.sm
@@ -0,0 +1,853 @@
+/*
+ * Copyright (c) 2017 Jason Lowe-Power
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This file contains a simple example MSI protocol.
+ *
+ * The protocol in this file is based off of the MSI protocol found in
+ * A Primer on Memory Consistency and Cache Coherence
+ *  Daniel J. Sorin, Mark D. Hill, and David A. Wood
+ *  Synthesis Lectures on Computer Architecture 2011 6:3, 141-149
+ *
+ * Table 8.1 contains the transitions and actions found in this file and
+ * section 8.2.4 explains the protocol in detail.
+ *
+ * See Learning gem5 Part 3: Ruby for more details.
+ *
+ * Authors: Jason Lowe-Power
+ */
+
+/// Declare a machine with type L1Cache.
+machine(MachineType:L1Cache, "MSI cache")
+: Sequencer *sequencer; // Incoming request from CPU come from this
+  CacheMemory *cacheMemory; // This stores the data and cache states
+  bool send_evictions; // Needed to support O3 CPU and mwait
+
+  // Other declarations
+  // Message buffers are required to send and receive data from the  
Ruby

+  // network. The from/to and request/response can be confusing!
+  // Virtual networks are needed to prevent deadlock (e.g., it is bad  
if a
+  // response gets stuck behind a stalled request). In this protocol,  
we are

+  // using three virtual networks. The highest priority is responses,
+  // followed by forwarded requests, then requests have the lowest  
priority.

+
+  // Requests *to* the directory
+  MessageBuffer * requestToDir, network="To", virtual_network="0",
+vnet_type="request";
+  // Responses *to* the directory or other caches
+  MessageBuffer * responseToDirOrSibling, network="To",  
virtual_network="2",

+vnet_type="response";
+
+  // Requests *from* the directory for fwds, invs, and put acks.
+  MessageBuffer * forwardFromDir, network="From", virtual_network="1",
+vnet_type="forward";
+  // Res

[gem5-dev] Change in public/gem5[master]: learning_gem5: Add config files for MSI protocol

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8943 )


Change subject: learning_gem5: Add config files for MSI protocol
..

learning_gem5: Add config files for MSI protocol

Adds the required configuration files to run the MSI protocol. These
config files are much simpler than the current Ruby examples and follow
the pattern in the other Learning gem5 run scripts.

By default, this script runs with two CPUs and runs the recently added
thread test binary.

Currently, only SE mode is supported.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8943
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
A configs/learning_gem5/part3/msi_caches.py
A configs/learning_gem5/part3/simple_ruby.py
2 files changed, 354 insertions(+), 0 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/configs/learning_gem5/part3/msi_caches.py  
b/configs/learning_gem5/part3/msi_caches.py

new file mode 100644
index 000..7bd24ef
--- /dev/null
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -0,0 +1,253 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2017 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" This file creates a set of Ruby caches, the Ruby network, and a simple
+point-to-point topology.
+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+   also needs to be updated. For now, email Jason  
<ja...@lowepower.com>

+
+"""
+
+import math
+
+from m5.defines import buildEnv
+from m5.util import fatal, panic
+
+from m5.objects import *
+
+class MyCacheSystem(RubySystem):
+
+def __init__(self):
+if buildEnv['PROTOCOL'] != 'MSI':
+fatal("This system assumes MSI from learning gem5!")
+
+super(MyCacheSystem, self).__init__()
+
+def setup(self, system, cpus, mem_ctrls):
+"""Set up the Ruby cache subsystem. Note: This can't be done in the
+   constructor because many of these items require a pointer to the
+   ruby system (self). This causes infinite recursion in  
initialize()

+   if we do this in the __init__.
+"""
+# Ruby's global network.
+self.network = MyNetwork(self)
+
+# MSI uses 3 virtual networks. One for requests (lowest priority),  
one

+# for responses (highest priority), and one for "forwards" or
+# cache-to-cache requests. See *.sm files for details.
+self.number_of_virtual_networks = 3
+self.network.number_of_virtual_networks = 3
+
+# There is a single global list of all of the controllers to make  
it

+# easier to connect everything to the global network. This can be
+# customized depending on the topology/network requirements.
+# Create one controller for each L1 cache (and the cache mem obj.)
+# Create a single directory controller (Really the memory cntrl)
+self.controllers = \
+[L1Cache(system, self, cpu) for cpu in cpus] + \
+  

[gem5-dev] Change in public/gem5[master]: learning_gem5: Ruby random tester files for MSI

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8944 )


Change subject: learning_gem5: Ruby random tester files for MSI
..

learning_gem5: Ruby random tester files for MSI

Adds a pair of scripts to run the Ruby random tester with the MSI protocol.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I15550a36618546f0354163b0216cf771f434ed84
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8944
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
A configs/learning_gem5/part3/ruby_test.py
A configs/learning_gem5/part3/test_caches.py
2 files changed, 195 insertions(+), 0 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/configs/learning_gem5/part3/ruby_test.py  
b/configs/learning_gem5/part3/ruby_test.py

new file mode 100644
index 000..692a87e
--- /dev/null
+++ b/configs/learning_gem5/part3/ruby_test.py
@@ -0,0 +1,84 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+""" This file creates a system with Ruby caches and runs the ruby random  
tester

+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+   also needs to be updated. For now, email Jason  
<ja...@lowepower.com>

+
+"""
+from __future__ import print_function
+
+# import the m5 (gem5) library created when gem5 is built
+import m5
+# import all of the SimObjects
+from m5.objects import *
+
+from test_caches import TestCacheSystem
+
+# create the system we are going to simulate
+system = System()
+
+# Set the clock fequency of the system (and all of its children)
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = '1GHz'
+system.clk_domain.voltage_domain = VoltageDomain()
+
+# Set up the system
+system.mem_mode = 'timing'   # Use timing accesses
+system.mem_ranges = [AddrRange('512MB')] # Create an address range
+
+# Create the tester
+system.tester = RubyTester(checks_to_complete = 100,
+   wakeup_frequency = 10,
+   num_cpus = 2)
+
+# Create a DDR3 memory controller and connect it to the membus
+system.mem_ctrl = DDR3_1600_8x8()
+system.mem_ctrl.range = system.mem_ranges[0]
+
+# Create the Ruby System
+system.caches = TestCacheSystem()
+system.caches.setup(system, system.tester, [system.mem_ctrl])
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = False, system = system)
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
+
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print('Exiting @ tick {} because {}'.format(
+ m5.curTick(), exit_event.getCause())
+ )
diff --git a/configs/learning_gem5/part3/test_caches.py  
b/configs/learning_gem5/part3/test_caches.py

new file mode 100644
index 000..3721f4a
--- /dev/null
+++ b/configs/learning_gem5/part3/test_caches.py
@@ -0,0 +1,111 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2017 Jason Power
+# All rights reserved.
+#
+# Redistribution

[gem5-dev] Change in public/gem5[master]: learning_gem5: Add a simple config for MI_example

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8945 )


Change subject: learning_gem5: Add a simple config for MI_example
..

learning_gem5: Add a simple config for MI_example

Adds a new config script to configure the MI_example protocol. This script
closely follows the script used for MSI, but instead supports the
MI_example protocol. This script works with the simple_ruby runscript and
can be included instead of msi_caches.

Change-Id: I8be0be67bf51369763ba103a5f101cfc01ad8859
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8945
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
---
A configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/simple_ruby.py
2 files changed, 241 insertions(+), 0 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py  
b/configs/learning_gem5/part3/ruby_caches_MI_example.py

new file mode 100644
index 000..104f0df
--- /dev/null
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -0,0 +1,239 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" This file creates a set of Ruby caches, the Ruby network, and a simple
+point-to-point topology.
+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+You can change simple_ruby to import from this file instead of from  
msi_caches

+to use the MI_example protocol instead of MSI.
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+   also needs to be updated. For now, email Jason  
<ja...@lowepower.com>

+
+"""
+
+import math
+
+from m5.defines import buildEnv
+from m5.util import fatal, panic
+
+from m5.objects import *
+
+class MyCacheSystem(RubySystem):
+
+def __init__(self):
+if buildEnv['PROTOCOL'] != 'MI_example':
+fatal("This system assumes MI_example!")
+
+super(MyCacheSystem, self).__init__()
+
+def setup(self, system, cpus, mem_ctrls):
+"""Set up the Ruby cache subsystem. Note: This can't be done in the
+   constructor because many of these items require a pointer to the
+   ruby system (self). This causes infinite recursion in  
initialize()

+   if we do this in the __init__.
+"""
+# Ruby's global network.
+self.network = MyNetwork(self)
+
+# MI example uses 5 virtual networks
+self.number_of_virtual_networks = 5
+self.network.number_of_virtual_networks = 5
+
+# There is a single global list of all of the controllers to make  
it

+# easier to connect everything to the global network. This can be
+# customized depending on the topology/network requirements.
+# Create one controller for each L1 cache (and the cache mem obj.)
+# Create a single directory controller (Really the memory cntrl)
+self.controllers = \
+[L1Cache(system, self, cpu) for cpu in cpus] + \
+[DirController(self, system.mem_ranges, mem_ctrls)]
+
+# Create one sequencer per CPU. In many systems this is more
+# complicate

[gem5-dev] Change in public/gem5[master]: learning_gem5: Add a simple Ruby protocol

[Jason Lowe-Power (Gerrit)]

Hello Nikos Nikoleris, Bradford Beckmann, Sooraj Puthoor,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8942

to look at the new patch set (#5).

Change subject: learning_gem5: Add a simple Ruby protocol
..

learning_gem5: Add a simple Ruby protocol

Adds the MSI protocol from "A Primer on Memory Consistency and Cache
Coherence" by Daniel J. Sorin, Mark D. Hill, and David A. Wood.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

This is meant to be a simple, clean, example of how to make a Ruby
protocol.
Currently, it only works in SE mode.

The next changeset will contain the required configuration files.

Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A src/learning_gem5/part3/MSI-cache.sm
A src/learning_gem5/part3/MSI-dir.sm
A src/learning_gem5/part3/MSI-msg.sm
A src/learning_gem5/part3/MSI.slicc
A src/learning_gem5/part3/SConsopts
5 files changed, 1,525 insertions(+), 0 deletions(-)


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Gerrit-Change-Number: 8942
Gerrit-PatchSet: 5
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Bradford Beckmann <brad.beckm...@amd.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
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Re: [gem5-dev] Help with X86 ISA (RDTSC/RDTSCP) to read the correct clock cycles

[Jason Lowe-Power]

Hi Li,

This patch (https://gem5-review.googlesource.com/c/public/gem5/+/9042/
) and a few
after it should solve the problem.

Interestingly, the reason I found this issue was for exactly the same
reason that you did. I was trying to run the spectre code. I got it
"working" perfectly in gem5. Here's a couple of pointers:

1) Make sure to use the O3 CPU
2) If your branch predictor is better, it's more likely to be vulnerable to
spectre. Using TAGE makes it happen much faster than the default Tournament
predictor.
3) Make sure to compile spectre *without* -O3. GCC's optimizations make is
less likely to happen. Also, older GCCs seem to work "better" as well.

Finally, I have a tag in my gem5 repo for which all of the code is already
set up. See https://github.com/jlpresearch/gem5/tree/spectre-test. Some
documentation here:
https://github.com/jlpresearch/gem5/blob/spectre-test/spectre.rst

Now that I've written this, I realize I should write up a blog post. I'll
do that soon.

One last note: The code above will accomplish what you want, but you should
make sure to fully understand everything that's going on and *why*.

Cheers,
Jason


On Thu, Mar 22, 2018 at 12:01 PM Li Zhou  wrote:

> Hi all (specifically Gabe and Jason),
>
>
> I'm trying to use gem5 to reproduce the results of Spectre code (
> https://github.com/crozone/SpectrePoC) in FS mode. It uses RDTSC/RDTSCP to
> measure the timing of a load operation. I have exactly the same issue with
> one previous post, the gem5 simply returns a fixed number for all the
> loads.
>
>
> I noticed that two patches were recently updated which implemented
> serialized RDTSC and RDTSCP (I assume RDTSCP wouldn't work correctly since
> the behavior of TSC_AUX hasn't been well defined, but RDTSC should work?).
> However, in my experiments, it still returns a fixed number for all loads
> for both RDTSC and RDTSCP. I also tried Jason's method, added a flag in
> decoder-ns.cc.inc and it didn't work (I may do it wrong. What I did was add
> the line of code/recompile/run with a script).
>
> I would like to know if I want RDTSC or RDTSCP work as expected what
> changes should I make to the gem5 code? Before I found the related post,
> I'm thinking to replace RDTSC/RDTSCP with curTick() inside the testing
> code,
> but also I didn't figure out how to do this and not sure if this would
> work. I'm new to gem5 so sorry if some questions don't make sense.
>
> -Li
>
> I newly joined the mailing list, so was not able to reply to the previous
> posts.
>
> FYI. The related post is:
> https://www.mail-archive.com/gem5-dev@gem5.org/msg24602.html
>
> The related patches are:
> https://www.mail-archive.com/gem5-dev@gem5.org/msg24671.html
> https://www.mail-archive.com/gem5-dev@gem5.org/msg24670.html
> https://www.mail-archive.com/gem5-dev@gem5.org/msg24668.html
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[gem5-dev] Learning gem5 Ruby protocol

[Jason Lowe-Power]

Hi all,

I would like to push the new Ruby protocol I wrote into the mainline before
my tutorial on Saturday (so, tomorrow). Let me know if you see any issues
before tomorrow, otherwise, I'm going to push as is. If there are any
problems, I'll hold off.

This shouldn't affect anything outside of Learning gem5.

The reviews so far (thanks Nikos and Sooraj!):
https://gem5-review.googlesource.com/c/public/gem5/+/8942
https://gem5-review.googlesource.com/c/public/gem5/+/8943/
https://gem5-review.googlesource.com/c/public/gem5/+/8944/
https://gem5-review.googlesource.com/c/public/gem5/+/8945/

Thanks!
Jason
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[gem5-dev] Change in public/gem5[master]: learning_gem5: Add a simple Ruby protocol

[Jason Lowe-Power (Gerrit)]

Hello Nikos Nikoleris, Bradford Beckmann, Sooraj Puthoor,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8942

to look at the new patch set (#4).

Change subject: learning_gem5: Add a simple Ruby protocol
..

learning_gem5: Add a simple Ruby protocol

Adds the MSI protocol from "A Primer on Memory Consistency and Cache
Coherence" by Daniel J. Sorin, Mark D. Hill, and David A. Wood.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

This is meant to be a simple, clean, example of how to make a Ruby
protocol.
Currently, it only works in SE mode.

The next changeset will contain the required configuration files.

Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A src/learning_gem5/part3/MSI-cache.sm
A src/learning_gem5/part3/MSI-dir.sm
A src/learning_gem5/part3/MSI-msg.sm
A src/learning_gem5/part3/MSI.slicc
A src/learning_gem5/part3/SConsopts
5 files changed, 1,525 insertions(+), 0 deletions(-)


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Gerrit-Change-Number: 8942
Gerrit-PatchSet: 4
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Bradford Beckmann <brad.beckm...@amd.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
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[gem5-dev] Change in public/gem5[master]: learning_gem5: Add config files for MSI protocol

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#4). (  
https://gem5-review.googlesource.com/8943 )


Change subject: learning_gem5: Add config files for MSI protocol
..

learning_gem5: Add config files for MSI protocol

Adds the required configuration files to run the MSI protocol. These
config files are much simpler than the current Ruby examples and follow
the pattern in the other Learning gem5 run scripts.

By default, this script runs with two CPUs and runs the recently added
thread test binary.

Currently, only SE mode is supported.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A configs/learning_gem5/part3/msi_caches.py
A configs/learning_gem5/part3/simple_ruby.py
2 files changed, 354 insertions(+), 0 deletions(-)


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[gem5-dev] Change in public/gem5[master]: learning_gem5: Add a simple Ruby protocol

[Jason Lowe-Power (Gerrit)]

Hello Nikos Nikoleris, Bradford Beckmann,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8942

to look at the new patch set (#3).

Change subject: learning_gem5: Add a simple Ruby protocol
..

learning_gem5: Add a simple Ruby protocol

Adds the MSI protocol from "A Primer on Memory Consistency and Cache
Coherence" by Daniel J. Sorin, Mark D. Hill, and David A. Wood.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

This is meant to be a simple, clean, example of how to make a Ruby
protocol.
Currently, it only works in SE mode.

The next changeset will contain the required configuration files.

Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A src/learning_gem5/part3/MSI-cache.sm
A src/learning_gem5/part3/MSI-dir.sm
A src/learning_gem5/part3/MSI-msg.sm
A src/learning_gem5/part3/MSI.slicc
A src/learning_gem5/part3/SConsopts
5 files changed, 1,518 insertions(+), 0 deletions(-)


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Gerrit-Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab
Gerrit-Change-Number: 8942
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Bradford Beckmann <brad.beckm...@amd.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-CC: Sooraj Puthoor <puthoorsoo...@gmail.com>
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[gem5-dev] Change in public/gem5[master]: arch-x86, sim-se: Bump kernel version to 3.2

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8903 )


Change subject: arch-x86,sim-se: Bump kernel version to 3.2
..

arch-x86,sim-se: Bump kernel version to 3.2

Current glibc expects at least kernel 3.2. Bump this so syscall emulation
with dynamically-linked binaries works.

Change-Id: I07077ed2de14c308f6ff79cae677915612557332
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8903
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Brandon Potter <brandon.pot...@amd.com>
---
M src/arch/x86/linux/process.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Brandon Potter: Looks good to me, approved



diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index 4591cf9..b3e9586 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -62,7 +62,7 @@

 strcpy(name->sysname, "Linux");
 strcpy(name->nodename, "sim.gem5.org");
-strcpy(name->release, "3.0.0");
+strcpy(name->release, "3.2.0");
 strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
 strcpy(name->machine, "x86_64");


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Gerrit-Change-Number: 8903
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: arch-x86, sim-se: Enable prlimit syscall

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8921 )


Change subject: arch-x86,sim-se: Enable prlimit syscall
..

arch-x86,sim-se: Enable prlimit syscall

Change-Id: I15f0e5ddb72578de90ed68866c8a0c1501717d61
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8921
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Gabe Black <gabebl...@google.com>
Maintainer: Brandon Potter <brandon.pot...@amd.com>
---
M src/arch/x86/linux/process.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  Brandon Potter: Looks good to me, approved



diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index b3e9586..1bde67e 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -522,7 +522,7 @@
 /* 299 */ SyscallDesc("recvmmsg", unimplementedFunc),
 /* 300 */ SyscallDesc("fanotify_init", unimplementedFunc),
 /* 301 */ SyscallDesc("fanotify_mark", unimplementedFunc),
-/* 302 */ SyscallDesc("prlimit64", unimplementedFunc),
+/* 302 */ SyscallDesc("prlimit64", prlimitFunc),
 /* 303 */ SyscallDesc("name_to_handle_at", unimplementedFunc),
 /* 304 */ SyscallDesc("open_by_handle_at", unimplementedFunc),
 /* 305 */ SyscallDesc("clock_adjtime", unimplementedFunc),

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Gerrit-Change-Number: 8921
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: sim-se: Add /sys/devices/system/cpu/online file

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8902 )


Change subject: sim-se: Add /sys/devices/system/cpu/online file
..

sim-se: Add /sys/devices/system/cpu/online file

Add the special file /sys/devices/system/cpu/online to the files that gem5
knows how to handle in SE mode. This file lists the CPUs that are active.
For instance, in an 8 CPU system it is the following:
0-7

This implementation simply returns a file that is 0-%d where %d is the
current number of thread contexts.

This file is required for C++11 threads with gcc 4.8 and above.

Change-Id: I0b566f77e75e9eca480509814d0fd038a231b940
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8902
Reviewed-by: Gabe Black <gabebl...@google.com>
Reviewed-by: Brandon Potter <brandon.pot...@amd.com>
Maintainer: Brandon Potter <brandon.pot...@amd.com>
---
M src/kern/linux/linux.cc
M src/kern/linux/linux.hh
2 files changed, 11 insertions(+), 0 deletions(-)

Approvals:
  Brandon Potter: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve



diff --git a/src/kern/linux/linux.cc b/src/kern/linux/linux.cc
index bd0b4d0..d571b81 100644
--- a/src/kern/linux/linux.cc
+++ b/src/kern/linux/linux.cc
@@ -55,6 +55,9 @@
 } else if (path.compare(0, 11, "/etc/passwd") == 0) {
 data = Linux::etcPasswd(process, tc);
 matched = true;
+} else if (path.compare(0, 30, "/sys/devices/system/cpu/online") == 0)  
{

+data = Linux::cpuOnline(process, tc);
+matched = true;
 }

 if (matched) {
@@ -87,3 +90,10 @@
 return csprintf("gem5-user:x:1000:1000:gem5-user,,,:%s:/bin/bash\n",
 process->getcwd());
 }
+
+std::string
+Linux::cpuOnline(Process *process, ThreadContext *tc)
+{
+return csprintf("0-%d\n",
+tc->getSystemPtr()->numContexts() - 1);
+}
diff --git a/src/kern/linux/linux.hh b/src/kern/linux/linux.hh
index b24ee38..a1df994 100644
--- a/src/kern/linux/linux.hh
+++ b/src/kern/linux/linux.hh
@@ -227,6 +227,7 @@
ThreadContext *tc);
 static std::string procMeminfo(Process *process, ThreadContext *tc);
 static std::string etcPasswd(Process *process, ThreadContext *tc);
+static std::string cpuOnline(Process *process, ThreadContext *tc);

 // For futex system call
 static const unsigned TGT_FUTEX_WAIT  = 0;

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[gem5-dev] Change in public/gem5[master]: sim-se: Fix fallthrough in prlimit

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8904 )


Change subject: sim-se: Fix fallthrough in prlimit
..

sim-se: Fix fallthrough in prlimit

Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8904
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Brandon Potter <brandon.pot...@amd.com>
---
M src/sim/syscall_emul.hh
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Brandon Potter: Looks good to me, approved



diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index eaa5e54..e5b0f45 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1731,6 +1731,7 @@
 rlp->rlim_cur = rlp->rlim_max = 256*1024*1024;
 rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
 rlp->rlim_max = TheISA::htog(rlp->rlim_max);
+break;
   default:
 warn("prlimit: unimplemented resource %d", resource);
 return -EINVAL;

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Gerrit-Branch: master
Gerrit-Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7
Gerrit-Change-Number: 8904
Gerrit-PatchSet: 3
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-MessageType: merged
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[gem5-dev] Change in public/gem5[master]: tests: Add test program for C++ threads

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8901 )


Change subject: tests: Add test program for C++ threads
..

tests: Add test program for C++ threads

Simple program that spawns threads equal to the number of CPU cores and
has some false sharing for testing coherence protocols.

Change-Id: I5be907fd6fea9a8b8e80b63785d186619be41354
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8901
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
---
A tests/test-progs/threads/bin/x86/linux/threads
A tests/test-progs/threads/src/Makefile
A tests/test-progs/threads/src/threads.cpp
3 files changed, 123 insertions(+), 0 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/tests/test-progs/threads/bin/x86/linux/threads  
b/tests/test-progs/threads/bin/x86/linux/threads

new file mode 100755
index 000..8354fd6
--- /dev/null
+++ b/tests/test-progs/threads/bin/x86/linux/threads
Binary files differ
diff --git a/tests/test-progs/threads/src/Makefile  
b/tests/test-progs/threads/src/Makefile

new file mode 100644
index 000..e5abfd0
--- /dev/null
+++ b/tests/test-progs/threads/src/Makefile
@@ -0,0 +1,3 @@
+
+../bin/x86/linux/threads: threads.cpp
+   g++ -o ../bin/x86/linux/threads threads.cpp -pthread -std=c++11
diff --git a/tests/test-progs/threads/src/threads.cpp  
b/tests/test-progs/threads/src/threads.cpp

new file mode 100644
index 000..fccf9a5
--- /dev/null
+++ b/tests/test-progs/threads/src/threads.cpp
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2017 Jason Lowe-Power
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are
+* met: redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer;
+* redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution;
+* neither the name of the copyright holders nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* Authors: Jason Lowe-Power
+*/
+
+#include 
+#include 
+
+using namespace std;
+
+/*
+ * c = a + b
+ */
+void array_add(int *a, int *b, int *c, int tid, int threads, int  
num_values)

+{
+for (int i = tid; i < num_values; i += threads) {
+c[i] = a[i] + b[i];
+}
+}
+
+
+int main(int argc, char *argv[])
+{
+unsigned num_values;
+if (argc == 1) {
+num_values = 100;
+} else if (argc == 2) {
+num_values = atoi(argv[1]);
+if (num_values <= 0) {
+cerr << "Usage: " << argv[0] << " [num_values]" << endl;
+return 1;
+}
+} else {
+cerr << "Usage: " << argv[0] << " [num_values]" << endl;
+return 1;
+}
+
+unsigned cpus = thread::hardware_concurrency();
+
+cout << "Running on " << cpus << " cores. ";
+cout << "with " << num_values << " values" << endl;
+
+int *a, *b, *c;
+a = new int[num_values];
+b = new int[num_values];
+c = new int[num_values];
+
+if (!(a && b && c)) {
+cerr << "Allocation error!" << endl;
+return 2;
+}
+
+for (int i = 0; i < num_values; i++) {
+a[i] = i;
+b[i] = num_values - i;
+c[i] = 0;
+}
+
+thread **threads = new thread*[cpus];
+
+// NOTE: -1 is required for this to work in SE mode.
+for (int i = 0; i < cpus - 1; i++) {
+threads[i] = new thread(array_add, a, b, c, i, cpus, num_values);
+}
+// Execute the last thread with this thread conte

[gem5-dev] Change in public/gem5[master]: ruby: Make sure addresses print in hex

[Jason Lowe-Power (Gerrit)]

Hello Nikos Nikoleris, Bradford Beckmann,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/8941

to look at the new patch set (#2).

Change subject: ruby: Make sure addresses print in hex
..

ruby: Make sure addresses print in hex

Added fix in the invalid transition panic and various places in ruby
random tester.

Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/cpu/testers/rubytest/Check.cc
M src/mem/slicc/symbols/StateMachine.py
2 files changed, 9 insertions(+), 9 deletions(-)


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Gerrit-Change-Number: 8941
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Bradford Beckmann <brad.beckm...@amd.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
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[gem5-dev] Change in public/gem5[master]: learning_gem5: Update README for Learning gem5

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8946 )


Change subject: learning_gem5: Update README for Learning gem5
..

learning_gem5: Update README for Learning gem5

Change-Id: I94485e401bc77207cab68c1e24ef7a6ed83bd43d
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8946
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
---
M configs/learning_gem5/README
1 file changed, 10 insertions(+), 6 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/configs/learning_gem5/README b/configs/learning_gem5/README
index ae7d62a..64c479e 100644
--- a/configs/learning_gem5/README
+++ b/configs/learning_gem5/README
@@ -5,16 +5,21 @@
 book. The scripts contained in these directories are for educational  
purposes

 only and should not be used for architectural research as-is.

-"Learning gem5" is currently in early development stages. A pre-alpha  
working

-version of the book can be found at the following URL.
+"Learning gem5" is a work-in-progress book that is frequently updated. For  
the

+most up-to-date version of the book, see the website.

-http://lowepower.com/jason/learning_gem5/
+http://learning.gem5.org/book/

 This directory is broken into one subdirectory per part of the book.

+If you would like to contribute (please do!) the code for the Learning  
gem5 book

+is hosted on GitHub.
+
+https://github.com/powerjg/learning_gem5
+
 Goals of these scripts
 ~~
-These scripts are not necessarily useful outside the scope of the learning
+These scripts are not necessarily useful outside the scope of the Learning
 gem5 book. The goal is to include the learning gem5 scripts, following the
 book as closely as possible, so that the regression tester will catch any
 changes that affect the book.
@@ -25,5 +30,4 @@

 Feedback
 
-Send mail to power...@gmail.com to provide feedback.
-
+Send mail to ja...@lowepower.com to provide feedback.

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[gem5-dev] Change in public/gem5[master]: arch-x86: Implement rdtscp instruction

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8961



Change subject: arch-x86: Implement rdtscp instruction
..

arch-x86: Implement rdtscp instruction

This is essentially the same as rdtsc except it writes ecx, too.
This instruction should write the value of TSC_AUX to ecx, but this patch
simply puts 0 in ecx.

Change-Id: I03de94e1269dae4ebedd1bdba400c56f2c59acf9
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/system/msrs.py
2 files changed, 10 insertions(+), 1 deletion(-)



diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa

index aa60e4c..761e838 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -133,7 +133,7 @@
 0x7: decode MODRM_MOD {
 0x3: decode MODRM_RM {
 0x0: Inst::SWAPGS();
-0x1: rdtscp();
+0x1: Inst::RDTSCP();
 default: Inst::UD2();
 }
 default: Inst::INVLPG(M);
diff --git a/src/arch/x86/isa/insts/system/msrs.py  
b/src/arch/x86/isa/insts/system/msrs.py

index d0e2675..f540e8d 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -65,4 +65,13 @@
 srli t1, t1, 32, dataSize=8
 mov rdx, rdx, t1, dataSize=4
 };
+
+def macroop RDTSCP
+{
+rdtsc t1
+mov rax, rax, t1, dataSize=4
+srli t1, t1, 32, dataSize=8
+mov rdx, rdx, t1, dataSize=4
+xor rcx, rcx, rcx
+};
 '''

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Re: [gem5-dev] Help with x86 ISA language

[Jason Lowe-Power]

Thanks for the pointers, Gabe. I've posted a couple of patches on gerrit.
Let me know what you think.

Jason

On Thu, Mar 8, 2018 at 1:52 AM Gabe Black <gabebl...@google.com> wrote:

> Macroops don't execute, so setting serialization flags on them doesn't
> really make sense. It looks like the rdtsc microop is only used in the
> rdtsc instruction and I can't think of anywhere else it might be used, so
> you can probably change the flags on the microop fairly safely. The easiest
> way to do that is to change the flags that are implied with the TscOp
> operand is used in an "instruction" definition where instruction is in the
> ISA parser sense. In src/arch/x86/isa/operands.isa, you can see that TscOp
> is set up with a tuple returned by the controlReg function. The way the
> tuple is interpreted by the parser is described in some documentation
> somewhere, but basically each element is a list of flags that are set on
> the instruction object in various circumstances like if the operand is
> read, written, etc. You'd want to add flags that are implied when the TscOp
> (and only the TscOp) is read, in addition to the ones it already has when
> written.
>
> According to the AMD manuals I have (I think the AMD manuals are a lot
> easier to read), the RDTSCP instruction is basically the same as the RDTSC
> instruction, except that it also sets the ECX register to the value from
> the TSC_AUX MSR. That value could be the processor ID, or it could be
> anything else software wants. The value is put there by software and it's
> interpretation is entirely up to software, so there's no need to determine
> the processor ID from within the microcode. To fully support RDTSCP you'd
> need to probably define a TSC_AUX msr/control register in gem5 though, and
> teach the MSR accessing bits what it's ID is, etc.
>
> Gabe
>
> On Wed, Mar 7, 2018 at 1:52 PM, Jason Lowe-Power <ja...@lowepower.com>
> wrote:
>
> > Hi all (specifically Gabe),
> >
> > I was trying to run some tests that use the RDTSCP instruction and I
> found
> > that the rdtsc micro op's current implementation isn't quite serializing
> > enough. From the Intel manual:
> >
> > The RDTSCP instruction is not a serializing instruction, but it does wait
> > until all previous instructions have executed and all previous loads are
> > globally visible. But it does not wait for previous stores to be globally
> > visible, and subsequent instructions may begin execution before the read
> > operation is performed. The following items may guide software seeking to
> > order executions of RDTSCP:
> > • If software requires RDTSCP to be executed only after all previous
> stores
> > are globally visible, it can execute MFENCE immediately before RDTSCP.
> > • If software requires RDTSCP to be executed prior to execution of any
> > subsequent instruction (including any memory accesses), it can execute
> > LFENCE immediately after RDTSCP.
> >
> > This sounds like the microop should be "serializing before" in gem5's
> > parlance. I believe that the two instructions RDTSC and RDTSCP have the
> > same semantics, but that is not clearly stated in the instruction
> manual. I
> > don't see any reason not to implement them the same in gem5. Correct me
> if
> > I'm wrong.
> >
> > In testing, I found that making the macro-op serializing doesn't work
> > because it only serializes the final instruction and the TSC has already
> > been read. For instance if you have the following code sequence:
> >
> > rdtscp
> > load miss
> > rdtscp
> >
> > The difference in the two counters is ~load miss time on real hardware.
> In
> > gem5, the difference is ~4 cycles.
> >
> > I've found that this can be fixed by adding the following code to the
> RDTSC
> > micro-op implementation generated by the ISA description in
> > decode-ns.cc.inc.
> >
> > flags[IsSerializeBefore] = true;
> >
> > After this change, gem5 reports numbers closer to real hardware.
> >
> > I can't figure out the "right" way to get this code generated, though! I
> > assume I need to somehow change the rdstc micro-op definition in
> regop.isa.
> > Any help would be greatly appreciated!
> >
> > Other quick question: RDTSCP is supposed to return the CPU number along
> > with the TSC value. Any hints has to how to get this from the ISA
> language?
> > Would the best way be to add a new micro-op for this?
> >
> > Thanks,
> > Jason
> > ___
> > gem5-dev mailing list
> > gem5-dev@gem5.org
> > http://m5sim.org/mailman/listinfo/gem5-dev
> ___
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[gem5-dev] Change in public/gem5[master]: arch-x86: Serialize TSC reads

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8962



Change subject: arch-x86: Serialize TSC reads
..

arch-x86: Serialize TSC reads

When reading the timestamp counter (rdtsc and rdtscp) all previous
instructions should be committed. Make reading the TscOp serialize
Before to force this to be true.

Change-Id: If81e22c643b46cf7ac08f6f1b13f16d83ffcae63
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/arch/x86/isa/operands.isa
1 file changed, 4 insertions(+), 5 deletions(-)



diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index de7ee5a..c195995 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -67,11 +67,10 @@
 return ('FloatReg', 'df', idx, 'IsFloating', id)
 def ccReg(idx, id):
 return ('CCReg', 'uqw', idx, 'IsCC', id)
-def controlReg(idx, id, ctype = 'uqw'):
+def controlReg(idx, id, ctype = 'uqw', read_serial=False):
 return ('ControlReg', ctype, idx,
-(None, None, ['IsSerializeAfter',
-  'IsSerializing',
-  'IsNonSpeculative']),
+(None, ['IsSerializeBefore'] if read_serial else None,
+  
['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']),

 id)
 def squashCheckReg(idx, id, check, ctype = 'uqw'):
 return ('ControlReg', ctype, idx,
@@ -204,7 +203,7 @@
 'CSAttr':squashCReg('MISCREG_CS_ATTR', 209),
 'MiscRegDest':   controlReg('dest', 210),
 'MiscRegSrc1':   controlReg('src1', 211),
-'TscOp': controlReg('MISCREG_TSC', 212),
+'TscOp': controlReg('MISCREG_TSC', 212, read_serial=True),
 'M5Reg': squashCReg('MISCREG_M5_REG', 213),
 'Mem':   ('Mem', 'uqw', None, \
   ('IsMemRef', 'IsLoad', 'IsStore'), 300)

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[gem5-dev] Change in public/gem5[master]: learning_gem5: Add a simple config for MI_example

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8945



Change subject: learning_gem5: Add a simple config for MI_example
..

learning_gem5: Add a simple config for MI_example

Adds a new config script to configure the MI_example protocol. This script
closely follows the script used for MSI, but instead supports the
MI_example protocol. This script works with the simple_ruby runscript and
can be included instead of msi_caches.

Change-Id: I8be0be67bf51369763ba103a5f101cfc01ad8859
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/simple_ruby.py
2 files changed, 241 insertions(+), 0 deletions(-)



diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py  
b/configs/learning_gem5/part3/ruby_caches_MI_example.py

new file mode 100644
index 000..104f0df
--- /dev/null
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -0,0 +1,239 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" This file creates a set of Ruby caches, the Ruby network, and a simple
+point-to-point topology.
+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+You can change simple_ruby to import from this file instead of from  
msi_caches

+to use the MI_example protocol instead of MSI.
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+   also needs to be updated. For now, email Jason  
<ja...@lowepower.com>

+
+"""
+
+import math
+
+from m5.defines import buildEnv
+from m5.util import fatal, panic
+
+from m5.objects import *
+
+class MyCacheSystem(RubySystem):
+
+def __init__(self):
+if buildEnv['PROTOCOL'] != 'MI_example':
+fatal("This system assumes MI_example!")
+
+super(MyCacheSystem, self).__init__()
+
+def setup(self, system, cpus, mem_ctrls):
+"""Set up the Ruby cache subsystem. Note: This can't be done in the
+   constructor because many of these items require a pointer to the
+   ruby system (self). This causes infinite recursion in  
initialize()

+   if we do this in the __init__.
+"""
+# Ruby's global network.
+self.network = MyNetwork(self)
+
+# MI example uses 5 virtual networks
+self.number_of_virtual_networks = 5
+self.network.number_of_virtual_networks = 5
+
+# There is a single global list of all of the controllers to make  
it

+# easier to connect everything to the global network. This can be
+# customized depending on the topology/network requirements.
+# Create one controller for each L1 cache (and the cache mem obj.)
+# Create a single directory controller (Really the memory cntrl)
+self.controllers = \
+[L1Cache(system, self, cpu) for cpu in cpus] + \
+[DirController(self, system.mem_ranges, mem_ctrls)]
+
+# Create one sequencer per CPU. In many systems this is more
+# complicated since you have to create sequencers for DMA  
controllers

+# and other controllers, too.
+self.sequencers = [RubySequencer(version = i,
+# I/D cache is combined 

[gem5-dev] Change in public/gem5[master]: learning_gem5: Update README for Learning gem5

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8946



Change subject: learning_gem5: Update README for Learning gem5
..

learning_gem5: Update README for Learning gem5

Change-Id: I94485e401bc77207cab68c1e24ef7a6ed83bd43d
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M configs/learning_gem5/README
1 file changed, 10 insertions(+), 6 deletions(-)



diff --git a/configs/learning_gem5/README b/configs/learning_gem5/README
index ae7d62a..64c479e 100644
--- a/configs/learning_gem5/README
+++ b/configs/learning_gem5/README
@@ -5,16 +5,21 @@
 book. The scripts contained in these directories are for educational  
purposes

 only and should not be used for architectural research as-is.

-"Learning gem5" is currently in early development stages. A pre-alpha  
working

-version of the book can be found at the following URL.
+"Learning gem5" is a work-in-progress book that is frequently updated. For  
the

+most up-to-date version of the book, see the website.

-http://lowepower.com/jason/learning_gem5/
+http://learning.gem5.org/book/

 This directory is broken into one subdirectory per part of the book.

+If you would like to contribute (please do!) the code for the Learning  
gem5 book

+is hosted on GitHub.
+
+https://github.com/powerjg/learning_gem5
+
 Goals of these scripts
 ~~
-These scripts are not necessarily useful outside the scope of the learning
+These scripts are not necessarily useful outside the scope of the Learning
 gem5 book. The goal is to include the learning gem5 scripts, following the
 book as closely as possible, so that the regression tester will catch any
 changes that affect the book.
@@ -25,5 +30,4 @@

 Feedback
 
-Send mail to power...@gmail.com to provide feedback.
-
+Send mail to ja...@lowepower.com to provide feedback.

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[gem5-dev] Change in public/gem5[master]: learning_gem5: Add config files for MSI protocol

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8943



Change subject: learning_gem5: Add config files for MSI protocol
..

learning_gem5: Add config files for MSI protocol

Adds the required configuration files to run the MSI protocol. These
config files are much simpler than the current Ruby examples and follow
the pattern in the other Learning gem5 run scripts.

By default, this script runs with two CPUs and runs the recently added
thread test binary.

Currently, only SE mode is supported.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A configs/learning_gem5/part3/msi_caches.py
A configs/learning_gem5/part3/simple_ruby.py
2 files changed, 354 insertions(+), 0 deletions(-)



diff --git a/configs/learning_gem5/part3/msi_caches.py  
b/configs/learning_gem5/part3/msi_caches.py

new file mode 100644
index 000..8e961cb
--- /dev/null
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -0,0 +1,253 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2017 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Power
+
+""" This file creates a set of Ruby caches, the Ruby network, and a simple
+point-to-point topology.
+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+   also needs to be updated. For now, email Jason  
<ja...@lowepower.com>

+
+"""
+
+import math
+
+from m5.defines import buildEnv
+from m5.util import fatal, panic
+
+from m5.objects import *
+
+class MyCacheSystem(RubySystem):
+
+def __init__(self):
+if buildEnv['PROTOCOL'] != 'MSI':
+fatal("This system assumes MSI from learning gem5!")
+
+super(MyCacheSystem, self).__init__()
+
+def setup(self, system, cpus, mem_ctrls, num_testers=0):
+"""Set up the Ruby cache subsystem. Note: This can't be done in the
+   constructor because many of these items require a pointer to the
+   ruby system (self). This causes infinite recursion in  
initialize()

+   if we do this in the __init__.
+"""
+# Ruby's global network.
+self.network = MyNetwork(self)
+
+# MSI uses 3 virtual networks. One for requests (lowest priority),  
one

+# for responses (highest priority), and one for "forwards" or
+# cache-to-cache requests. See *.sm files for details.
+self.number_of_virtual_networks = 3
+self.network.number_of_virtual_networks = 3
+
+# There is a single global list of all of the controllers to make  
it

+# easier to connect everything to the global network. This can be
+# customized depending on the topology/network requirements.
+# Create one controller for each L1 cache (and the cache mem obj.)
+# Create a single directory controller (Really the memory cntrl)
+self.controllers = \
+[L1Cache(system, self, cpu) for cpu in cpus] + \
+[DirController(self, system.mem_ranges, mem_ctrls)]
+
+# Create one sequencer per CPU. In many systems this is more
+# complicated since you have to create sequencers for DMA  
con

[gem5-dev] Change in public/gem5[master]: learning_gem5: Add a simple Ruby protocol

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8942



Change subject: learning_gem5: Add a simple Ruby protocol
..

learning_gem5: Add a simple Ruby protocol

Adds the MSI protocol from "A Primer on Memory Consistency and Cache
Coherence" by Daniel J. Sorin, Mark D. Hill, and David A. Wood.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

This is meant to be a simple, clean, example of how to make a Ruby
protocol.
Currently, it only works in SE mode.

The next changeset will contain the required configuration files.

Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A src/learning_gem5/part3/MSI-cache.sm
A src/learning_gem5/part3/MSI-dir.sm
A src/learning_gem5/part3/MSI-msg.sm
A src/learning_gem5/part3/MSI.slicc
A src/learning_gem5/part3/SConsopts
5 files changed, 1,518 insertions(+), 0 deletions(-)



diff --git a/src/learning_gem5/part3/MSI-cache.sm  
b/src/learning_gem5/part3/MSI-cache.sm

new file mode 100644
index 000..b79c235
--- /dev/null
+++ b/src/learning_gem5/part3/MSI-cache.sm
@@ -0,0 +1,846 @@
+/*
+ * Copyright (c) 2017 Jason Lowe-Power
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This file contains a simple example MSI protocol.
+ *
+ * The protocol in this file is based off of the MSI protocol found in
+ * A Primer on Memory Consistency and Cache Coherence
+ *  Daniel J. Sorin, Mark D. Hill, and David A. Wood
+ *  Synthesis Lectures on Computer Architecture 2011 6:3, 141-149
+ *
+ * Table 8.1 contains the transitions and actions found in this file and
+ * section 8.2.4 explains the protocol in detail.
+ *
+ * See Learning gem5 Part 3: Ruby for more details.
+ *
+ * Authors: Jason Lowe-Power
+ */
+
+/// Declare a machine with type L1Cache.
+machine(MachineType:L1Cache, "MSI cache")
+: Sequencer *sequencer; // Incoming request from CPU come from this
+  CacheMemory *cacheMemory; // This stores the data and cache states
+  bool send_evictions; // Needed to support O3 CPU and mwait
+
+  // Other declarations
+  // Message buffers are required to send and receive data from the  
Ruby

+  // network. The from/to and request/response can be confusing!
+  // Virtual networks are needed to prevent deadlock (e.g., it is bad  
if a
+  // response gets stuck behind a stalled request). In this protocol,  
we are

+  // using three virtual networks. The highest priority is responses,
+  // followed by forwarded requests, then requests have the lowest  
priority.

+
+  // Requests *to* the directory
+  MessageBuffer * requestToDir, network="To", virtual_network="0",
+vnet_type="request";
+  // Responses *to* the directory or other caches
+  MessageBuffer * responseToDirOrSibling, network="To",  
virtual_network="2",

+vnet_type="response";
+
+  // Requests *from* the directory for fwds, invs, and put acks.
+  MessageBuffer * forwardFromDir, network="From", virtual_network="1",
+vnet_type="forward";
+  // Responses *from* directory and other caches for this cache's reqs.
+  MessageBuffer * responseFromDirOrSibling, network="From",
+virtual_net

[gem5-dev] Change in public/gem5[master]: learning_gem5: Ruby random tester files for MSI

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8944



Change subject: learning_gem5: Ruby random tester files for MSI
..

learning_gem5: Ruby random tester files for MSI

Adds a pair of scripts to run the Ruby random tester with the MSI protocol.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I15550a36618546f0354163b0216cf771f434ed84
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A configs/learning_gem5/part3/ruby_test.py
A configs/learning_gem5/part3/test_caches.py
2 files changed, 195 insertions(+), 0 deletions(-)



diff --git a/configs/learning_gem5/part3/ruby_test.py  
b/configs/learning_gem5/part3/ruby_test.py

new file mode 100644
index 000..300af89
--- /dev/null
+++ b/configs/learning_gem5/part3/ruby_test.py
@@ -0,0 +1,84 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Jason Lowe-Power
+
+""" This file creates a system with Ruby caches and runs the ruby random  
tester

+See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
+
+IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
+   also needs to be updated. For now, email Jason  
<ja...@lowepower.com>

+
+"""
+from __future__ import print_function
+
+# import the m5 (gem5) library created when gem5 is built
+import m5
+# import all of the SimObjects
+from m5.objects import *
+
+from test_caches import TestCacheSystem
+
+# create the system we are going to simulate
+system = System()
+
+# Set the clock fequency of the system (and all of its children)
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = '1GHz'
+system.clk_domain.voltage_domain = VoltageDomain()
+
+# Set up the system
+system.mem_mode = 'timing'   # Use timing accesses
+system.mem_ranges = [AddrRange('512MB')] # Create an address range
+
+# Create the tester
+system.tester = RubyTester(checks_to_complete = 100,
+   wakeup_frequency = 10,
+   num_cpus = 2)
+
+# Create a DDR3 memory controller and connect it to the membus
+system.mem_ctrl = DDR3_1600_8x8()
+system.mem_ctrl.range = system.mem_ranges[0]
+
+# # Create the Ruby System
+system.caches = TestCacheSystem()
+system.caches.setup(system, system.tester, [system.mem_ctrl])
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = False, system = system)
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')
+
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print('Exiting @ tick {} because {}'.format(
+ m5.curTick(), exit_event.getCause())
+ )
diff --git a/configs/learning_gem5/part3/test_caches.py  
b/configs/learning_gem5/part3/test_caches.py

new file mode 100644
index 000..3721f4a
--- /dev/null
+++ b/configs/learning_gem5/part3/test_caches.py
@@ -0,0 +1,111 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2017 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and th

[gem5-dev] Change in public/gem5[master]: ruby: Make sure addresses print in hex

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8941



Change subject: ruby: Make sure addresses print in hex
..

ruby: Make sure addresses print in hex

Added fix in the invalid transition panic and various places in ruby
random tester.

Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/cpu/testers/rubytest/Check.cc
M src/mem/slicc/symbols/StateMachine.py
2 files changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/cpu/testers/rubytest/Check.cc  
b/src/cpu/testers/rubytest/Check.cc

index e68196c..beeb4a5 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -209,7 +209,7 @@
 DPRINTF(RubyTest, "status before action update: %s\n",
 (TesterStatus_to_string(m_status)).c_str());
 m_status = TesterStatus_Action_Pending;
-DPRINTF(RubyTest, "Check %s, State=Action_Pending\n", m_address);
+DPRINTF(RubyTest, "Check %#x, State=Action_Pending\n", m_address);
 } else {
 // If the packet did not issue, must delete
 // Note: No need to delete the data, the packet destructor
@@ -263,7 +263,7 @@
 DPRINTF(RubyTest, "status before check update: %s\n",
 TesterStatus_to_string(m_status).c_str());
 m_status = TesterStatus_Check_Pending;
-DPRINTF(RubyTest, "Check %s, State=Check_Pending\n", m_address);
+DPRINTF(RubyTest, "Check %#x, State=Check_Pending\n", m_address);
 } else {
 // If the packet did not issue, must delete
 // Note: No need to delete the data, the packet destructor
@@ -301,10 +301,10 @@
 m_store_count++;
 if (m_store_count == CHECK_SIZE) {
 m_status = TesterStatus_Ready;
-DPRINTF(RubyTest, "Check %s, State=Ready\n", m_address);
+DPRINTF(RubyTest, "Check %#x, State=Ready\n", m_address);
 } else {
 m_status = TesterStatus_Idle;
-DPRINTF(RubyTest, "Check %s, State=Idle store_count: %d\n",
+DPRINTF(RubyTest, "Check %#x, State=Idle store_count: %d\n",
 m_address, m_store_count);
 }
 DPRINTF(RubyTest, "Action callback return data now %d\n",
@@ -314,7 +314,7 @@
 // Perform load/check
 for (int byte_number=0; byte_number<CHECK_SIZE; byte_number++) {
 if (uint8_t(m_value + byte_number) !=  
data->getByte(byte_number)) {
-panic("Action/check failure: proc: %d address: %s  
data: %s "
+panic("Action/check failure: proc: %d address: %#x  
data: %s "

   "byte_number: %d m_value+byte_number: %d byte: %d %s"
   "Time: %d\n",
   proc, address, data, byte_number,
diff --git a/src/mem/slicc/symbols/StateMachine.py  
b/src/mem/slicc/symbols/StateMachine.py

index 3f4e43a..e63f6fc 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1400,7 +1400,7 @@
 code('''
   default:
 panic("Invalid transition\\n"
-  "%s time: %d addr: %s event: %s state: %s\\n",
+  "%s time: %d addr: %#x event: %s state: %s\\n",
   name(), curCycle(), addr, event, state);
 }


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[gem5-dev] Change in public/gem5[master]: sim-se: Fix fallthrough in prlimit

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#2). (  
https://gem5-review.googlesource.com/8904 )


Change subject: sim-se: Fix fallthrough in prlimit
..

sim-se: Fix fallthrough in prlimit

Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/sim/syscall_emul.hh
1 file changed, 1 insertion(+), 0 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7
Gerrit-Change-Number: 8904
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerit-CC: Gabe Black <gabebl...@google.com>
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[gem5-dev] Change in public/gem5[master]: arch-x86, sim-se: Enable prlimit syscall

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8921



Change subject: arch-x86,sim-se: Enable prlimit syscall
..

arch-x86,sim-se: Enable prlimit syscall

Change-Id: I15f0e5ddb72578de90ed68866c8a0c1501717d61
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/arch/x86/linux/process.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index b3e9586..1bde67e 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -522,7 +522,7 @@
 /* 299 */ SyscallDesc("recvmmsg", unimplementedFunc),
 /* 300 */ SyscallDesc("fanotify_init", unimplementedFunc),
 /* 301 */ SyscallDesc("fanotify_mark", unimplementedFunc),
-/* 302 */ SyscallDesc("prlimit64", unimplementedFunc),
+/* 302 */ SyscallDesc("prlimit64", prlimitFunc),
 /* 303 */ SyscallDesc("name_to_handle_at", unimplementedFunc),
 /* 304 */ SyscallDesc("open_by_handle_at", unimplementedFunc),
 /* 305 */ SyscallDesc("clock_adjtime", unimplementedFunc),

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[gem5-dev] Change in public/gem5[master]: tests: Add test program for C++ threads

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8901



Change subject: tests: Add test program for C++ threads
..

tests: Add test program for C++ threads

Simple program that spawns threads equal to the number of CPU cores and
has some false sharing for testing coherence protocols.

Change-Id: I5be907fd6fea9a8b8e80b63785d186619be41354
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
A tests/test-progs/threads/bin/x86/linux/threads
A tests/test-progs/threads/src/Makefile
A tests/test-progs/threads/src/threads.cpp
3 files changed, 123 insertions(+), 0 deletions(-)



diff --git a/tests/test-progs/threads/bin/x86/linux/threads  
b/tests/test-progs/threads/bin/x86/linux/threads

new file mode 100755
index 000..8354fd6
--- /dev/null
+++ b/tests/test-progs/threads/bin/x86/linux/threads
Binary files differ
diff --git a/tests/test-progs/threads/src/Makefile  
b/tests/test-progs/threads/src/Makefile

new file mode 100644
index 000..e5abfd0
--- /dev/null
+++ b/tests/test-progs/threads/src/Makefile
@@ -0,0 +1,3 @@
+
+../bin/x86/linux/threads: threads.cpp
+   g++ -o ../bin/x86/linux/threads threads.cpp -pthread -std=c++11
diff --git a/tests/test-progs/threads/src/threads.cpp  
b/tests/test-progs/threads/src/threads.cpp

new file mode 100644
index 000..fccf9a5
--- /dev/null
+++ b/tests/test-progs/threads/src/threads.cpp
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2017 Jason Lowe-Power
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are
+* met: redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer;
+* redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution;
+* neither the name of the copyright holders nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* Authors: Jason Lowe-Power
+*/
+
+#include 
+#include 
+
+using namespace std;
+
+/*
+ * c = a + b
+ */
+void array_add(int *a, int *b, int *c, int tid, int threads, int  
num_values)

+{
+for (int i = tid; i < num_values; i += threads) {
+c[i] = a[i] + b[i];
+}
+}
+
+
+int main(int argc, char *argv[])
+{
+unsigned num_values;
+if (argc == 1) {
+num_values = 100;
+} else if (argc == 2) {
+num_values = atoi(argv[1]);
+if (num_values <= 0) {
+cerr << "Usage: " << argv[0] << " [num_values]" << endl;
+return 1;
+}
+} else {
+cerr << "Usage: " << argv[0] << " [num_values]" << endl;
+return 1;
+}
+
+unsigned cpus = thread::hardware_concurrency();
+
+cout << "Running on " << cpus << " cores. ";
+cout << "with " << num_values << " values" << endl;
+
+int *a, *b, *c;
+a = new int[num_values];
+b = new int[num_values];
+c = new int[num_values];
+
+if (!(a && b && c)) {
+cerr << "Allocation error!" << endl;
+return 2;
+}
+
+for (int i = 0; i < num_values; i++) {
+a[i] = i;
+b[i] = num_values - i;
+c[i] = 0;
+}
+
+thread **threads = new thread*[cpus];
+
+// NOTE: -1 is required for this to work in SE mode.
+for (int i = 0; i < cpus - 1; i++) {
+threads[i] = new thread(array_add, a, b, c, i, cpus, num_values);
+}
+// Execute the last thread with this thread context to appease SE mode
+array_add(a, b, c, cpus - 1, cpus, num_values);
+
+cout << "Waiting for other threads to complete" << endl;
+
+for (int i = 0; i < cpus - 1; i++) {
+thre

[gem5-dev] Change in public/gem5[master]: sim-se: Add /sys/devices/system/cpu/online file

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8902



Change subject: sim-se: Add /sys/devices/system/cpu/online file
..

sim-se: Add /sys/devices/system/cpu/online file

Add the special file /sys/devices/system/cpu/online to the files that gem5
knows how to handle in SE mode. This file lists the CPUs that are active.
For instance, in an 8 CPU system it is the following:
0-7

This implementation simply returns a file that is 0-%d where %d is the
current number of thread contexts.

This file is required for C++11 threads with gcc 4.8 and above.

Change-Id: I0b566f77e75e9eca480509814d0fd038a231b940
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/kern/linux/linux.cc
M src/kern/linux/linux.hh
2 files changed, 11 insertions(+), 0 deletions(-)



diff --git a/src/kern/linux/linux.cc b/src/kern/linux/linux.cc
index bd0b4d0..d571b81 100644
--- a/src/kern/linux/linux.cc
+++ b/src/kern/linux/linux.cc
@@ -55,6 +55,9 @@
 } else if (path.compare(0, 11, "/etc/passwd") == 0) {
 data = Linux::etcPasswd(process, tc);
 matched = true;
+} else if (path.compare(0, 30, "/sys/devices/system/cpu/online") == 0)  
{

+data = Linux::cpuOnline(process, tc);
+matched = true;
 }

 if (matched) {
@@ -87,3 +90,10 @@
 return csprintf("gem5-user:x:1000:1000:gem5-user,,,:%s:/bin/bash\n",
 process->getcwd());
 }
+
+std::string
+Linux::cpuOnline(Process *process, ThreadContext *tc)
+{
+return csprintf("0-%d\n",
+tc->getSystemPtr()->numContexts() - 1);
+}
diff --git a/src/kern/linux/linux.hh b/src/kern/linux/linux.hh
index b24ee38..a1df994 100644
--- a/src/kern/linux/linux.hh
+++ b/src/kern/linux/linux.hh
@@ -227,6 +227,7 @@
ThreadContext *tc);
 static std::string procMeminfo(Process *process, ThreadContext *tc);
 static std::string etcPasswd(Process *process, ThreadContext *tc);
+static std::string cpuOnline(Process *process, ThreadContext *tc);

 // For futex system call
 static const unsigned TGT_FUTEX_WAIT  = 0;

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Gerrit-Change-Number: 8902
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[gem5-dev] Change in public/gem5[master]: arch-x86, sim-se: Bump kernel version to 3.2

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8903



Change subject: arch-x86,sim-se: Bump kernel version to 3.2
..

arch-x86,sim-se: Bump kernel version to 3.2

Current glibc expects at least kernel 3.2. Bump this so syscall emulation
with dynamically-linked binaries works.

Change-Id: I07077ed2de14c308f6ff79cae677915612557332
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/arch/x86/linux/process.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index 4591cf9..b3e9586 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -62,7 +62,7 @@

 strcpy(name->sysname, "Linux");
 strcpy(name->nodename, "sim.gem5.org");
-strcpy(name->release, "3.0.0");
+strcpy(name->release, "3.2.0");
 strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
 strcpy(name->machine, "x86_64");


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Gerrit-Change-Id: I07077ed2de14c308f6ff79cae677915612557332
Gerrit-Change-Number: 8903
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Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: sim-se, arch-x86: Enable prlimit syscall

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8904



Change subject: sim-se,arch-x86: Enable prlimit syscall
..

sim-se,arch-x86: Enable prlimit syscall

I'm not sure why the prlimit syscall wasn't enabled before. This enables
it and fixes an implicit fallthrough warning since the function is now
compiled.

Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/arch/x86/linux/process.cc
M src/sim/syscall_emul.hh
2 files changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index b3e9586..1bde67e 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -522,7 +522,7 @@
 /* 299 */ SyscallDesc("recvmmsg", unimplementedFunc),
 /* 300 */ SyscallDesc("fanotify_init", unimplementedFunc),
 /* 301 */ SyscallDesc("fanotify_mark", unimplementedFunc),
-/* 302 */ SyscallDesc("prlimit64", unimplementedFunc),
+/* 302 */ SyscallDesc("prlimit64", prlimitFunc),
 /* 303 */ SyscallDesc("name_to_handle_at", unimplementedFunc),
 /* 304 */ SyscallDesc("open_by_handle_at", unimplementedFunc),
 /* 305 */ SyscallDesc("clock_adjtime", unimplementedFunc),
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index eaa5e54..e5b0f45 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1731,6 +1731,7 @@
 rlp->rlim_cur = rlp->rlim_max = 256*1024*1024;
 rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
 rlp->rlim_max = TheISA::htog(rlp->rlim_max);
+break;
   default:
 warn("prlimit: unimplemented resource %d", resource);
 return -EINVAL;

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[gem5-dev] Change in public/gem5[master]: mem-cache: Fix missing overrides

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/8861 )


Change subject: mem-cache: Fix missing overrides
..

mem-cache: Fix missing overrides

clang doesn't like inconsistent overrides. Add override to all overidden
functions in lru.hh

Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8861
Reviewed-by: Gabe Black <gabebl...@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikole...@arm.com>
---
M src/mem/cache/tags/lru.hh
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved



diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index 530b07a..1fbe4eb 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -69,9 +69,9 @@
  */
 ~LRU() {}

-CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles );
-CacheBlk* findVictim(Addr addr);
-void insertBlock(PacketPtr pkt, BlkType *blk);
+CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles ) override;
+CacheBlk* findVictim(Addr addr) override;
+void insertBlock(PacketPtr pkt, BlkType *blk) override;
 void invalidate(CacheBlk *blk) override;
 };


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d
Gerrit-Change-Number: 8861
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerit-CC: Daniel Carvalho <oda...@yahoo.com.br>
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[gem5-dev] Change in public/gem5[master]: mem-cache: Fix missing overrides

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/8861



Change subject: mem-cache: Fix missing overrides
..

mem-cache: Fix missing overrides

clang doesn't like inconsistent overrides. Add override to all overidden
functions in lru.hh

Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/mem/cache/tags/lru.hh
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index 530b07a..1fbe4eb 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -69,9 +69,9 @@
  */
 ~LRU() {}

-CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles );
-CacheBlk* findVictim(Addr addr);
-void insertBlock(PacketPtr pkt, BlkType *blk);
+CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles ) override;
+CacheBlk* findVictim(Addr addr) override;
+void insertBlock(PacketPtr pkt, BlkType *blk) override;
 void invalidate(CacheBlk *blk) override;
 };


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[gem5-dev] Help with x86 ISA language

[Jason Lowe-Power]

Hi all (specifically Gabe),

I was trying to run some tests that use the RDTSCP instruction and I found
that the rdtsc micro op's current implementation isn't quite serializing
enough. From the Intel manual:

The RDTSCP instruction is not a serializing instruction, but it does wait
until all previous instructions have executed and all previous loads are
globally visible. But it does not wait for previous stores to be globally
visible, and subsequent instructions may begin execution before the read
operation is performed. The following items may guide software seeking to
order executions of RDTSCP:
• If software requires RDTSCP to be executed only after all previous stores
are globally visible, it can execute MFENCE immediately before RDTSCP.
• If software requires RDTSCP to be executed prior to execution of any
subsequent instruction (including any memory accesses), it can execute
LFENCE immediately after RDTSCP.

This sounds like the microop should be "serializing before" in gem5's
parlance. I believe that the two instructions RDTSC and RDTSCP have the
same semantics, but that is not clearly stated in the instruction manual. I
don't see any reason not to implement them the same in gem5. Correct me if
I'm wrong.

In testing, I found that making the macro-op serializing doesn't work
because it only serializes the final instruction and the TSC has already
been read. For instance if you have the following code sequence:

rdtscp
load miss
rdtscp

The difference in the two counters is ~load miss time on real hardware. In
gem5, the difference is ~4 cycles.

I've found that this can be fixed by adding the following code to the RDTSC
micro-op implementation generated by the ISA description in
decode-ns.cc.inc.

flags[IsSerializeBefore] = true;

After this change, gem5 reports numbers closer to real hardware.

I can't figure out the "right" way to get this code generated, though! I
assume I need to somehow change the rdstc micro-op definition in regop.isa.
Any help would be greatly appreciated!

Other quick question: RDTSCP is supposed to return the CPU number along
with the TSC value. Any hints has to how to get this from the ISA language?
Would the best way be to add a new micro-op for this?

Thanks,
Jason
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[gem5-dev] Learning gem5 tutorial at ASPLOS

[Jason Lowe-Power]

Hi all,

As a reminder, the early registration deadline for ASPLOS is coming up soon
in two weeks (https://www.asplos2018.org/registration/#reg).

I have a couple of "gem5 best-practices" talks scheduled for the afternoon.
However, there are still more slots. *If you would like to give a short
presentation* (15-30 minutes) on how you use gem5, how to use a particular
gem5 component, or other things you've learned while using gem5 over the
years, *send me an email with a title and a short (few sentences) abstract*.

Original message included below.

Cheers,
Jason

On Fri, Jan 19, 2018 at 1:12 PM Jason Lowe-Power <ja...@lowepower.com>
wrote:

> Hi all,
>
> Apologies if you get more than one copy of this message.
>
> We are running another Learning gem5 tutorial at ASPLOS in Williamsburg VA
> this year. The tutorial is on Saturday March 24th. More information can be
> found in the tutorial website: http://learning.gem5.org/tutorial. Early
> registration for ASPLOS ends 2/23. See https://www.asplos2018.org/ for
> registration details.
>
> This year we'll be covering the basics of gem5, how to build memory system
> objects, and *new this yea*r we'll cover coherence protocols in Ruby and
> how CPU models are built. Finally,  we will have a session in the afternoon
> of gem5 best practices where we'll hear how gem5 experts use gem5.
>
> This is a great opportunity for junior computer architects to get exposure
> to one of the community's most popular tools. Instead of spending years
> trying to learn gem5 on your own, you can get a head start in just one day!
>
> If you have any questions,  feel free to email Jason Lowe-Power at
> ja...@lowepower.com.
>
> Hope to see you in Williamsburg!
>
> Jason
>
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[gem5-dev] Change in public/gem5[master]: dev: Fix i8042 device errors

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/7301 )


Change subject: dev: Fix i8042 device errors
..

dev: Fix i8042 device errors

The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2
for x86) incorrectly added breaks to the i8042 device without implementing
the correct functions. This patch implements keyboard writes, but ignores
output writes.

Information on the PS2 controller can be found at
https://wiki.osdev.org/%228042%22_PS/2_Controller

Note: Without this patch Linux 4.14 won't boot.

Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/7301
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Gabe Black <gabebl...@google.com>
---
M src/dev/x86/i8042.cc
1 file changed, 16 insertions(+), 3 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 279c520..c884f71 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -35,6 +35,11 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"

+/**
+ * Note: For details on the implementation see
+ * https://wiki.osdev.org/%228042%22_PS/2_Controller
+ */
+
 // The 8042 has a whopping 32 bytes of internal RAM.
 const uint8_t RamSize = 32;
 const uint8_t NumOutputBits = 14;
@@ -382,6 +387,17 @@
 "mouse output buffer\" command.\n", data);
 writeData(data, true);
 break;
+  case WriteKeyboardOutputBuff:
+DPRINTF(I8042, "Got data %#02x for \"Write "
+"keyboad output buffer\" command.\n", data);
+writeData(data, false);
+break;
+  case WriteOutputPort:
+DPRINTF(I8042, "Got data %#02x for \"Write "
+"output port\" command.\n", data);
+panic_if(bits(data, 0) != 1, "Reset bit should be 1");
+// Safe to ignore otherwise
+break;
   default:
 panic("Data written for unrecognized "
 "command %#02x\n", lastCommand);
@@ -453,12 +469,9 @@
   case ReadOutputPort:
 panic("i8042 \"Read output port\" command not implemented.\n");
   case WriteOutputPort:
-warn("i8042 \"Write output port\" command not implemented.\n");
 lastCommand = WriteOutputPort;
 break;
   case WriteKeyboardOutputBuff:
-warn("i8042 \"Write keyboard output buffer\" "
-"command not implemented.\n");
 lastCommand = WriteKeyboardOutputBuff;
 break;
   case WriteMouseOutputBuff:

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[gem5-dev] Change in public/gem5[master]: dev: Fix i8042 device errors

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/7301

to look at the new patch set (#6).

Change subject: dev: Fix i8042 device errors
..

dev: Fix i8042 device errors

The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2
for x86) incorrectly added breaks to the i8042 device without implementing
the correct functions. This patch implements keyboard writes, but ignores
output writes.

Information on the PS2 controller can be found at
https://wiki.osdev.org/%228042%22_PS/2_Controller

Note: Without this patch Linux 4.14 won't boot.

Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/dev/x86/i8042.cc
1 file changed, 16 insertions(+), 3 deletions(-)


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Gerrit-Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Gerrit-Change-Number: 7301
Gerrit-PatchSet: 6
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: dev: Fix i8042 device errors

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/7301

to look at the new patch set (#5).

Change subject: dev: Fix i8042 device errors
..

dev: Fix i8042 device errors

The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2
for x86) incorrectly added breaks to the i8042 device without implementing
the correct functions. This patchs "implements" keyboard and output write
by ignoring the writes.

Information on the PS2 controller can be found at
https://wiki.osdev.org/%228042%22_PS/2_Controller

Note: Without this patch Linux 4.14 won't boot.

Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/dev/x86/i8042.cc
1 file changed, 16 insertions(+), 3 deletions(-)


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[gem5-dev] Change in public/gem5[master]: dev: Fix wrong missing fallthrough

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/7301

to look at the new patch set (#4).

Change subject: dev: Fix wrong missing fallthrough
..

dev: Fix wrong missing fallthrough

The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2
for x86) incorrectly assumed these missing fallthroughs should have been
breaks. This implements the keyboard and mouse output buffers.

Information on the PS2 controller can be found at
https://wiki.osdev.org/%228042%22_PS/2_Controller

Note: Without this patch Linux 4.14 won't boot.

Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/dev/x86/i8042.cc
1 file changed, 16 insertions(+), 3 deletions(-)


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[gem5-dev] Change in public/gem5[master]: dev: Fix wrong missing fallthrough

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/7301

to look at the new patch set (#3).

Change subject: dev: Fix wrong missing fallthrough
..

dev: Fix wrong missing fallthrough

The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2
for x86) incorrectly assumed these missing fallthroughs should have been
breaks. This implements the keyboard and mouse output buffers.

Information on the PS2 controller can be found at
https://wiki.osdev.org/%228042%22_PS/2_Controller

Note: Without this patch Linux 4.14 won't boot.

Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/dev/x86/i8042.cc
1 file changed, 15 insertions(+), 3 deletions(-)


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Gerrit-Change-Number: 7301
Gerrit-PatchSet: 3
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[gem5-dev] Change in public/gem5[master]: arch-x86: Adding clflush, clflushopt, clwb instructions

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/7401 )


Change subject: arch-x86: Adding clflush, clflushopt, clwb instructions
..

arch-x86: Adding clflush, clflushopt, clwb instructions

This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.

Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Gabe Black <gabebl...@google.com>
---
M src/arch/x86/cpuid.cc
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
M src/arch/x86/isa/microops/ldstop.isa
4 files changed, 60 insertions(+), 4 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/x86/cpuid.cc b/src/arch/x86/cpuid.cc
index c78b720..867087e 100644
--- a/src/arch/x86/cpuid.cc
+++ b/src/arch/x86/cpuid.cc
@@ -37,6 +37,12 @@
 enum StandardCpuidFunction {
 VendorAndLargestStdFunc,
 FamilyModelStepping,
+CacheAndTLB,
+SerialNumber,
+CacheParams,
+MonitorMwait,
+ThermalPowerMgmt,
+ExtendedFeatures,
 NumStandardCpuidFuncs
 };

@@ -158,6 +164,10 @@
 result = CpuidResult(0x00020f51, 0x0805,
  0xe7dbfbff, 0x04000209);
 break;
+  case ExtendedFeatures:
+result = CpuidResult(0x, 0x0180,
+ 0x, 0x);
+break;
   default:
 warn("x86 cpuid family 0x: unimplemented function %u",
 funcNum);
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa

index f0698ce..aa60e4c 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -800,8 +800,16 @@
 0x3: Inst::STMXCSR(Md);
 0x4: xsave();
 0x5: xrstor();
-0x6: Inst::UD2();
-0x7: clflush();
+0x6: decode LEGACY_DECODEVAL {
+0x0: Inst::UD2();
+0x1: Inst::CLWB(Mb);
+default: Inst::UD2();
+}
+0x7: decode LEGACY_DECODEVAL {
+0x0: Inst::CLFLUSH(Mb);
+0x1: Inst::CLFLUSHOPT(Mb);
+default: Inst::CLFLUSH(Mb);
+}
 }
 }
 0x7: Inst::IMUL(Gv,Ev);
diff --git  
a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py  
b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py

index d42c687..4dc0b30 100644
--- a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
+++ b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
@@ -58,6 +58,41 @@
 ld t0, seg, riprel, disp, dataSize=1, prefetch=True
 };

+def macroop CLFLUSH_M
+{
+clflushopt t0, seg, sib, disp, dataSize=1
+mfence
+};
+
+def macroop CLFLUSH_P
+{
+rdip t7
+clflushopt t0, seg, riprel, disp, dataSize=1
+mfence
+};
+
+def macroop CLFLUSHOPT_M
+{
+clflushopt t0, seg, sib, disp, dataSize=1
+};
+
+def macroop CLFLUSHOPT_P
+{
+rdip t7
+clflushopt t0, seg, riprel, disp, dataSize=1
+};
+
+def macroop CLWB_M
+{
+clwb t1, seg, sib, disp, dataSize=1
+};
+
+def macroop CLWB_P
+{
+rdip t7
+clwb t1, seg, riprel, disp, dataSize=1
+};
+
 '''

 #let {{
@@ -71,6 +106,4 @@
 #   "GenFault ${new UnimpInstFault}"
 #class PREFETCHW(Inst):
 #   "GenFault ${new UnimpInstFault}"
-#class CLFLUSH(Inst):
-#   "GenFault ${new UnimpInstFault}"
 #}};
diff --git a/src/arch/x86/isa/microops/ldstop.isa  
b/src/arch/x86/isa/microops/ldstop.isa

index a3d9c5a..83e24e1 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -634,6 +634,11 @@
 ''')

 defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
+defineMicroStoreOp('Clflushopt', 'Mem = 0;',
+   mem_flags="Request::CLEAN | Request::INVALIDATE" +
+   " | Request::DST_POC")
+defineMicroStoreOp('Clwb', 'Mem = 0;',
+   mem_flags="Request::CLEAN | Request::DST_POC")

 def defineMicroStoreSplitOp(mnemonic, code,
 completeCode="", mem_flags="0"):

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[gem5-dev] Change in public/gem5[master]: dev: Fix wrong missing fallthrough

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/7301

to look at the new patch set (#2).

Change subject: dev: Fix wrong missing fallthrough
..

dev: Fix wrong missing fallthrough

The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2
for x86) incorrectly assumed these missing fallthroughs should have been
breaks. This "implements" the keyboard and mouse output buffers.

This patch changes the behavior back to what was happening before
5c41076bd7610. This code likely needs more updates to support keyboards
correctly.

Note: Without this patch Linux 4.14 won't boot.

Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/dev/x86/i8042.cc
1 file changed, 10 insertions(+), 3 deletions(-)


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Gerrit-Change-Number: 7301
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[gem5-dev] Change in public/gem5[master]: dev: Fix wrong missing fallthrough

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/7301



Change subject: dev: Fix wrong missing fallthrough
..

dev: Fix wrong missing fallthrough

The patch that added M5_FALLTHROUGH (5c41076bd7610 misc: Updates for gcc7.2
for x86) incorrectly assumed these missing fallthroughs should have been
breaks. Since we do not implement the keyboard output buffer any writes
should look like mouse output buffer writes. Otherwise, the panic on line
386 is triggered on the next write.

This patch changes the behavior back to what was happening before
5c41076bd7610. This code likely needs more updates to support keyboards
correctly.

Note: Without this patch Linux 4.14 won't boot.

Change-Id: I7de137b46cef00e6c1f1c14335cb52107cd7fe5b
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/dev/x86/i8042.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index c5fca1b..de5e173 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -455,12 +455,12 @@
   case WriteOutputPort:
 warn("i8042 \"Write output port\" command not implemented.\n");
 lastCommand = WriteOutputPort;
-break;
+M5_FALLTHROUGH;
   case WriteKeyboardOutputBuff:
 warn("i8042 \"Write keyboard output buffer\" "
 "command not implemented.\n");
 lastCommand = WriteKeyboardOutputBuff;
-break;
+M5_FALLTHROUGH;
   case WriteMouseOutputBuff:
 DPRINTF(I8042, "Got command to write to mouse output  
buffer.\n");

 lastCommand = WriteMouseOutputBuff;

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Re: [gem5-dev] remote GDB debugging

[Jason Lowe-Power]

Hi Gabe,

All of this seems reasonable to me. I've never really used the remote GDB
feature, so I don't have any insight to give you. I strongly agree that
multiple system objects can make sense (I have some patches which use this
ability), so we shouldn't break that. For multithreaded GDB support, I
think it's less important than other things. I haven't heard anyone ask for
that feature. Though, I haven't been listening for it either.

Cheers,
Jason

On Tue, Jan 9, 2018 at 1:26 AM Gabe Black  wrote:

> Hi folks. As part of looking at refactoring how ISAs plug into things, I
> started looking at how remote GDB is set up. Currently the system object
> does that through its registerThreadContext function, where it queries the
> remote GDB port (set through a gem5 command line option), and then
> instantiates a remote GDB object and a listener to listen on that port. If
> the CPU this thread goes with has the wait_for_remote_gdb parameter set,
> then gem5 will wait for the connection before continuing.
>
> The first most fundamental problem is that this assumes that there's a
> single System object in the simulation. Unlike the Root SimObject, I don't
> think that this is guaranteed, and actually I think it's a design feature
> that there can be multiple systems which, for instance, communicate with
> each other over a simulated network link. If there are multiple system
> objects, they will each have a thread with, for instance, ID 0, and so will
> both try to set up a listener at port + 0.
>
> What I think might make more sense is for each System object to have a
> scalar or vector RemoteGDB SimObject parameter, and for python to assign
> port numbers incrementally, starting with the gem5 command line argument.
> If no remote GDB parameter is assigned, then there won't be any GDB
> debugging on that system.
>
> This all makes it a bit more feasible to abstract out the ISA variant of
> remote GDB being used, because the right type can be assigned in already
> ISA specialized system classes in python and not new-ed manually in the top
> level system.cc.
>
> Also, I think it would be nice if the remote GDB protocol implementation
> would be extended so that it supports working with multiple threads. Each
> thread in gem5 would then correspond to a thread in gdb. There could
> potentially be issues where gem5 wants to either run or stop everything,
> and gdb might want to run or stop single threads. This makes things a
> little easier as far as setting up System classes in python too, since you
> don't have to know how many threads there are to know how many remote GDBs
> you need to instantiate.
>
> Please let me know what you think, especially if you have any insight into
> debugging multicore/multithreaded systems with remote GDB and any pitfalls
> we might run into there.
>
> Gabe
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Re: [gem5-dev] Using branching in gem5 public

[Jason Lowe-Power]

Hey Tony,

A few thoughts:

I think it's a good idea to post pre-production code publicly. This gives
other developers a chance to see and comment on the design (well, it
*could*), and, more importantly, it gives users access to new features
quickly.

There is one potential downside to the above: Less motivation to clean up
code and push it into the mainline. I don't know how large of a downside
this is, but from my personal experience with gem5-gpu, it's likely to
happen. Merging gem5-gpu with mainline gem5 is *a lot* of work, and since
we published our gem5 changes in another repo we never felt the need to
undertake it. This was bad for the long-term viability of gem5-gpu and
gem5-gpu's users.

As far as specifically branches go, I think I would prefer to see separate
repos like the arm/gem5 repo (or my github repo). I worry about two things
when bringing branches into public/gem5.
1. We will have too many branches and it will be difficult to manage
2. Configuring gerrit so code-review is only required on master and
whenever others post changes to any other branch no one gets emailed.

The second concern may be solvable (I have no idea), and the first concern
may not be warranted.

I completely agree that branches are great (see my github repo, for
instance. I have 10-20 branches personally). However, one thing I have
discovered is that when working in a group you have to be *very* careful
about how branches are managed across the group (e.g., when and who is
allowed to rebase).

I think using separate repositories gives most of the benefits of branches
(simple to pull changes from others and see others work, better
organization, etc) without the downsides.

I'm open to other points of view, of course!

Cheers,
Jason

On Thu, Dec 14, 2017 at 8:30 AM Gutierrez, Anthony <
anthony.gutier...@amd.com> wrote:

> Hi All,
>
> I have a question about using branches in the mainline gem5 repo. I see
> ARM have a separate repo here:
> https://gem5-review.googlesource.com/admin/projects/arm/gem5. It is used
> for staging ARM features under development. At AMD we would like to do
> something similar, as we have some significant changes to the GPU model we
> would like to push out to the public. We were thinking about doing so with
> branches, and were wondering what others thought about branches? I'm sure
> it's been discussed somewhat in the past, but I can't find much searching
> through old posts.
>
> What I was thinking would be to have institutional branches, like AMD or
> ARM branches, and perhaps users from those institutions who are also gem5
> maintainers could have user specific branches. We use branches a lot
> internally and find them extremely useful. So I'd like to get a better idea
> why there is an aversion to using branches on the public tree, if there is
> such an aversion.
>
> -Tony
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[gem5-dev] Change in public/gem5[master]: ext: Upgrade PyBind11 to version 2.2.1

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5801 )


Change subject: ext: Upgrade PyBind11 to version 2.2.1
..

ext: Upgrade PyBind11 to version 2.2.1

This upgrade is necessary for pybind to build with GCC 7.2.

We still need to add the patch for stl.h. MSC_FULL_VER change is no longer
needed.
See https://gem5-review.googlesource.com/c/public/gem5/+/2230

Change-Id: I806729217d022070583994c2dfcaa74476aef30f
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5801
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M ext/pybind11/.appveyor.yml
M ext/pybind11/.travis.yml
M ext/pybind11/CMakeLists.txt
M ext/pybind11/ISSUE_TEMPLATE.md
M ext/pybind11/MANIFEST.in
M ext/pybind11/docs/Doxyfile
M ext/pybind11/docs/advanced/cast/custom.rst
M ext/pybind11/docs/advanced/cast/eigen.rst
M ext/pybind11/docs/advanced/cast/functional.rst
M ext/pybind11/docs/advanced/cast/overview.rst
M ext/pybind11/docs/advanced/cast/stl.rst
M ext/pybind11/docs/advanced/cast/strings.rst
M ext/pybind11/docs/advanced/classes.rst
A ext/pybind11/docs/advanced/embedding.rst
M ext/pybind11/docs/advanced/functions.rst
M ext/pybind11/docs/advanced/misc.rst
M ext/pybind11/docs/advanced/pycpp/numpy.rst
M ext/pybind11/docs/advanced/pycpp/object.rst
M ext/pybind11/docs/advanced/pycpp/utilities.rst
M ext/pybind11/docs/advanced/smart_ptrs.rst
M ext/pybind11/docs/basics.rst
M ext/pybind11/docs/benchmark.py
M ext/pybind11/docs/benchmark.rst
M ext/pybind11/docs/changelog.rst
M ext/pybind11/docs/classes.rst
M ext/pybind11/docs/compiling.rst
M ext/pybind11/docs/conf.py
M ext/pybind11/docs/faq.rst
M ext/pybind11/docs/index.rst
M ext/pybind11/docs/reference.rst
M ext/pybind11/docs/release.rst
A ext/pybind11/docs/upgrade.rst
M ext/pybind11/include/pybind11/attr.h
A ext/pybind11/include/pybind11/buffer_info.h
M ext/pybind11/include/pybind11/cast.h
M ext/pybind11/include/pybind11/chrono.h
M ext/pybind11/include/pybind11/common.h
M ext/pybind11/include/pybind11/complex.h
R ext/pybind11/include/pybind11/detail/class.h
A ext/pybind11/include/pybind11/detail/common.h
R ext/pybind11/include/pybind11/detail/descr.h
A ext/pybind11/include/pybind11/detail/init.h
A ext/pybind11/include/pybind11/detail/internals.h
R ext/pybind11/include/pybind11/detail/typeid.h
M ext/pybind11/include/pybind11/eigen.h
A ext/pybind11/include/pybind11/embed.h
M ext/pybind11/include/pybind11/eval.h
M ext/pybind11/include/pybind11/functional.h
A ext/pybind11/include/pybind11/iostream.h
M ext/pybind11/include/pybind11/numpy.h
M ext/pybind11/include/pybind11/operators.h
M ext/pybind11/include/pybind11/options.h
M ext/pybind11/include/pybind11/pybind11.h
M ext/pybind11/include/pybind11/pytypes.h
M ext/pybind11/include/pybind11/stl.h
M ext/pybind11/include/pybind11/stl_bind.h
A ext/pybind11/pybind11/__main__.py
M ext/pybind11/pybind11/_version.py
M ext/pybind11/setup.py
M ext/pybind11/tests/CMakeLists.txt
M ext/pybind11/tests/conftest.py
M ext/pybind11/tests/constructor_stats.h
A ext/pybind11/tests/local_bindings.h
A ext/pybind11/tests/pybind11_cross_module_tests.cpp
M ext/pybind11/tests/pybind11_tests.cpp
M ext/pybind11/tests/pybind11_tests.h
M ext/pybind11/tests/pytest.ini
D ext/pybind11/tests/test_alias_initialization.cpp
D ext/pybind11/tests/test_alias_initialization.py
M ext/pybind11/tests/test_buffers.cpp
M ext/pybind11/tests/test_buffers.py
A ext/pybind11/tests/test_builtin_casters.cpp
A ext/pybind11/tests/test_builtin_casters.py
A ext/pybind11/tests/test_call_policies.cpp
A ext/pybind11/tests/test_call_policies.py
M ext/pybind11/tests/test_callbacks.cpp
M ext/pybind11/tests/test_callbacks.py
M ext/pybind11/tests/test_chrono.cpp
M ext/pybind11/tests/test_chrono.py
A ext/pybind11/tests/test_class.cpp
A ext/pybind11/tests/test_class.py
D ext/pybind11/tests/test_class_args.cpp
D ext/pybind11/tests/test_class_args.py
A ext/pybind11/tests/test_cmake_build/CMakeLists.txt
A ext/pybind11/tests/test_cmake_build/embed.cpp
A ext/pybind11/tests/test_cmake_build/installed_embed/CMakeLists.txt
M ext/pybind11/tests/test_cmake_build/main.cpp
A ext/pybind11/tests/test_cmake_build/subdirectory_embed/CMakeLists.txt
M ext/pybind11/tests/test_constants_and_functions.cpp
M ext/pybind11/tests/test_constants_and_functions.py
A ext/pybind11/tests/test_copy_move.cpp
A ext/pybind11/tests/test_copy_move.py
D ext/pybind11/tests/test_copy_move_policies.cpp
D ext/pybind11/tests/test_copy_move_policies.py
M ext/pybind11/tests/test_docstring_options.cpp
M ext/pybind11/tests/test_docstring_options.py
M ext/pybind11/tests/test_eigen.cpp
M ext/pybind11/tests/test_eigen.py
A ext/pybind11/tests/test_embed/CMakeLists.txt
A ext/pybind11/tests/test_embed/catch.cpp
A ext/pybind11/tests/test_embed/test_interpreter.cpp
A ext/pybind11/tests/test_embed/test_interpreter.py
M 

[gem5-dev] Change in public/gem5[master]: misc: Updates for gcc7.2 for x86

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/5802 )


Change subject: misc: Updates for gcc7.2 for x86
..

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
  case statments. C++17 adds the [[fallthrough]]; declaration. However,
  to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
  M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
  if that doesn't exist, it defaults to nothing (no older compilers
  generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
  in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include  for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabebl...@google.com>
---
M ext/dnet/ip.h
M ext/drampower/src/Utils.h
M src/arch/arm/isa.cc
M src/arch/arm/table_walker.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa/microops/regop.isa
M src/base/compiler.hh
M src/base/cprintf.cc
M src/base/imgwriter.cc
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/dyn_inst.cc
M src/dev/arm/generic_timer.cc
M src/dev/net/i8254xGBe.cc
M src/dev/pci/copy_engine.cc
M src/dev/storage/ide_disk.cc
M src/dev/x86/i8042.cc
M src/kern/linux/printk.cc
M src/mem/slicc/symbols/Type.py
M src/sim/eventq.hh
M src/sim/fd_array.cc
21 files changed, 54 insertions(+), 56 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved



diff --git a/ext/dnet/ip.h b/ext/dnet/ip.h
index 95b7718..d2f9ad1 100644
--- a/ext/dnet/ip.h
+++ b/ext/dnet/ip.h
@@ -428,47 +428,13 @@
 ip_cksum_add(const void *buf, size_t len, int cksum)
 {
 uint16_t *sp = (uint16_t *)buf;
-int n, sn;
+int sn;

 sn = len / 2;
-n = (sn + 15) / 16;

-/* XXX - unroll loop using Duff's device. */
-switch (sn % 16) {
-case 0:do {
-cksum += *sp++;
-case 15:
-cksum += *sp++;
-case 14:
-cksum += *sp++;
-case 13:
-cksum += *sp++;
-case 12:
-cksum += *sp++;
-case 11:
-cksum += *sp++;
-case 10:
-cksum += *sp++;
-case 9:
-cksum += *sp++;
-case 8:
-cksum += *sp++;
-case 7:
-cksum += *sp++;
-case 6:
-cksum += *sp++;
-case 5:
-cksum += *sp++;
-case 4:
-cksum += *sp++;
-case 3:
-cksum += *sp++;
-case 2:
-cksum += *sp++;
-case 1:
-cksum += *sp++;
-} while (--n > 0);
-}
+do {
+cksum += *sp++;
+} while (--sn > 0);
 if (len & 1)
 cksum += htons(*(u_char *)sp << 8);

diff --git a/ext/drampower/src/Utils.h b/ext/drampower/src/Utils.h
index 80f4390..7c165a3 100644
--- a/ext/drampower/src/Utils.h
+++ b/ext/drampower/src/Utils.h
@@ -46,7 +46,6 @@
 template
 T fromString(const std::string& s,
  std::ios_base& (*f)(std::ios_base &) = std::dec)
-throw(std::runtime_error)
 {
   std::istringstream is(s);
   T t;
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a490e5f..44e4ff3 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1653,6 +1653,7 @@
 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
 }
 }
+M5_FALLTHROUGH;
   case MISCREG_TTBR0:
   case MISCREG_TTBR1:
 {
@@ -1666,12 +1667,14 @@
 }
 }
 }
+M5_FALLTHROUGH;
   case MISCREG_SCTLR_EL1:
 {
 tc->getITBPtr()->invalidateMiscReg();
 tc->getDTBPtr()->invalidateMiscReg();
 setMiscRegNoEffect(misc_reg, newVal);
 }
+M5_FALLTHROUGH;
   case MISCREG_CONTEXTIDR:
   case MISCREG_PRRR:
   case MISCREG_NMRR:
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 2d66642..63b67f5 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1398,6 +1398,7 @@
   case 0x1 ... 0x3: // Norm

[gem5-dev] Change in public/gem5[master]: misc: Updates for gcc7.2 for x86

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/5802

to look at the new patch set (#12).

Change subject: misc: Updates for gcc7.2 for x86
..

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
  case statments. C++17 adds the [[fallthrough]]; declaration. However,
  to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
  M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
  if that doesn't exist, it defaults to nothing (no older compilers
  generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
  in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include  for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M ext/dnet/ip.h
M ext/drampower/src/Utils.h
M src/arch/arm/isa.cc
M src/arch/arm/table_walker.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa/microops/regop.isa
M src/base/compiler.hh
M src/base/cprintf.cc
M src/base/imgwriter.cc
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/dyn_inst.cc
M src/dev/arm/generic_timer.cc
M src/dev/net/i8254xGBe.cc
M src/dev/pci/copy_engine.cc
M src/dev/storage/ide_disk.cc
M src/dev/x86/i8042.cc
M src/kern/linux/printk.cc
M src/mem/slicc/symbols/Type.py
M src/sim/eventq.hh
M src/sim/fd_array.cc
21 files changed, 54 insertions(+), 56 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Gerrit-Change-Number: 5802
Gerrit-PatchSet: 12
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-CC: Brandon Potter <brandon.pot...@amd.com>
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[gem5-dev] Change in public/gem5[master]: misc: Updates for gcc7.2 for x86

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/5802

to look at the new patch set (#10).

Change subject: misc: Updates for gcc7.2 for x86
..

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
  case statments. C++17 adds the [[fallthrough]]; declaration. However,
  to support non C++17 standards (i.e., C++11), we use gnu::fallthrough.
* The above resulted in a couple of bugs that were found. This is noted
  in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include  for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M ext/dnet/ip.h
M ext/drampower/src/Utils.h
M src/arch/arm/isa.cc
M src/arch/arm/table_walker.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa/microops/regop.isa
M src/base/compiler.hh
M src/base/cprintf.cc
M src/base/imgwriter.cc
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/dyn_inst.cc
M src/dev/arm/generic_timer.cc
M src/dev/net/i8254xGBe.cc
M src/dev/pci/copy_engine.cc
M src/dev/storage/ide_disk.cc
M src/dev/x86/i8042.cc
M src/kern/linux/printk.cc
M src/mem/slicc/symbols/Type.py
M src/sim/eventq.hh
M src/sim/fd_array.cc
21 files changed, 54 insertions(+), 56 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Gerrit-Change-Number: 5802
Gerrit-PatchSet: 10
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: base: Add endianness conversion functions for std::array types.

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#2) to the change originally  
created by Gabe Black. ( https://gem5-review.googlesource.com/6581 )


Change subject: base: Add endianness conversion functions for std::array  
types.

..

base: Add endianness conversion functions for std::array types.

These swap the endianness of each element within the array
individually.

They probably obsolute the Twin(32|64)_t types which I believe were
used for SPARC.

Change-Id: Ic389eb24bdcdc0081068b0c5a37abdf416f6c924
---
M src/sim/byteswap.hh
1 file changed, 9 insertions(+), 0 deletions(-)


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Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic389eb24bdcdc0081068b0c5a37abdf416f6c924
Gerrit-Change-Number: 6581
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-Assignee: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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[gem5-dev] Change in public/gem5[master]: x86: Rework how "split" loads/stores are handled.

[Jason Lowe-Power (Gerrit)]

Jason Lowe-Power has uploaded a new patch set (#2) to the change originally  
created by Gabe Black. ( https://gem5-review.googlesource.com/6582 )


Change subject: x86: Rework how "split" loads/stores are handled.
..

x86: Rework how "split" loads/stores are handled.

Explicitly separate the way the data is represented in the underlying
representation from how it's represented in the instruction.

In order to make the ISA parser happy, the Mem operand needs to have
a single, particular type. To handle that with scalar types, we just
used uint64_ts and then worked with values that were smaller than the
maximum we could hold. To work with these new array values, we also
use an underlying uint64_t for each element.

To make accessing the underlying memory system more natural, when we
go to actually read or write values, we translate the access into an
array of the actual, correct underlying type. That way we don't have
non-exact asserts which confuse gcc, or weird endianness conversion
which assumes that the data should be flipped 8 bytes at a time.

Because the functions involved are generally inline, the syntactic
niceness should all boil off, and the final implementation in the
binary should be simple and efficient for the given data types.

Change-Id: I14ce7a2fe0dc2cbaf6ad4a0d19f743c45ee78e26
---
M src/arch/x86/isa/microops/ldstop.isa
M src/arch/x86/memhelpers.hh
2 files changed, 101 insertions(+), 94 deletions(-)


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Gerrit-Change-Id: I14ce7a2fe0dc2cbaf6ad4a0d19f743c45ee78e26
Gerrit-Change-Number: 6582
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-Assignee: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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Re: [gem5-dev] Linux 4.9 kernel for gem5 now available for Arm

[Jason Lowe-Power]

Hi Jasmin,

See http://www.lowepower.com/jason/setting-up-gem5-fv4.14-rc3ull-system.html
<http://www.lowepower.com/jason/setting-up-gem5-full-system.html> for an
example of what I've done.

You can simply compile a kernel and build a disk image. It really isn't
much harder than that. There are two gotchas: 1) making sure to compile
without modules (compile all needed drivers into the kernel) and 2)
disabling drivers that break gem5. There is a link on that page to a config
file that has worked for me in the past. I've also successfully built and
run v4.14-rc3 recently.

The only other problem that I've run into is getting the init/startup
process working correctly to get the gem5init script working. However, this
is orthogonal to any gem5 issues. It's just that Ubuntu is using upstart
(or whatever they are using now) and that is *incredibly* difficult to use.

Hope this helps!

Cheers,
Jason

---
Jason Lowe-Power
Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/


On Tue, Dec 12, 2017 at 2:44 PM Jasmin Jahic <jasmin.ja...@gmail.com> wrote:

> Hello,
>
> great to hear that! May I ask, what is the situation with x86? Besides the
> Gentoo solution, present at the website, were there some efforts to bring
> to life some other, newer version of Linux?
>
> Best regards,
> Jasmin JAHIC
>
> On Mon, Dec 11, 2017 at 6:18 PM, Andreas Sandberg <
> andreas.sandb...@arm.com>
> wrote:
>
> > Hi Everyone,
> >
> > I'm happy to announce that we have just completed testing of the
> > gem5-specific patches for Linux 4.9. The new kernel is can be downloaded
> > from the gem5/v4.9 branch in the arm/linux [1] repository.
> >
> > The kernel comes with default configurations for Armv7 and Armv8 and has
> > the same set of gem5-specific patches as the older 4.x kernels. These
> > patches add support for:
> >
> >   * gem5's GICv2 extensions. This enables support for up to 255 CPUs if
> > the gem5 extensions are enabled in the GIC (set gem5_extensions to True
> > in your configuration script).
> >   * A virtual DRM connector. This makes it possible to use gem5's
> > display models without a proper HDMI encoder model.
> >   * The custom FBIOGET_DMABUF IOCTL. This change is useful to avoid a
> > CPU-side memcpy between the GPU's render buffer and the framebuffer for
> > Android setups that using NoMali.
> >   * gem5's DVFS controller.
> >   * General gem5 instrumentation.
> >
> > Cheers,
> > Andreas
> >
> > [1] https://gem5-review.googlesource.com/#/admin/projects/arm/linux
> > [2] http://gem5.org/ARM_Kernel
> >
> > IMPORTANT NOTICE: The contents of this email and any attachments are
> > confidential and may also be privileged. If you are not the intended
> > recipient, please notify the sender immediately and do not disclose the
> > contents to any other person, use it for any purpose, or store or copy
> the
> > information in any medium. Thank you.
> > ___
> > gem5-dev mailing list
> > gem5-dev@gem5.org
> > http://m5sim.org/mailman/listinfo/gem5-dev
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Re: [gem5-dev] Implementing leaf 4 of cpuid

[Jason Lowe-Power]

Hi Sam,

The way *I* would do this (though it may not be the best way) is to do what
you suggest, precompute the cpuid value in python and set that as a
parameter on the System object (maybe the CPU? Can different cores return
different cpuid values?).

You should be able to access all of this information from Python. The
hardest part is trying to make the code general. For instance, there is no
way for you as the API writer will know what the gem5 user will name their
caches. Usually it's icache/dcache, but there's nothing in gem5 to enforce
those names (for good reason!).

My initial thought is to add a python function to the System which takes
"caches" as parameters. "Caches" in the sense of Python's duck typing so
you could pass either a Cache object or a RubyCache object (they both have
parameters named "size" and "assoc" so they should be interchangeable
here). This function can compute the needed value for the cpuid.

If you think it's more appropriate to have the cpuid a parameter of the
CPU, then maybe the computeCpuid function should be a helper function
somewhere else (I'm not sure where would be best. I suppose BaseCPU would
make sense.).

Please submit a patch when you do implement this! :)

Cheers,
Jason

---
Jason Lowe-Power
Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://faculty.engineering.ucdavis.edu/lowepower/



On Tue, Dec 12, 2017 at 9:07 PM Sam Xi <liku...@fas.harvard.edu> wrote:

> Hi,
>
> I am trying to implement another part of the cpuid instruction, namely leaf
> 4, which returns deterministic cache parameters of the system (size,
> associativity, etc). However, I'm a bit stumped as to how I can actually
> access this information. There doesn't seem to be any way to get a pointer
> to a Cache object from the CPU or the System. The most I've been able to
> find is getting a handle to the master port for either the icache or the
> dcache, but even then there's no way to get a handle to the owner of the
> corresponding slave port. It seems that the only bird's eye view of the
> system is available in Python. So if this is all true, then would the best
> way to implement this to be precomputing all the register outputs in python
> and setting them appropriately in the CPU objects as the caches are
> instantiated?
>
> Thanks,
> Sam
> --
> Thanks,
>
> Sam Xi
> Harvard University
> Computer Science, Ph.D. Candidate
> http://www.samxi.org
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[gem5-dev] Change in public/gem5[master]: misc: Updates for gcc7.2 for x86

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/5802

to look at the new patch set (#9).

Change subject: misc: Updates for gcc7.2 for x86
..

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
  case statments. C++17 adds the [[fallthrough]]; declaration. However,
  to support non C++17 standards (i.e., C++11), we use gnu::fallthrough.
* The above resulted in a couple of bugs that were found. This is noted
  in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include  for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M ext/dnet/ip.h
M ext/drampower/src/Utils.h
M src/arch/arm/isa.cc
M src/arch/arm/table_walker.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/memhelpers.hh
M src/base/compiler.hh
M src/base/cprintf.cc
M src/base/imgwriter.cc
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/dyn_inst.cc
M src/dev/arm/generic_timer.cc
M src/dev/net/i8254xGBe.cc
M src/dev/pci/copy_engine.cc
M src/dev/storage/ide_disk.cc
M src/dev/x86/i8042.cc
M src/kern/linux/printk.cc
M src/mem/slicc/symbols/Type.py
M src/sim/eventq.hh
M src/sim/fd_array.cc
22 files changed, 58 insertions(+), 62 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Gerrit-Change-Number: 5802
Gerrit-PatchSet: 9
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-CC: Brandon Potter <brandon.pot...@amd.com>
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[gem5-dev] Change in public/gem5[master]: misc: Updates for gcc7.2 for x86

[Jason Lowe-Power (Gerrit)]

Hello Gabe Black, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/5802

to look at the new patch set (#8).

Change subject: misc: Updates for gcc7.2 for x86
..

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
  case statments. C++17 adds the [[fallthrough]]; declaration. However,
  to support non C++17 standards (i.e., C++11), we use gnu::fallthrough.
* The above resulted in a couple of bugs that were found. This is noted
  in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include  for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M ext/dnet/ip.h
M ext/drampower/src/Utils.h
M src/arch/arm/isa.cc
M src/arch/arm/table_walker.cc
M src/arch/x86/isa.cc
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/memhelpers.hh
M src/base/compiler.hh
M src/base/cprintf.cc
M src/base/imgwriter.cc
M src/cpu/kvm/base.cc
M src/cpu/kvm/x86_cpu.cc
M src/cpu/minor/dyn_inst.cc
M src/dev/arm/generic_timer.cc
M src/dev/net/i8254xGBe.cc
M src/dev/pci/copy_engine.cc
M src/dev/storage/ide_disk.cc
M src/dev/x86/i8042.cc
M src/kern/linux/printk.cc
M src/mem/slicc/symbols/Type.py
M src/sim/eventq.hh
M src/sim/fd_array.cc
22 files changed, 57 insertions(+), 60 deletions(-)


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To view, visit https://gem5-review.googlesource.com/5802
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Gerrit-Change-Number: 5802
Gerrit-PatchSet: 8
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-CC: Brandon Potter <brandon.pot...@amd.com>
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