[linux-sunxi] Re: GMAC Reveice Clock Delay Chain value
Am Dienstag, 2. Juni 2015 13:44:31 UTC+2 schrieb thomas...@phg-online.de: Hello, since modifying/setting CONFIG_GMAC_TX_DELAY in u-boot seems to be necessary to get GMAC work reliable on some boards I wonder whether GMAC_RX_DELAY isn't worth a look (with many A20 based boards we've here we experience big differences in TX and RX throughput). The background is outlined here: http://lists.denx.de/pipermail/u-boot/2014-September/190239.html RX delay seems to be related to bits 5-7 of the GMAC clk register, TX delay is defined in bits 10-12. AFAIK this stuff is still undocumented so I decided to try to brute-force through all possible combinations. I tried to patch both 'board/sunxi/Kconfig' and 'board/sunxi/gmac.c' to be able to define 'CONFIG_GMAC_RX_DELAY' in defconfigs. Then I let a script create 64 different u-boot versions as debian packages to be able to test them automatically. It seems to make a difference. Currently I test an Olimex Lime2 and will provide results later (each test run takes approx. 90 seconds including reboot, 30 seconds iperf test, exchange of u-boot and next automated reboot). Can anyone please tell me whether these 2 u-boot modifications against v2015.04 (http://pastebin.com/adiWjzya) are correct to modify bits 5-7 of GMAC clk register: --- diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 2fcab60..4623de6 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -451,4 +451,10 @@ config GMAC_TX_DELAY ---help--- Set the GMAC Transmit Clock Delay Chain value. +config GMAC_RX_DELAY +int GMAC Receive Clock Delay Chain +default 0 +---help--- +Set the GMAC Reveice Clock Delay Chain value. + endif diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 8849132..1bce3ce 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -26,6 +26,8 @@ int sunxi_gmac_initialize(bd_t *bis) CCM_GMAC_CTRL_GPIT_RGMII); setbits_le32(ccm-gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); +setbits_le32(ccm-gmac_clk_cfg, + CCM_GMAC_CTRL_RX_CLK_DELAY(CONFIG_GMAC_RX_DELAY)); #else setbits_le32(ccm-gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | CCM_GMAC_CTRL_GPIT_MII); -- Regards, Thomas Sound interesting. How did your test runs work out? Regards, Timo -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: Mainline U-boot wiki page updated
Am Freitag, 5. Juni 2015 05:36:42 UTC+2 schrieb Chen-Yu Tsai: Hi, I've updated the wiki page with all the new U-boot releases, as well as the latest stuff planned for v2015.07. I might have missed something, so a second set of eyes would be nice. Regards ChenYu Hi, thanks for working on this. Just one suggestion (that has little to do with the recent U-Boot changes): The wiki currently has different instructions on how to build the mainline kernel and boot it. While the instructions on the Mainline U-Boot page http://linux-sunxi.org/Mainline_U-boot#Boot use a uImage, the Mainline Kernel Howto http://linux-sunxi.org/Mainline_Kernel_Howto#Boot uses a zImage with different loadadresses. This might confuse people. Can we unify this and just mention one recommended way? Regards, Timo -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [RFC 07/11] mtd/nand Add Sunxi NAND driver
Heavily based on BBrezillon's (downstream) driver. Most noticable differences - No per-partition ECC settings. Partitions in U-boot are quite different from Linux - U-boot register definitions, shared with sunxi_nand_spl - FDT parsing in-line, there's no framework method yet Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- arch/arm/include/asm/arch-sunxi/nand.h | 46 +- board/sunxi/board.c|5 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/sunxi_nand.c | 1887 include/fdtdec.h | 13 + lib/fdtdec.c | 17 + 6 files changed, 1966 insertions(+), 3 deletions(-) create mode 100644 drivers/mtd/nand/sunxi_nand.c diff --git a/arch/arm/include/asm/arch-sunxi/nand.h b/arch/arm/include/asm/arch-sunxi/nand.h index 22844d8..d0fae80 100644 --- a/arch/arm/include/asm/arch-sunxi/nand.h +++ b/arch/arm/include/asm/arch-sunxi/nand.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2015 Roy Spliet rspl...@ultimaker.com + * (C) Copyright 2015 Roy Spliet r.spl...@ultimaker.com * * SPDX-License-Identifier:GPL-2.0+ */ @@ -27,8 +27,7 @@ struct sunxi_nand u32 ecc_ctl;/* 0x034 ECC configure and control */ u32 ecc_st; /* 0x038 ECC status and operation info */ u32 efr;/* 0x03C Enhanced feature */ - u32 err_cnt0; /* 0x040 Corrected error bit counter 0 */ - u32 err_cnt1; /* 0x044 Corrected error bit counter 1 */ + u32 err_cnt[4]; /* 0x040[4] Corrected error bit counter 0 */ u32 user_data[16]; /* 0x050[16] User data field */ u32 efnand_st; /* 0x090 EFNAND status */ u32 res0[3]; @@ -40,28 +39,69 @@ struct sunxi_nand u32 res1[3]; u32 mdma_addr; /* 0x0C0 MBUS DMA Address */ u32 mdma_cnt; /* 0x0C4 MBUS DMA data counter */ + u32 res2[206]; + u32 ram0_base; }; #define SUNXI_NAND_CTL_EN (1 0) #define SUNXI_NAND_CTL_RST (1 1) +#define SUNXI_NAND_BUS_WIDTH (1 2) +#define SUNXI_NAND_CTL_RB_SEL_MASK (0x3 3) +#define SUNXI_NAND_CTL_RB_SEL(a) ((a) 3) +#define SUNXI_NAND_CTL_CE_ACT (1 6) +#define SUNXI_NAND_CTL_PAGE_SIZE_MASK (0xf 8) #define SUNXI_NAND_CTL_PAGE_SIZE(a)((fls(a) - 11) 8) #define SUNXI_NAND_CTL_RAM_METHOD_DMA (1 14) +#define SUNXI_NAND_CTL_CE_SEL_MASK (0xf 24) +#define SUNXI_NAND_CTL_CE_SEL(a) (a 24) +#define SUNXI_NAND_CTL_DEBUG (1 31) +#define SUNXI_NAND_ST_RB_B2R (1 0) #define SUNXI_NAND_ST_CMD_INT (1 1) #define SUNXI_NAND_ST_DMA_INT (1 2) #define SUNXI_NAND_ST_FIFO_FULL(1 3) +#define SUNXI_NAND_ST_BUSY (1 4) +#define SUNXI_NAND_ST_RB_STATE0(1 8) +#define SUNXI_NAND_ST_RB_STATE1(1 9) +#define SUNXI_NAND_ST_RB_STATE2(1 10) +#define SUNXI_NAND_ST_RB_STATE3(1 11) + +#define SUNXI_NAND_INT_B2R_ENABLE (1 0) +#define SUNXI_NAND_INT_CMD_ENABLE (1 1) +#define SUNXI_NAND_INT_DMA_ENABLE (1 2) +#define SUNXI_NAND_INT_MASK(SUNXI_NAND_INT_B2R_ENABLE | \ +SUNXI_NAND_INT_CMD_ENABLE | \ +SUNXI_NAND_INT_DMA_ENABLE) + +#define SUNXI_NAND_CMD_LOW_BYTE(a) (a 0xff) +#define SUNXI_NAND_CMD_HIGH_BYTE(a)((a 0xff) 8) #define SUNXI_NAND_CMD_ADDR_CYCLES(a) ((a - 1) 16); +#define SUNXI_NAND_CMD_SEND_ADR(1 19) +#define SUNXI_NAND_CMD_ACCESS_RD 0 +#define SUNXI_NAND_CMD_ACCESS_WR (1 20) +#define SUNXI_NAND_CMD_DATA_TRANS (1 21) #define SUNXI_NAND_CMD_SEND_CMD1 (1 22) #define SUNXI_NAND_CMD_WAIT_FLAG (1 23) +#define SUNXI_NAND_CMD_SEND_CMD2 (1 24) #define SUNXI_NAND_CMD_ORDER_INTERLEAVE0 #define SUNXI_NAND_CMD_ORDER_SEQ (1 25) +#define SUNXI_NAND_CMD_DATA_SWAP_METHOD(1 26) +#define SUNXI_NAND_CMD_ROW_AUTO_INC(1 27) +#define SUNXI_NAND_CMD_SEND_CMD3 (1 28) +#define SUNXI_NAND_CMD_SEND_CMD4 (1 29) #define SUNXI_NAND_ECC_CTL_ECC_EN (1 0) #define SUNXI_NAND_ECC_CTL_PIPELINE(1 3) +#define SUNXI_NAND_ECC_CTL_EXCEPTION (1 4) #define SUNXI_NAND_ECC_CTL_BS_512B (1 5) #define SUNXI_NAND_ECC_CTL_RND_EN (1 9) +#define SUNXI_NAND_ECC_CTL_RND_DIRECTION (1 10) +#define SUNXI_NAND_ECC_CTL_MODE_MASK (0xf 12) #define SUNXI_NAND_ECC_CTL_MODE(a) ((a) 12) +#define
[linux-sunxi] [RFC 10/11] mtd/nand: Define bootcmd for nand
Assumes a UBI partition called boot
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
include/config_distro_bootcmd.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 3a360ca4..361b914 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -72,6 +72,21 @@
BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC
#endif
+#ifdef CONFIG_CMD_NAND
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ bootcmd_nand= \
+ ubi part #devtypel #instance _main; \
+ ubifsmount ubi:boot;\
+ run scan_ubifs_for_script\0
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance)#devtypel
+#else
+#define BOOTENV_SHARED_NAND
+#define BOOTENV_DEV_NAND \
+ BOOT_TARGET_DEVICES_references_NAND_without_CONFIG_CMD_NAND
+#define BOOTENV_DEV_NAME_NAND \
+ BOOT_TARGET_DEVICES_references_NAND_without_CONFIG_CMD_NAND
+#endif
+
#ifdef CONFIG_CMD_SATA
#define BOOTENV_SHARED_SATABOOTENV_SHARED_BLKDEV(sata)
#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV
@@ -202,6 +217,17 @@
echo SCRIPT FAILED: continuing...; \
fi\0\
\
+ scan_ubifs_for_script= \
+ for script in ${boot_scripts}; do \
+ for prefix in ${boot_prefixes}; do \
+ if ubifsload ${scriptaddr} \
+ ${prefix}${script}; then\
+ echo Found U-Boot script\
+ ${prefix}${script}; \
+ source ${scriptaddr}; \
+ fi; \
+ done; \
+ done\0 \
boot_a_script= \
load ${devtype} ${devnum}:${bootpart} \
${scriptaddr} ${prefix}${script}; \
--
2.4.2
--
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[linux-sunxi] [RFC 03/11] mtd/nand: support ONFI timing mode retrieval for non-ONFI
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/nand_base.c | 1 +
include/linux/mtd/nand.h | 7 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index c0e381a..dbeb092 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3709,6 +3709,7 @@ static bool find_full_id_nand(struct mtd_info *mtd,
struct nand_chip *chip,
chip-options |= type-options;
chip-ecc_strength_ds = NAND_ECC_STRENGTH(type);
chip-ecc_step_ds = NAND_ECC_STEP(type);
+ chip-onfi_timing_mode_ds = type-onfi_timing_mode_ds;
*busw = type-options NAND_BUSWIDTH_16;
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index abda5c3..0cdb3b9 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -634,6 +634,7 @@ struct nand_buffers {
* @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
* also from the datasheet. It is the recommended ECC step
* size, if known; if unknown, set to zero.
+ * @onfi_timing_mode_ds:[INTERN] ONFI timing mode deduced from datasheet.
* @numchips: [INTERN] number of physical chips
* @chipsize: [INTERN] the size of one chip for multichip arrays
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
@@ -718,6 +719,7 @@ struct nand_chip {
uint8_t bits_per_cell;
uint16_t ecc_strength_ds;
uint16_t ecc_step_ds;
+ int onfi_timing_mode_ds;
int badblockpos;
int badblockbits;
@@ -822,6 +824,10 @@ struct nand_chip {
* @ecc_step_ds in nand_chip{}, also from the datasheet.
* For example, the 4bit ECC for each 512Byte can be set with
* NAND_ECC_INFO(4, 512).
+ * @onfi_timing_mode_ds: the ONFI timing mode supported by this NAND chip. This
+ * should be deduced from timings described in the
+ * datasheet.
+ *
*/
struct nand_flash_dev {
char *name;
@@ -842,6 +848,7 @@ struct nand_flash_dev {
uint16_t strength_ds;
uint16_t step_ds;
} ecc;
+ int onfi_timing_mode_ds;
};
/**
--
2.4.2
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[linux-sunxi] [RFC 08/11] mtd/nand: Add DT definitions for Olimex Lime
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 41 ++
arch/arm/dts/sun7i-a20.dtsi | 90 +++
2 files changed, 131 insertions(+)
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
index 6592cb2..cc5e65d 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
@@ -181,3 +181,44 @@
usb2_vbus-supply = reg_usb2_vbus;
status = okay;
};
+
+nfc {
+ pinctrl-names = default;
+ pinctrl-0 = nand_pins_a nand_cs0_pins_a nand_rb0_pins_a;
+ status = okay;
+
+ nand@0 {
+ #address-cells = 2;
+ #size-cells = 2;
+ reg = 0;
+ allwinner,rb = 0;
+ nand-ecc-mode = hw;
+ nand-ecc-strength = 40;
+ nand-ecc-step-size = 1024;
+ nand-rnd-mode = hw;
+ nand-randomizer-seeds = /bits/ 16
+ 0x2b75 0x0bd0 0x5ca3 0x62d1 0x1c93 0x07e9 0x2162 0x3a72
+ 0x0d67 0x67f9 0x1be7 0x077d 0x032f 0x0dac 0x2716 0x2436
+ 0x7922 0x1510 0x3860 0x5287 0x480f 0x4252 0x1789 0x5a2d
+ 0x2a49 0x5e10 0x437f 0x4b4e 0x2f45 0x216e 0x5cb7 0x7130
+ 0x2a3f 0x60e4 0x4dc9 0x0ef0 0x0f52 0x1bb9 0x6211 0x7a56
+ 0x226d 0x4ea7 0x6f36 0x3692 0x38bf 0x0c62 0x05eb 0x4c55
+ 0x60f4 0x728c 0x3b6f 0x2037 0x7f69 0x0936 0x651a 0x4ceb
+ 0x6218 0x79f3 0x383f 0x18d9 0x4f05 0x5c82 0x2912 0x6f17
+ 0x6856 0x5938 0x1007 0x61ab 0x3e7f 0x57c2 0x542f 0x4f62
+ 0x7454 0x2eac 0x7739 0x42d4 0x2f90 0x435a 0x2e52 0x2064
+ 0x637c 0x66ad 0x2c90 0x0bad 0x759c 0x0029 0x0986 0x7126
+ 0x1ca7 0x1605 0x386a 0x27f5 0x1380 0x6d75 0x24c3 0x0f8e
+ 0x2b7a 0x1418 0x1fd1 0x7dc1 0x2d8e 0x43af 0x2267 0x7da3
+ 0x4e3d 0x1338 0x50db 0x454d 0x764d 0x40a3 0x42e6 0x262b
+ 0x2d2e 0x1aea 0x2e17 0x173d 0x3a6e 0x71bf 0x25f9 0x0a5d
+ 0x7c57 0x0fbe 0x46ce 0x4939 0x6b17 0x37bb 0x3e91
0x76db;
+ onfi,nand-timing-mode = 0x1f;
+/*
+ main@40 {
+ label = main;
+ reg = /bits/ 64 0x40 0xffc0;
+ };
+*/
+ };
+};
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
index d4ba772..af89575 100644
--- a/arch/arm/dts/sun7i-a20.dtsi
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -612,6 +612,17 @@
clocks = ahb_gates 17;
status = disabled;
};
+
+ nfc: nand@01c03000 {
+ compatible = allwinner,sun4i-nand;
+ reg = 0x01c03000 0x1000;
+ interrupts = 0 37 4;
+ clocks = ahb_gates 13, nand_clk;
+ clock-names = ahb, mod;
+ #address-cells = 1;
+ #size-cells = 0;
+ status = disabled;
+ };
mdio: mdio@01c0b080 {
compatible = allwinner,sun4i-a10-mdio;
@@ -1020,6 +1031,85 @@
allwinner,drive = SUN4I_PINCTRL_10_MA;
allwinner,pull = SUN4I_PINCTRL_NO_PULL;
};
+ nand_pins_a: nand_base0@0 {
+ allwinner,pins = PC0, PC1, PC2,
+ PC5, PC8, PC9, PC10,
+ PC11, PC12, PC13, PC14,
+ PC15, PC16;
+ allwinner,function = nand0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ nand_cs0_pins_a: nand_cs@0 {
+ allwinner,pins = PC4;
+ allwinner,function = nand0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ nand_cs1_pins_a: nand_cs@1 {
+ allwinner,pins = PC3;
+ allwinner,function = nand0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ nand_cs2_pins_a: nand_cs@2 {
+ allwinner,pins = PC17;
+ allwinner,function = nand0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
[linux-sunxi] [RFC] Sunxi NAND support for U-Boot
Following up on earlier SPL patches, here a series based on Yassin Jaffer's work to bring NAND support to U-boot. RFC because I know that the sunxi nand configuration options are dependent on a work-in-progress by Daniel - trying to deliver a single SPL for both MMC and NAND boot. Given I have spent the past few weeks learning how Boris' original driver works, I have probably grown a bit blind for potentially existing issues. Please provide plenty of feedback so I can bring this in good shape. Patches tested on an Olimex Lime with 4GB Hynix nand. Has a partition as defined in sunxi-common.h with two UBIFS partitions (boot, rootfs) set up in Linux. To me it feels self-explanatory how to set this up, but I've spent the last few weeks full-time on this, implying my view of the world and how it revolves around MTD is rather distorted. Feel free to ask directed questions if you desire assistance in setting up and/or testing. Thanks! Roy -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [RFC 04/11] mtd/nand: add page status table (pst)
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/nand_base.c | 154 +++
include/linux/mtd/nand.h | 21 ++
2 files changed, 175 insertions(+)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index dbeb092..1c514a0 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1185,6 +1185,138 @@ EXPORT_SYMBOL(nand_lock);
#endif
/**
+ * nand_page_is_empty - check wether a NAND page contains only FFs
+ * @mtd: mtd info
+ * @data: data buffer
+ * @oob: oob buffer
+ *
+ * Reads the data stored in the databuf buffer and check if it contains only
+ * FFs.
+ *
+ * Return true if it does else return false.
+ */
+bool nand_page_is_empty(struct mtd_info *mtd, void *data, void *oob)
+{
+ u8 *buf;
+ int length;
+ u32 pattern = 0x;
+ int bitflips = 0;
+ int cnt;
+
+ buf = data;
+ length = mtd-writesize;
+ while (length) {
+ cnt = length sizeof(pattern) ? length : sizeof(pattern);
+ if (memcmp(pattern, buf, cnt)) {
+ int i;
+ for (i = 0; i cnt * 8; i++) {
+ if (!(buf[i / 8]
+ (1 (i % 8 {
+ bitflips++;
+ if (bitflips mtd-ecc_strength)
+ return false;
+ }
+ }
+ }
+
+ buf += sizeof(pattern);
+ length -= sizeof(pattern);
+ }
+
+ buf = oob;
+ length = mtd-oobsize;
+ while (length) {
+ cnt = length sizeof(pattern) ? length : sizeof(pattern);
+ if (memcmp(pattern, buf, cnt)) {
+ int i;
+ for (i = 0; i cnt * 8; i++) {
+ if (!(buf[i / 8]
+ (1 (i % 8 {
+ bitflips++;
+ if (bitflips mtd-ecc_strength)
+ return false;
+ }
+ }
+ }
+
+ buf += sizeof(pattern);
+ length -= sizeof(pattern);
+ }
+
+ return true;
+}
+EXPORT_SYMBOL(nand_page_is_empty);
+
+/**
+ * nand_page_get_status - retrieve page status from the page status table (pst)
+ * @mtd: mtd info
+ * @page: page you want to get status on
+ *
+ * Return the page status.
+ */
+int nand_page_get_status(struct mtd_info *mtd, int page)
+{
+ struct nand_chip *chip = mtd-priv;
+ u8 shift = (page % 4) * 2;
+ uint64_t offset = page / 4;
+ int ret = NAND_PAGE_STATUS_UNKNOWN;
+
+ if (chip-pst)
+ ret = (chip-pst[offset] shift) 0x3;
+
+ return ret;
+}
+EXPORT_SYMBOL(nand_page_get_status);
+
+/**
+ * nand_page_set_status - assign page status from in the page status table
+ * @mtd: mtd info
+ * @page: page you want to get status on
+ * @status:new status to assign
+ */
+void nand_page_set_status(struct mtd_info *mtd, int page,
+ enum nand_page_status status)
+{
+ struct nand_chip *chip = mtd-priv;
+ u8 shift;
+ uint64_t offset;
+
+ if (!chip-pst)
+ return;
+
+ shift = (page % 4) * 2;
+ offset = page / 4;
+ chip-pst[offset] = ~(0x3 shift);
+ chip-pst[offset] |= (status 0x3) shift;
+}
+EXPORT_SYMBOL(nand_page_set_status);
+
+/**
+ * nand_pst_create - create a page status table
+ * @mtd: mtd info
+ *
+ * Allocate a page status table and assign it to the mtd device.
+ *
+ * Returns 0 in case of success or -ERRNO in case of error.
+ */
+int nand_pst_create(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd-priv;
+
+ if (chip-pst)
+ return 0;
+
+ chip-pst = kzalloc(mtd-size
+ (chip-page_shift + mtd-subpage_sft + 2),
+ GFP_KERNEL);
+ if (!chip-pst)
+ return -ENOMEM;
+
+ return 0;
+}
+EXPORT_SYMBOL(nand_pst_create);
+
+/**
* nand_read_page_raw - [INTERN] read raw page data without ecc
* @mtd: mtd info structure
* @chip: nand chip info structure
@@ -2521,6 +2653,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t
to,
int bytes = mtd-writesize;
int cached = writelen bytes page != blockmask;
uint8_t *wbuf = buf;
+ int subpage;
WATCHDOG_RESET();
/* Partial page write? */
@@ -2547,6 +2680,14 @@ static int nand_do_write_ops(struct mtd_info *mtd,
loff_t to,
if (ret)
break;
+ for
[linux-sunxi] [RFC 05/11] mtd/nand: take nand_ecc_ctrl initialization out of nand_scan_tail
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/nand_base.c | 101 ++-
1 file changed, 61 insertions(+), 40 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 1c514a0..83586cc 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4114,47 +4114,15 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
}
EXPORT_SYMBOL(nand_scan_ident);
-
-/**
- * nand_scan_tail - [NAND Interface] Scan for the NAND device
- * @mtd: MTD device structure
- *
- * This is the second phase of the normal nand_scan() function. It fills out
- * all the uninitialized function pointers with the defaults and scans for a
- * bad block table if appropriate.
+/*
+ * Initialize ECC struct:
+ * - fill ECC struct with default function/values when these ones are
undefined
+ * - fill ECC infos based on MTD device
*/
-int nand_scan_tail(struct mtd_info *mtd)
+static int nand_ecc_ctrl_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc)
{
int i;
- struct nand_chip *chip = mtd-priv;
- struct nand_ecc_ctrl *ecc = chip-ecc;
- struct nand_buffers *nbuf;
- /* New bad blocks should be marked in OOB, flash-based BBT, or both */
- BUG_ON((chip-bbt_options NAND_BBT_NO_OOB_BBM)
- !(chip-bbt_options NAND_BBT_USE_FLASH));
-
- if (!(chip-options NAND_OWN_BUFFERS)) {
-#ifndef __UBOOT__
- nbuf = kzalloc(sizeof(*nbuf) + mtd-writesize
- + mtd-oobsize * 3, GFP_KERNEL);
- if (!nbuf)
- return -ENOMEM;
- nbuf-ecccalc = (uint8_t *)(nbuf + 1);
- nbuf-ecccode = nbuf-ecccalc + mtd-oobsize;
- nbuf-databuf = nbuf-ecccode + mtd-oobsize;
-#else
- nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
-#endif
-
- chip-buffers = nbuf;
- } else {
- if (!chip-buffers)
- return -ENOMEM;
- }
-
- /* Set the internal oob buffer location, just after the page data */
- chip-oob_poi = chip-buffers-databuf + mtd-writesize;
/*
* If no default placement scheme is given, select an appropriate one.
@@ -4180,9 +4148,6 @@ int nand_scan_tail(struct mtd_info *mtd)
}
}
- if (!chip-write_page)
- chip-write_page = nand_write_page;
-
/*
* Check ECC mode, default to software if 3byte/512byte hardware ECC is
* selected and we have 256 byte pagesize fallback to software ECC
@@ -4349,6 +4314,62 @@ int nand_scan_tail(struct mtd_info *mtd)
}
ecc-total = ecc-steps * ecc-bytes;
+ return 0;
+}
+
+/**
+ * nand_scan_tail - [NAND Interface] Scan for the NAND device
+ * @mtd: MTD device structure
+ *
+ * This is the second phase of the normal nand_scan() function. It fills out
+ * all the uninitialized function pointers with the defaults and scans for a
+ * bad block table if appropriate.
+ */
+int nand_scan_tail(struct mtd_info *mtd)
+{
+ int ret;
+ struct nand_chip *chip = mtd-priv;
+ struct nand_ecc_ctrl *ecc = chip-ecc;
+ struct nand_buffers *nbuf;
+
+ /* New bad blocks should be marked in OOB, flash-based BBT, or both */
+ BUG_ON((chip-bbt_options NAND_BBT_NO_OOB_BBM)
+ !(chip-bbt_options NAND_BBT_USE_FLASH));
+
+ if (!(chip-options NAND_OWN_BUFFERS)) {
+#ifndef __UBOOT__
+ nbuf = kzalloc(sizeof(*nbuf) + mtd-writesize
+ + mtd-oobsize * 3, GFP_KERNEL);
+ if (!nbuf)
+ return -ENOMEM;
+ nbuf-ecccalc = (uint8_t *)(nbuf + 1);
+ nbuf-ecccode = nbuf-ecccalc + mtd-oobsize;
+ nbuf-databuf = nbuf-ecccode + mtd-oobsize;
+#else
+ nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
+#endif
+
+ chip-buffers = nbuf;
+ } else {
+ if (!chip-buffers)
+ return -ENOMEM;
+ }
+
+ /* Set the internal oob buffer location, just after the page data */
+ chip-oob_poi = chip-buffers-databuf + mtd-writesize;
+
+ if (!chip-write_page)
+ chip-write_page = nand_write_page;
+
+ /* Initialize ECC struct */
+ ret = nand_ecc_ctrl_init(mtd, ecc);
+ if (ret) {
+ if (!(chip-options NAND_OWN_BUFFERS))
+ kfree(chip-buffers);
+
+ return ret;
+ }
+
/* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
if (!(chip-options NAND_NO_SUBPAGE_WRITE) nand_is_slc(chip)) {
switch (ecc-steps) {
--
2.4.2
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[linux-sunxi] [RFC 02/11] mtd/nand: add ONFI timing mode to nand_timings converter
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/Makefile | 2 +-
drivers/mtd/nand/nand_timings.c | 252
include/linux/mtd/nand.h| 3 +
3 files changed, 256 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/nand/nand_timings.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index a0cf4d5..f194493 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -32,7 +32,7 @@ obj-y += nand_bbt.o
obj-y += nand_ids.o
obj-y += nand_util.o
obj-y += nand_ecc.o
-obj-y += nand_base.o
+obj-y += nand_base.o nand_timings.o
endif # not spl
diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c
new file mode 100644
index 000..9e8b0a5
--- /dev/null
+++ b/drivers/mtd/nand/nand_timings.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2014 Free Electrons
+ *
+ * Author: Boris BREZILLON boris.brezil...@free-electrons.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include common.h
+#include linux/err.h
+#include linux/mtd/nand.h
+
+static const struct nand_sdr_timings onfi_sdr_timings[] = {
+ /* Mode 0 */
+ {
+ .tADL_min = 20,
+ .tALH_min = 2,
+ .tALS_min = 5,
+ .tAR_min = 25000,
+ .tCEA_max = 10,
+ .tCEH_min = 2,
+ .tCH_min = 2,
+ .tCHZ_max = 10,
+ .tCLH_min = 2,
+ .tCLR_min = 2,
+ .tCLS_min = 5,
+ .tCOH_min = 0,
+ .tCS_min = 7,
+ .tDH_min = 2,
+ .tDS_min = 4,
+ .tFEAT_max = 100,
+ .tIR_min = 1,
+ .tITC_max = 100,
+ .tRC_min = 10,
+ .tREA_max = 4,
+ .tREH_min = 3,
+ .tRHOH_min = 0,
+ .tRHW_min = 20,
+ .tRHZ_max = 20,
+ .tRLOH_min = 0,
+ .tRP_min = 5,
+ .tRST_max = 2500ULL,
+ .tWB_max = 20,
+ .tRR_min = 4,
+ .tWC_min = 10,
+ .tWH_min = 3,
+ .tWHR_min = 12,
+ .tWP_min = 5,
+ .tWW_min = 10,
+ },
+ /* Mode 1 */
+ {
+ .tADL_min = 10,
+ .tALH_min = 1,
+ .tALS_min = 25000,
+ .tAR_min = 1,
+ .tCEA_max = 45000,
+ .tCEH_min = 2,
+ .tCH_min = 1,
+ .tCHZ_max = 5,
+ .tCLH_min = 1,
+ .tCLR_min = 1,
+ .tCLS_min = 25000,
+ .tCOH_min = 15000,
+ .tCS_min = 35000,
+ .tDH_min = 1,
+ .tDS_min = 2,
+ .tFEAT_max = 100,
+ .tIR_min = 0,
+ .tITC_max = 100,
+ .tRC_min = 5,
+ .tREA_max = 3,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 10,
+ .tRHZ_max = 10,
+ .tRLOH_min = 0,
+ .tRP_min = 25000,
+ .tRR_min = 2,
+ .tRST_max = 5,
+ .tWB_max = 10,
+ .tWC_min = 45000,
+ .tWH_min = 15000,
+ .tWHR_min = 8,
+ .tWP_min = 25000,
+ .tWW_min = 10,
+ },
+ /* Mode 2 */
+ {
+ .tADL_min = 10,
+ .tALH_min = 1,
+ .tALS_min = 15000,
+ .tAR_min = 1,
+ .tCEA_max = 3,
+ .tCEH_min = 2,
+ .tCH_min = 1,
+ .tCHZ_max = 5,
+ .tCLH_min = 1,
+ .tCLR_min = 1,
+ .tCLS_min = 15000,
+ .tCOH_min = 15000,
+ .tCS_min = 25000,
+ .tDH_min = 5000,
+ .tDS_min = 15000,
+ .tFEAT_max = 100,
+ .tIR_min = 0,
+ .tITC_max = 100,
+ .tRC_min = 35000,
+ .tREA_max = 25000,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 10,
+ .tRHZ_max = 10,
+ .tRLOH_min = 0,
+ .tRR_min = 2,
+ .tRST_max = 5,
+ .tWB_max = 10,
+ .tRP_min = 17000,
+ .tWC_min = 35000,
+ .tWH_min = 15000,
+ .tWHR_min = 8,
+ .tWP_min = 17000,
+
[linux-sunxi] [RFC 09/11] sunxi/nand: Enable UBI and NAND commands
Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- board/sunxi/Kconfig| 8 +++- drivers/mtd/Makefile | 1 + include/configs/sunxi-common.h | 33 + 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index cf58d73..37bbd0f 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -269,17 +269,15 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. -config SPL_NAND_SUPPORT - bool SPL/NAND mode support +config NAND_SUNXI + bool NAND support depends on SPL default n ---help--- This enables support for booting from NAND internal memory. U-Boot SPL doesn't detect where is it load from, therefore this option is needed to properly load image from - flash. Option also disables MMC functionality on U-Boot due to - initialization errors encountered, when both controllers are - enabled. + flash. config USB0_VBUS_PIN string Vbus enable pin for usb0 (otg) diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 5467a95..124b0f9 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_FTSMC020) += ftsmc020.o obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o obj-$(CONFIG_ST_SMI) += st_smi.o +obj-$(CONFIG_MTD_UBI) += ubi/ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index cce0441..ec28c40 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -113,7 +113,7 @@ #endif /* 4MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 20)) /* * Miscellaneous configurable options @@ -326,10 +326,31 @@ extern int soft_i2c_gpio_scl; #define CONFIG_ENV_IS_NOWHERE #endif -#ifdef CONFIG_SPL_NAND_SUPPORT +#ifdef CONFIG_NAND_SUNXI +#ifndef CONFIG_NAND_SUNXI_GPC_PORTS +#error No NAND GPC ports defined, NAND unsupported +#endif /* CONFIG_NAND_SUNXI_GPC_PORTS */ #define CONFIG_NAND #define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_NAND_SUNXI +#define CONFIG_SYS_MAX_NAND_DEVICE 8 + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* Requirements for UBI */ +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_MTD_DEVICE + +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_MTD_PARTITIONS +/* +#define CONFIG_MTD_DEBUG +#define CONFIG_MTD_DEBUG_VERBOSE MTD_DEBUG_LEVEL3 +*/ #define CONFIG_CMD_SPL_WRITE_SIZE 0x000400 #define CONFIG_SYS_NAND_U_BOOT_OFFS0x008000 @@ -338,11 +359,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_NAND_SUNXI_ECC_STEP 1024 #define CONFIG_NAND_SUNXI_ECC_STRENGTH 40 #define CONFIG_NAND_SUNXI_ADDR_CYCLES 5 - -#ifndef CONFIG_NAND_SUNXI_GPC_PORTS -#error No NAND GPC ports defined, NAND unsupported -#endif -#endif /* CONFIG_SPL_NAND_SUPPORT */ +#endif /* CONFIG_NAND_SUNXI */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_CONSOLE_IS_IN_ENV -- 2.4.2 -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [RFC 06/11] mtd/nand: Add randomisation layer
Based on BBrezillons work, minus per-partition support. Changes to support
that would be quite invasive while it hasn't been solved yet for Linux.
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
drivers/mtd/nand/nand_base.c | 255 ++-
include/linux/mtd/nand.h | 96
2 files changed, 299 insertions(+), 52 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 83586cc..5196c0c 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1185,6 +1185,62 @@ EXPORT_SYMBOL(nand_lock);
#endif
/**
+ * nand_rnd_is_activ - check wether a region of a NAND page requires NAND
+ *randomizer to be disabled
+ * @mtd: mtd info
+ * @page: NAND page
+ * @column:offset within the page
+ * @len: len of the region
+ *
+ * Returns 1 if the randomizer should be enabled, 0 if not, or -ERR in case of
+ * error.
+ *
+ * In case of success len will contain the size of the region:
+ * - if the requested region fits in a NAND random region len will not change
+ * - else len will be replaced by the available length within the NAND random
+ *region
+ */
+int nand_rnd_is_activ(struct mtd_info *mtd, int page, int column, int *len)
+{
+ struct nand_chip *chip = mtd-priv;
+ struct nand_rnd_layout *layout = chip-rnd.layout;
+ struct nand_rndfree *range;
+ int ret = 1;
+ int tmp;
+ int i;
+
+ if (!len || *len 0 || column 0 ||
+ column + *len mtd-writesize + mtd-oobsize)
+ return -EINVAL;
+
+ if (layout) {
+ for (i = 0; i layout-nranges; i++) {
+ range = layout-ranges[i];
+ if (column + *len = range-offset) {
+ break;
+ } else if (column = range-offset + range-length) {
+ continue;
+ } else if (column range-offset) {
+ tmp = range-offset - column;
+ if (*len tmp)
+ *len = tmp;
+ break;
+ } else {
+ tmp = range-offset + range-length - column;
+ if (*len tmp)
+ *len = tmp;
+ ret = 0;
+ break;
+ }
+
+ }
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(nand_rnd_is_activ);
+
+/**
* nand_page_is_empty - check wether a NAND page contains only FFs
* @mtd: mtd info
* @data: data buffer
@@ -1329,9 +1385,13 @@ EXPORT_SYMBOL(nand_pst_create);
static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf, int oob_required, int page)
{
- chip-read_buf(mtd, buf, mtd-writesize);
- if (oob_required)
- chip-read_buf(mtd, chip-oob_poi, mtd-oobsize);
+ nand_rnd_config(mtd, page, 0, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, buf, mtd-writesize);
+ if (oob_required){
+ nand_rnd_config(mtd, page, mtd-writesize, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, chip-oob_poi, mtd-oobsize);
+ }
+ nand_rnd_config(mtd, -1, -1, NAND_RND_READ);
return 0;
}
@@ -1352,29 +1412,40 @@ static int nand_read_page_raw_syndrome(struct mtd_info
*mtd,
int eccsize = chip-ecc.size;
int eccbytes = chip-ecc.bytes;
uint8_t *oob = chip-oob_poi;
- int steps, size;
+ int steps, size, column = 0;
for (steps = chip-ecc.steps; steps 0; steps--) {
- chip-read_buf(mtd, buf, eccsize);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, buf, eccsize);
buf += eccsize;
+ column += eccsize;
if (chip-ecc.prepad) {
- chip-read_buf(mtd, oob, chip-ecc.prepad);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, oob, chip-ecc.prepad);
oob += chip-ecc.prepad;
+ column += chip-ecc.prepad;
}
- chip-read_buf(mtd, oob, eccbytes);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, oob, eccbytes);
oob += eccbytes;
+ column += eccbytes;
if (chip-ecc.postpad) {
- chip-read_buf(mtd, oob, chip-ecc.postpad);
+ nand_rnd_config(mtd, page, column, NAND_RND_READ);
+ nand_rnd_read_buf(mtd, oob, chip-ecc.postpad);
oob += chip-ecc.postpad;
+ column += chip-ecc.postpad;
[linux-sunxi] [RFC 01/11] mtd/nand: define struct nand_timings
From: yassin yassinjaf...@gmail.com
Signed-off-by: Roy Spliet r.spl...@ultimaker.com
---
include/linux/mtd/nand.h | 49
1 file changed, 49 insertions(+)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index bc927ec..b026110 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -1008,6 +1008,55 @@ static inline int jedec_feature(struct nand_chip *chip)
: 0;
}
+/**
+ * struct nand_sdr_timings - SDR NAND chip timings
+ *
+ * This struct defines the timing requirements of a SDR NAND chip.
+ * These informations can be found in every NAND datasheets and the timings
+ * meaning are described in the ONFI specifications:
+ * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
+ * Parameters)
+ *
+ * All these timings are expressed in picoseconds.
+ */
+
+struct nand_sdr_timings {
+ u32 tALH_min;
+ u32 tADL_min;
+ u32 tALS_min;
+ u32 tAR_min;
+ u32 tCEA_max;
+ u32 tCEH_min;
+ u32 tCH_min;
+ u32 tCHZ_max;
+ u32 tCLH_min;
+ u32 tCLR_min;
+ u32 tCLS_min;
+ u32 tCOH_min;
+ u32 tCS_min;
+ u32 tDH_min;
+ u32 tDS_min;
+ u32 tFEAT_max;
+ u32 tIR_min;
+ u32 tITC_max;
+ u32 tRC_min;
+ u32 tREA_max;
+ u32 tREH_min;
+ u32 tRHOH_min;
+ u32 tRHW_min;
+ u32 tRHZ_max;
+ u32 tRLOH_min;
+ u32 tRP_min;
+ u32 tRR_min;
+ u64 tRST_max;
+ u32 tWB_max;
+ u32 tWC_min;
+ u32 tWH_min;
+ u32 tWHR_min;
+ u32 tWP_min;
+ u32 tWW_min;
+};
+
#ifdef __UBOOT__
/* Standard NAND functions from nand_base.c */
void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
--
2.4.2
--
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[linux-sunxi] [RFC 11/11] mtd/nand: Sunxi NAND boot partition definitions
Based on the default layout of the android image used at least on Olimex Lime Signed-off-by: Roy Spliet r.spl...@ultimaker.com --- include/configs/sunxi-common.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ec28c40..b38f2f5 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -404,8 +404,15 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_NAND +#define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand , 0) +#else +#define BOOT_TARGET_DEVICES_NAND(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_NAND(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ @@ -441,6 +448,8 @@ extern int soft_i2c_gpio_scl; MEM_LAYOUT_ENV_SETTINGS \ fdtfile= CONFIG_DEFAULT_DEVICE_TREE .dtb\0 \ console=ttyS0,115200\0 \ + mtdids=nand0=mtd2\0 \ + mtdparts=mtdparts=mtd2:0xffc0@0x40(nand0_main)\0 \ BOOTENV #else /* ifndef CONFIG_SPL_BUILD */ -- 2.4.2 -- IMAGINE IT MAKE IT Meet us online at Twitter http://twitter.com/ultimaker, Facebook http://facebook.com/ultimaker, Google+ http://google.com/+Ultimaker www.ultimaker.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: Allwinner R8 module
Allwinner quoted me R8 at $4.80 alone and R8M module for $16 https:// olimex.wordpress.com/2015/06/05/how -to-get-in-the-news-tell-people-that-you-will-make-and-sell-something-which-cost-you-20-for-9/ … https://t.co/1fvaIL1k2J at this price it's better to use A33/H3 понеделник, 11 май 2015 г., 4:49:44 UTC+3, Jon Smirl написа: Does anyone have any info on the new Allwinner R8 module being used in the Chip $9 PC Kickstarter? It is A13+flash+RAM on module. I'd like to get a pin out and projected price. That module has to be really low cost if they are able to make a $9 computer out of it. -- Jon Smirl jons...@gmail.com javascript: -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: GMAC Reveice Clock Delay Chain value
m.silentcr...@gmail.com wrote: Sound interesting. How did your test runs work out? I found a couple of settings for the Lamobo R1 that might work slightly better than the default 3/0 TX/RX delay settings. But on Banana Pi and Olimex Lime2 the defaults (3/0 and 0/0) provided the best results. Since I'm still not knowing what I'm doing or whether my modifications to try to write to the right 3 bits and make this register accessible using CONFIG_GMAC_RX_DELAY do really work (I'm no coder) I simply gave up and skip Cubietruck and pcDuino3 Nano that I would've run through the same series of tests otherwise. Regards, Thomas -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: Allwinner R8 module
These marketing big events, takes their own live, and the seed for less than $10 development systems are here to stay. What is actually over is the market for $20+ for these systems. Whomever wants to be successful on this arena, must come with the $4.99 price tag. That is what will make the next big thing. :-) Yes, there will be a huge number of copy cats of this $9 system. Give it a year and you will see it. R On Friday, June 5, 2015 at 7:16:21 AM UTC-5, TsvetanUsunov wrote: Allwinner quoted me R8 at $4.80 alone and R8M module for $16 https:// olimex.wordpress.com/2015/06/05/how -to-get-in-the-news-tell-people-that-you-will-make-and-sell-something-which-cost-you-20-for-9/ … https://t.co/1fvaIL1k2J at this price it's better to use A33/H3 понеделник, 11 май 2015 г., 4:49:44 UTC+3, Jon Smirl написа: Does anyone have any info on the new Allwinner R8 module being used in the Chip $9 PC Kickstarter? It is A13+flash+RAM on module. I'd like to get a pin out and projected price. That module has to be really low cost if they are able to make a $9 computer out of it. -- Jon Smirl jons...@gmail.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] State of sunxi in Linux 4.1 LTS
Hi, now that Linux 4.1 has been picked to be the next LTS version of Linux [i], I'm wondering about the state of sunxi in the upcoming 4.1 release and longterm support. 1) It was mentioned in one of the emails on this list (I can't find it now), that not all the sunxi patches planned for 4.1 got merged and are now queued for 4.2 instead. Does this cause any issues in 4.1 for sunxi devices or is this merely a delay of features that are independent from the stuff that did get merged? 2) Given that sunxi support in mainline has already come a long way (at least for older SoCs like A10/A20 there's not much left to desire imho) and that there is not much work going into sunxi-3.4 anymore, I'm wondering if there is any interest in a new LTS kernel aimed for sunxi devices or recommended by the sunxi community. I'm not really sure how the current situation is: Is there an effort to ensure, that all important sunxi bugfixes that get applied to the mainline tree are also send to the stable and longterm releases (if they apply there)? If not (since it might be a lot of effort), how about picking a newer LTS tree, make it the recommended LTS version for sunxi devices and ensure that important bugfixes affecting that tree are being applied or backported to it. Or, if somebody wanted to invest even more effort, send backported patches including newer features to the LTSI project for the inclusion in their next LTSI kernel. Now, these are just random thoughts - not thought through (and to some extend I also lack the knowledge for that), but open for discussion. Regards and thanks for all the work being done in this community, Timo [i] https://twitter.com/LinuxLTSI/status/606321352815972354 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [u-boot] PMIC init failure on A33?
Hi, I'm seeing PMIC (AXP22x) init failures on my A33 boards. On my SinA33 it fails to set the RSB runtime address for the AXP223. As a result, the CPU is running at the default frequency of 408 MHz, instead of full speed. Wonder if anyone else is seeing these failures? Also I can't get my Q8H v1.5 A33 tablet's LCD screen to display anything. It's just completely white. Any ideas? Thanks ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 15/20] ARM: dts: sun7i: Enable USB DRC on Bananapi (BROKEN!)
Hi,
On 05-06-15 21:02, Hans de Goede wrote:
Enable the otg/drc usb controller on the Bananapi.
This is based on the fex file settings which claim that vbus-det is
PH5, but this does not work and the schematic shows that it is actually
connected to gpio1 of the axp209, so we cannot add otg support for the
bananapi until we get support for the axp209 gpio pins in the kernel.
Signed-off-by: Hans de Goede hdego...@redhat.com
This one obviously should not have been part of this set, please
ignore this one.
Thanks,
Hans
---
arch/arm/boot/dts/sun7i-a20-bananapi.dts | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 9f7b472..ce318bf 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -159,7 +159,25 @@
status = okay;
};
+otg_sram {
+ status = okay;
+};
+
pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = PH4;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_UP;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = PH5;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_DOWN;
+ };
+
mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
allwinner,pins = PH10;
allwinner,function = gpio_in;
@@ -182,6 +200,10 @@
};
};
+reg_usb0_vbus {
+ status = okay;
+};
+
reg_usb1_vbus {
status = okay;
};
@@ -216,7 +238,17 @@
status = okay;
};
+usb_otg {
+ dr_mode = otg;
+ status = okay;
+};
+
usbphy {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_id_detect_pin, usb0_vbus_detect_pin;
+ usb0_id_det-gpio = pio 7 4 GPIO_ACTIVE_HIGH; /* PH4 */
+ usb0_vbus_det-gpio = pio 7 5 GPIO_ACTIVE_HIGH; /* PH5 */
+ usb0_vbus-supply = reg_usb0_vbus;
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
status = okay;
--
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[linux-sunxi] ffmpeg with cedrus264 and Ubuntu 14 kernel 3.4
After a lot of struggling I've finally managed to run ubuntu on an optimusboard (Allwinner A80). I've compiled ffmpeg with cedarx support but when trying to transcode with the -c:v cedrus264 option it throws an error saying cannot allocate frame. There is a /dev/cedar_dev device node present and the libraries inside /usr/lib/vdpau are present too. I think it's a CMA problem but I'n not sure. I don't even know if the kernel has CMA enabled, there is no CMA mention inside the kernel arguments. Could someone please help me? -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 3/7] phy-sun4i-usb: Add support for the usb-phys on the sun8i-a33 SoC
The usb-phys on the sun8i-a33 SoC are mostly the same as sun8i-a23 but for
some reason (hw bug?) the phyctl register was moved to a different address
and is not initialized to 0 on reset.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
drivers/phy/phy-sun4i-usb.c| 39 --
2 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index f0c640a..5f48979 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -8,6 +8,7 @@ Required properties:
* allwinner,sun6i-a31-usb-phy
* allwinner,sun7i-a20-usb-phy
* allwinner,sun8i-a23-usb-phy
+ * allwinner,sun8i-a33-usb-phy
- reg : a list of offset + length pairs
- reg-names :
* phy_ctrl
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 7d96414..7d067ee 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -42,9 +42,10 @@
#define DRIVER_NAME sun4i-usb-phy
#define REG_ISCR 0x00
-#define REG_PHYCTL 0x04
+#define REG_PHYCTL_A10 0x04
#define REG_PHYBIST0x08
#define REG_PHYTUNE0x0c
+#define REG_PHYCTL_A33 0x10
#define PHYCTL_DATABIT(7)
@@ -92,6 +93,7 @@ struct sun4i_usb_phy_data {
struct mutex mutex;
int num_phys;
u32 disc_thresh;
+ bool has_a33_phyctl;
struct sun4i_usb_phy {
struct phy *phy;
void __iomem *pmu;
@@ -155,37 +157,46 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy
*phy, u32 addr, u32 data,
{
struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
u32 temp, usbc_bit = BIT(phy-index * 2);
+ void *phyctl;
int i;
mutex_lock(phy_data-mutex);
+ if (phy_data-has_a33_phyctl) {
+ phyctl = phy_data-base + REG_PHYCTL_A33;
+ /* A33 needs us to set phyctl to 0 explictly */
+ writel(0, phyctl);
+ } else {
+ phyctl = phy_data-base + REG_PHYCTL_A10;
+ }
+
for (i = 0; i len; i++) {
- temp = readl(phy_data-base + REG_PHYCTL);
+ temp = readl(phyctl);
/* clear the address portion */
temp = ~(0xff 8);
/* set the address */
temp |= ((addr + i) 8);
- writel(temp, phy_data-base + REG_PHYCTL);
+ writel(temp, phyctl);
/* set the data bit and clear usbc bit*/
- temp = readb(phy_data-base + REG_PHYCTL);
+ temp = readb(phyctl);
if (data 0x1)
temp |= PHYCTL_DATA;
else
temp = ~PHYCTL_DATA;
temp = ~usbc_bit;
- writeb(temp, phy_data-base + REG_PHYCTL);
+ writeb(temp, phyctl);
/* pulse usbc_bit */
- temp = readb(phy_data-base + REG_PHYCTL);
+ temp = readb(phyctl);
temp |= usbc_bit;
- writeb(temp, phy_data-base + REG_PHYCTL);
+ writeb(temp, phyctl);
- temp = readb(phy_data-base + REG_PHYCTL);
+ temp = readb(phyctl);
temp = ~usbc_bit;
- writeb(temp, phy_data-base + REG_PHYCTL);
+ writeb(temp, phyctl);
data = 1;
}
@@ -433,7 +444,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
data-extcon.dev.parent = dev;
if (of_device_is_compatible(np, allwinner,sun5i-a13-usb-phy) ||
- of_device_is_compatible(np, allwinner,sun8i-a23-usb-phy))
+ of_device_is_compatible(np, allwinner,sun8i-a23-usb-phy) ||
+ of_device_is_compatible(np, allwinner,sun8i-a33-usb-phy))
data-num_phys = 2;
else
data-num_phys = 3;
@@ -445,11 +457,15 @@ static int sun4i_usb_phy_probe(struct platform_device
*pdev)
data-disc_thresh = 3;
if (of_device_is_compatible(np, allwinner,sun6i-a31-usb-phy) ||
- of_device_is_compatible(np, allwinner,sun8i-a23-usb-phy))
+ of_device_is_compatible(np, allwinner,sun8i-a23-usb-phy) ||
+ of_device_is_compatible(np, allwinner,sun8i-a33-usb-phy))
dedicated_clocks = true;
else
dedicated_clocks = false;
+ if (of_device_is_compatible(np, allwinner,sun8i-a33-usb-phy))
+ data-has_a33_phyctl = true;
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, phy_ctrl);
data-base = devm_ioremap_resource(dev, res);
if (IS_ERR(data-base))
@@ -586,6 +602,7 @@ static const struct
[linux-sunxi] [PATCH 7/7] musb: sunxi: Add support for musb controller in A33 SoC
The A33 SoC uses the same musb controller as found on the A31 and later,
but allwinner has removed the configdata register, this commit adds special
handling for this.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt | 3 ++-
drivers/usb/musb/sunxi.c | 15 +++
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
index c5ef893..fff87c8 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
@@ -2,7 +2,8 @@ Allwinner sun4i A10 musb DRC/OTG controller
---
Required properties:
- - compatible : allwinner,sun4i-a10-musb or allwinner,sun6i-a31-musb
+ - compatible : allwinner,sun4i-a10-musb, allwinner,sun6i-a31-musb
+ or allwinner,sun8i-a33-musb
- reg : mmio address range of the musb controller
- clocks : clock specifier for the musb controller ahb gate clock
- reset : reset specifier for the ahb reset (A31 and newer only)
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index 8eccbb7..b0fdd83 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -73,6 +73,7 @@
#define SUNXI_MUSB_FL_PHY_ON 4
#define SUNXI_MUSB_FL_HAS_SRAM 5
#define SUNXI_MUSB_FL_HAS_RESET6
+#define SUNXI_MUSB_FL_NO_CONFIGDATA7
/* Our read/write methods need access and do not get passed in a musb ref :| */
struct musb *sunxi_musb;
@@ -370,6 +371,8 @@ static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset)
{
+ struct sunxi_glue *glue;
+
if (addr == sunxi_musb-mregs) {
/* generic control or fifo control reg access */
switch (offset) {
@@ -392,6 +395,12 @@ static u8 sunxi_musb_readb(const void __iomem *addr,
unsigned offset)
case MUSB_RXFIFOSZ:
return readb(addr + SUNXI_MUSB_RXFIFOSZ);
case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
+ glue = dev_get_drvdata(sunxi_musb-controller-parent);
+ /* A33 saves a reg, and we get to hardcode this */
+ if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
+glue-flags))
+ return 0xde;
+
return readb(addr + SUNXI_MUSB_CONFIGDATA);
/* Offset for these is fixed by sunxi_musb_busctl_offset() */
case SUNXI_MUSB_TXFUNCADDR:
@@ -636,6 +645,11 @@ static int sunxi_musb_probe(struct platform_device *pdev)
if (of_device_is_compatible(np, allwinner,sun6i-a31-musb))
set_bit(SUNXI_MUSB_FL_HAS_RESET, glue-flags);
+ if (of_device_is_compatible(np, allwinner,sun8i-a33-musb)) {
+ set_bit(SUNXI_MUSB_FL_HAS_RESET, glue-flags);
+ set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, glue-flags);
+ }
+
glue-clk = devm_clk_get(pdev-dev, NULL);
if (IS_ERR(glue-clk)) {
dev_err(pdev-dev, Error getting clock: %ld\n,
@@ -716,6 +730,7 @@ static int sunxi_musb_remove(struct platform_device *pdev)
static const struct of_device_id sunxi_musb_match[] = {
{ .compatible = allwinner,sun4i-a10-musb, },
{ .compatible = allwinner,sun6i-a31-musb, },
+ { .compatible = allwinner,sun8i-a33-musb, },
{}
};
--
2.4.2
--
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[linux-sunxi] [PATCH 0/7] musb-sunxi / phy-sun4i-usb: Add suppor for new SoCs
Hi Felipe and Kishon, This musb-sunxi / phy-sun4i-usb series adds supports for the otg and host usb-phys found on newer sunxi SoCs and for the musb ip found on newer sunxi SoCs. This series sits on top of the 2 still outstanding musb-sunxi / phy-sun4i-usb patches. These patches (and the 2 still outstanding patches) have no compile time dependecies on each other. So they can be merged through your trees seperately, or they can all go through one tree, depending on what you prefer. Regards, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 4/7] phy-sun4i-usb: Add support for boards with broken Vusb-detection
On some boards we cannot detect the presence of an external Vusb, because
e.g. the 5V of the otg connector is directly connected to the 5V of the board,
and thus is always high.
This commit adds support for using such boards by only looking at the
id-detection pin.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/phy/phy-sun4i-usb.c | 44
1 file changed, 36 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 7d067ee..4981041 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -22,6 +22,7 @@
*/
#include linux/clk.h
+#include linux/delay.h
#include linux/err.h
#include linux/extcon.h
#include linux/io.h
@@ -312,7 +313,7 @@ static int sun4i_usb_phy_power_on(struct phy *_phy)
phy-regulator_on = true;
/* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */
- if (phy-index == 0 data-phy0_poll)
+ if (phy-index == 0 data-vbus_det_gpio data-phy0_poll)
mod_delayed_work(system_wq, data-detect, DEBOUNCE_TIME);
return 0;
@@ -333,7 +334,7 @@ static int sun4i_usb_phy_power_off(struct phy *_phy)
* phy0 vbus typically slowly discharges, sometimes this causes the
* Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan.
*/
- if (phy-index == 0 !data-phy0_poll)
+ if (phy-index == 0 data-vbus_det_gpio !data-phy0_poll)
mod_delayed_work(system_wq, data-detect, POLL_TIME);
return 0;
@@ -362,7 +363,10 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct
work_struct *work)
int id_det, vbus_det, id_notify = 0, vbus_notify = 0;
id_det = gpiod_get_value_cansleep(data-id_det_gpio);
- vbus_det = gpiod_get_value_cansleep(data-vbus_det_gpio);
+ if (data-vbus_det_gpio)
+ vbus_det = gpiod_get_value_cansleep(data-vbus_det_gpio);
+ else
+ vbus_det = 1; /* Report vbus as high */
mutex_lock(phy0-mutex);
@@ -372,6 +376,16 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct
work_struct *work)
}
if (id_det != data-id_det) {
+ /*
+* When a host cable (id == 0) gets plugged in on systems
+* without vbus detection report vbus low for long enough for
+* the musb-ip to end the current device session.
+*/
+ if (!data-vbus_det_gpio id_det == 0) {
+ sun4i_usb_phy0_set_vbus_detect(phy0, 0);
+ msleep(200);
+ sun4i_usb_phy0_set_vbus_detect(phy0, 1);
+ }
sun4i_usb_phy0_set_id_detect(phy0, id_det);
data-id_det = id_det;
id_notify = 1;
@@ -385,10 +399,23 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct
work_struct *work)
mutex_unlock(phy0-mutex);
- if (id_notify)
+ if (id_notify) {
extcon_set_cable_state(data-extcon,
extcon_cable_name[EXTCON_USB_HOST],
!id_det);
+ /*
+* When a host cable gets unplugged (id == 1) on systems
+* without vbus detection report vbus low for long enough to
+* the musb-ip to end the current host session.
+*/
+ if (!data-vbus_det_gpio id_det == 1) {
+ mutex_lock(phy0-mutex);
+ sun4i_usb_phy0_set_vbus_detect(phy0, 0);
+ msleep(1000);
+ sun4i_usb_phy0_set_vbus_detect(phy0, 1);
+ mutex_unlock(phy0-mutex);
+ }
+ }
if (vbus_notify)
extcon_set_cable_state(data-extcon,
@@ -485,9 +512,9 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
data-vbus_det_gpio = NULL;
}
- /* We either want both gpio pins or neither (when in host mode) */
- if (!data-id_det_gpio != !data-vbus_det_gpio) {
- dev_err(dev, failed to get id or vbus detect pin\n);
+ /* vbus_det without id_det makes no sense, and is not supported */
+ if (data-vbus_det_gpio !data-id_det_gpio) {
+ dev_err(dev, usb0_id_det missing or invalid\n);
return -ENODEV;
}
@@ -550,7 +577,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
data-id_det_irq = gpiod_to_irq(data-id_det_gpio);
data-vbus_det_irq = gpiod_to_irq(data-vbus_det_gpio);
- if (data-id_det_irq 0 || data-vbus_det_irq 0)
+ if ((data-id_det_gpio data-id_det_irq 0) ||
+ (data-vbus_det_gpio data-vbus_det_irq 0))
data-phy0_poll = true;
if (data-id_det_irq = 0) {
--
2.4.2
--
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[linux-sunxi] [PATCH 2/7] phy-sun4i-usb: Add support for the usb-phys on the sun8i-a23 SoC
The usb-phys on the sun8i-a23 SoC have the same setup wrt clocks as on the
sun6i-a31 SoC, but there are only 2 instead of 3 like on the sun5i-a13 SoC.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 2 ++
drivers/phy/phy-sun4i-usb.c | 7 +--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 557fa99..f0c640a 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -7,6 +7,7 @@ Required properties:
* allwinner,sun5i-a13-usb-phy
* allwinner,sun6i-a31-usb-phy
* allwinner,sun7i-a20-usb-phy
+ * allwinner,sun8i-a23-usb-phy
- reg : a list of offset + length pairs
- reg-names :
* phy_ctrl
@@ -17,6 +18,7 @@ Required properties:
- clock-names :
* usb_phy for sun4i, sun5i or sun7i
* usb0_phy, usb1_phy and usb2_phy for sun6i
+ * usb0_phy, usb1_phy for sun8i
- resets : a list of phandle + reset specifier pairs
- reset-names :
* usb0_reset
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 0df1c4f..7d96414 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -432,7 +432,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
data-extcon.supported_cable = data-extcon_cable_names;
data-extcon.dev.parent = dev;
- if (of_device_is_compatible(np, allwinner,sun5i-a13-usb-phy))
+ if (of_device_is_compatible(np, allwinner,sun5i-a13-usb-phy) ||
+ of_device_is_compatible(np, allwinner,sun8i-a23-usb-phy))
data-num_phys = 2;
else
data-num_phys = 3;
@@ -443,7 +444,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
else
data-disc_thresh = 3;
- if (of_device_is_compatible(np, allwinner,sun6i-a31-usb-phy))
+ if (of_device_is_compatible(np, allwinner,sun6i-a31-usb-phy) ||
+ of_device_is_compatible(np, allwinner,sun8i-a23-usb-phy))
dedicated_clocks = true;
else
dedicated_clocks = false;
@@ -583,6 +585,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] =
{
{ .compatible = allwinner,sun5i-a13-usb-phy },
{ .compatible = allwinner,sun6i-a31-usb-phy },
{ .compatible = allwinner,sun7i-a20-usb-phy },
+ { .compatible = allwinner,sun8i-a23-usb-phy },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.4.2
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[linux-sunxi] [PATCH 1/7] phy-sun4i-usb: Swap check for disconnect threshold
Before this commit the code for determining the disconnect threshold was checking for allwinner,sun4i-a10-usb-phy or allwinner,sun6i-a31-usb-phy assuming that those where the exception and then newer SoCs would use a disconnect threshold of 2 like sun7i does. But it turns out that newer SoCs use a disconnect threshold of 3 and sun5i and sun7i are the exceptions, so check for those instead. Here are the settings from the various Allwinner SDK sources: sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); Note this commit makes no functional changes as currently we only support sun4i - sun7i. Signed-off-by: Hans de Goede hdego...@redhat.com --- drivers/phy/phy-sun4i-usb.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c index b45d707..0df1c4f 100644 --- a/drivers/phy/phy-sun4i-usb.c +++ b/drivers/phy/phy-sun4i-usb.c @@ -437,11 +437,11 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev) else data-num_phys = 3; - if (of_device_is_compatible(np, allwinner,sun4i-a10-usb-phy) || - of_device_is_compatible(np, allwinner,sun6i-a31-usb-phy)) - data-disc_thresh = 3; - else + if (of_device_is_compatible(np, allwinner,sun5i-a13-usb-phy) || + of_device_is_compatible(np, allwinner,sun7i-a20-usb-phy)) data-disc_thresh = 2; + else + data-disc_thresh = 3; if (of_device_is_compatible(np, allwinner,sun6i-a31-usb-phy)) dedicated_clocks = true; -- 2.4.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 11/20] ARM: dts: sun6i: Enable USB DRC on the Mele A1000G quad
The Mele A1000G-quad has an usb to sata bridge connected to its otg
controller, this commit enables support for this. Since the otg is
hardwired to the sata bridge it gets enabled in host only mode.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
index 4404f37..4dd70cc 100644
--- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
+++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
@@ -143,6 +143,11 @@
status = okay;
};
+usb_otg {
+ dr_mode = host;
+ status = okay;
+};
+
usbphy {
usb1_vbus-supply = reg_usb1_vbus;
status = okay;
--
2.4.2
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[linux-sunxi] [PATCH 10/20] ARM: dts: sun5i: Enable USB DRC on UTOO P66
Enable the OTG controller on the UTOO P66 tablet.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
index 514f159..3043aac 100644
--- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
+++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
@@ -153,6 +153,10 @@
};
};
+otg_sram {
+ status = okay;
+};
+
pio {
mmc0_cd_pin_p66: mmc0_cd_pin@0 {
allwinner,pins = PG0;
@@ -161,6 +165,20 @@
allwinner,pull = SUN4I_PINCTRL_PULL_UP;
};
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = PG1;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_DOWN;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = PG2;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_UP;
+ };
+
i2c_lcd_pins: i2c_lcd_pin@0 {
allwinner,pins = PG10, PG12;
allwinner,function = gpio_out;
@@ -219,7 +237,16 @@
status = okay;
};
+usb_otg {
+ dr_mode = otg;
+ status = okay;
+};
+
usbphy {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_id_detect_pin, usb0_vbus_detect_pin;
+ usb0_id_det-gpio = pio 6 2 GPIO_ACTIVE_HIGH; /* PG2 */
+ usb0_vbus_det-gpio = pio 6 1 GPIO_ACTIVE_HIGH; /* PG1 */
usb0_vbus-supply = reg_usb0_vbus;
usb1_vbus-supply = reg_ldo3;
status = okay;
--
2.4.2
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[linux-sunxi] [PATCH 12/20] ARM: dts: sun7i: Enable USB DRC on Cubietruck
From: Roman Byshko rbys...@gmail.com
Enable the otg/drc usb controller on the cubietruck.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 4611e2f..839d79d 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -199,6 +199,10 @@
status = okay;
};
+otg_sram {
+ status = okay;
+};
+
pio {
vmmc3_pin_cubietruck: vmmc3_pin@0 {
allwinner,pins = PH9;
@@ -227,6 +231,20 @@
allwinner,drive = SUN4I_PINCTRL_10_MA;
allwinner,pull = SUN4I_PINCTRL_NO_PULL;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = PH19;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_NO_PULL;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = PH22;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_NO_PULL;
+ };
};
pwm {
@@ -288,7 +306,16 @@
status = okay;
};
+usb_otg {
+ dr_mode = otg;
+ status = okay;
+};
+
usbphy {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_id_detect_pin, usb0_vbus_detect_pin;
+ usb0_id_det-gpios = pio 7 19 GPIO_ACTIVE_HIGH; /* PH19 */
+ usb0_vbus_det-gpios = pio 7 22 GPIO_ACTIVE_HIGH; /* PH22 */
usb0_vbus-supply = reg_usb0_vbus;
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
--
2.4.2
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[linux-sunxi] [PATCH 15/20] ARM: dts: sun7i: Enable USB DRC on Bananapi (BROKEN!)
Enable the otg/drc usb controller on the Bananapi.
This is based on the fex file settings which claim that vbus-det is
PH5, but this does not work and the schematic shows that it is actually
connected to gpio1 of the axp209, so we cannot add otg support for the
bananapi until we get support for the axp209 gpio pins in the kernel.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-bananapi.dts | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 9f7b472..ce318bf 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -159,7 +159,25 @@
status = okay;
};
+otg_sram {
+ status = okay;
+};
+
pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = PH4;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_UP;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = PH5;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_DOWN;
+ };
+
mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
allwinner,pins = PH10;
allwinner,function = gpio_in;
@@ -182,6 +200,10 @@
};
};
+reg_usb0_vbus {
+ status = okay;
+};
+
reg_usb1_vbus {
status = okay;
};
@@ -216,7 +238,17 @@
status = okay;
};
+usb_otg {
+ dr_mode = otg;
+ status = okay;
+};
+
usbphy {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_id_detect_pin, usb0_vbus_detect_pin;
+ usb0_id_det-gpio = pio 7 4 GPIO_ACTIVE_HIGH; /* PH4 */
+ usb0_vbus_det-gpio = pio 7 5 GPIO_ACTIVE_HIGH; /* PH5 */
+ usb0_vbus-supply = reg_usb0_vbus;
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
status = okay;
--
2.4.2
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[linux-sunxi] [PATCH 14/20] ARM: dts: sun7i: Enable USB DRC on A20-OLinuxIno-Micro
Enable the otg/drc usb controller on the A20-OLinuxIno-Micro.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 32 +
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index 00f8f25..c5d70ca 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -215,6 +215,10 @@
status = okay;
};
+otg_sram {
+ status = okay;
+};
+
pio {
mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
allwinner,pins = PH11;
@@ -229,12 +233,30 @@
allwinner,drive = SUN4I_PINCTRL_20_MA;
allwinner,pull = SUN4I_PINCTRL_NO_PULL;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = PH4;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_UP;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = PH5;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_DOWN;
+ };
};
reg_ahci_5v {
status = okay;
};
+reg_usb0_vbus {
+ status = okay;
+};
+
reg_usb1_vbus {
status = okay;
};
@@ -275,7 +297,17 @@
status = okay;
};
+usb_otg {
+ dr_mode = otg;
+ status = okay;
+};
+
usbphy {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_id_detect_pin, usb0_vbus_detect_pin;
+ usb0_id_det-gpio = pio 7 4 GPIO_ACTIVE_HIGH; /* PH4 */
+ usb0_vbus_det-gpio = pio 7 5 GPIO_ACTIVE_HIGH; /* PH5 */
+ usb0_vbus-supply = reg_usb0_vbus;
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
status = okay;
--
2.4.2
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[linux-sunxi] [PATCH 19/20] ARM: dts: sun8i: Enable USB host on GA10H-A33 tablets
The GA10H tablets not only have an otg connector, but also a normal
usb host connector, enabled support for this.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
index 7520e06..1aefc67 100644
--- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
+++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
@@ -61,6 +61,10 @@
};
};
+ehci0 {
+ status = okay;
+};
+
i2c0 {
pinctrl-names = default;
pinctrl-0 = i2c0_pins_a;
@@ -109,6 +113,10 @@
status = okay;
};
+ohci0 {
+ status = okay;
+};
+
pio {
mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
allwinner,pins = PB4;
--
2.4.2
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[linux-sunxi] [PATCH 09/20] ARM: dts: sun4i: Enable USB DRC on the Cubieboard
Enable the otg/drc usb controller on the Cubieboard. Note that the
5V of the otg is directly connected to the general 5V, so we only use
the id pin.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 9afb4e0..046a84d 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -155,6 +155,10 @@
status = okay;
};
+otg_sram {
+ status = okay;
+};
+
pio {
led_pins_cubieboard: led_pins@0 {
allwinner,pins = PH20, PH21;
@@ -162,6 +166,13 @@
allwinner,drive = SUN4I_PINCTRL_20_MA;
allwinner,pull = SUN4I_PINCTRL_NO_PULL;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = PH4;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_UP;
+ };
};
reg_ahci_5v {
@@ -216,7 +227,15 @@
status = okay;
};
+usb_otg {
+ dr_mode = otg;
+ status = okay;
+};
+
usbphy {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_id_detect_pin;
+ usb0_id_det-gpio = pio 7 4 GPIO_ACTIVE_HIGH; /* PH4 */
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
status = okay;
--
2.4.2
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[linux-sunxi] [PATCH 00/20] ARM: dts: Add USB and OTG related nodes and enable on various boards
Hi Maxime, Here is a patch-set with all the otg / sun8i-usb-host related dts patches I've accumulated. These are intended for 4.3, and go hand in hand with the outstanding musb-sunxi / phy-sun4i-usb patches, which I expect to be merged as is for 4.3 . Regards, Hans -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 04/20] ARM: dts: sun7i: Add USB Dual Role Controller
From: Roman Byshko rbys...@gmail.com
Add a node for the otg/drc usb controller to sun7i-a20.dtsi
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 6a63f30..7549f1b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -699,6 +699,18 @@
#size-cells = 0;
};
+ usb_otg: usb@01c13000 {
+ compatible = allwinner,sun4i-a10-musb;
+ reg = 0x01c13000 0x0400;
+ clocks = ahb_gates 0;
+ interrupts = GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = mc;
+ phys = usbphy 0;
+ phy-names = usb;
+ allwinner,sram = otg_sram 1;
+ status = disabled;
+ };
+
usbphy: phy@01c13400 {
#phy-cells = 1;
compatible = allwinner,sun7i-a20-usb-phy;
--
2.4.2
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[linux-sunxi] [PATCH 06/20] ARM: dts: sun8i: Add A33 usb-phy and otg nodes
Note these are added to the sun8i-a33.dtsi file rather then to the shared
sun8i-a23-a33.dtsi file as both the phy and the otg controller on the a33
are slightly different.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a33.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 85ee080..da01b76 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -80,6 +80,38 @@
clock-output-names = mbus;
};
};
+
+ soc@01c0 {
+ usb_otg: usb@01c19000 {
+ compatible = allwinner,sun8i-a33-musb;
+ reg = 0x01c19000 0x0400;
+ clocks = ahb1_gates 24;
+ resets = ahb1_rst 24;
+ interrupts = GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = mc;
+ phys = usbphy 0;
+ phy-names = usb;
+ status = disabled;
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = allwinner,sun8i-a33-usb-phy;
+ reg = 0x01c19400 0x14,
+ 0x01c1a800 0x4;
+ reg-names = phy_ctrl,
+ pmu1;
+ clocks = usb_clk 8,
+usb_clk 9;
+ clock-names = usb0_phy,
+ usb1_phy;
+ resets = usb_clk 0,
+usb_clk 1;
+ reset-names = usb0_reset,
+ usb1_reset;
+ status = disabled;
+ #phy-cells = 1;
+ };
+ };
};
pio {
--
2.4.2
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[linux-sunxi] [PATCH 07/20] ARM: dts: sun8i: Add support for USB controllers on A23/A33
From: Chen-Yu Tsai w...@csie.org
A23/A33 has one pair of EHCI/OHCI USB controllers. There are 2 USB PHYs,
one for the USB OTG controller, one for the EHCI/OHCI pair. The latter
may also support HSIC, though none of the available boards utilize this,
so this is not supported yet.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7abd0ae..b9e4d56 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -332,6 +332,28 @@
#size-cells = 0;
};
+ ehci0: usb@01c1a000 {
+ compatible = allwinner,sun8i-a23-ehci, generic-ehci;
+ reg = 0x01c1a000 0x100;
+ interrupts = GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH;
+ clocks = ahb1_gates 26;
+ resets = ahb1_rst 26;
+ phys = usbphy 1;
+ phy-names = usb;
+ status = disabled;
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = allwinner,sun8i-a23-ohci, generic-ohci;
+ reg = 0x01c1a400 0x100;
+ interrupts = GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH;
+ clocks = ahb1_gates 29, usb_clk 16;
+ resets = ahb1_rst 29;
+ phys = usbphy 1;
+ phy-names = usb;
+ status = disabled;
+ };
+
pio: pinctrl@01c20800 {
/* compatible gets set in SoC specific dtsi file */
reg = 0x01c20800 0x400;
--
2.4.2
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[linux-sunxi] [PATCH 08/20] ARM: dts: sun4i: Enable USB DRC on Chuwi V7 CW0825
Enable the otg/drc usb controller on the Chuwi V7 CW0825 tablet.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 34 +
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
index 5878a0b..1430568 100644
--- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
@@ -114,6 +114,30 @@
status = okay;
};
+otg_sram {
+ status = okay;
+};
+
+pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = PH4;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_UP;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = PH5;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_DOWN;
+ };
+};
+
+reg_usb0_vbus {
+ status = okay;
+};
+
reg_usb2_vbus {
status = okay;
};
@@ -124,7 +148,17 @@
status = okay;
};
+usb_otg {
+ dr_mode = otg;
+ status = okay;
+};
+
usbphy {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_id_detect_pin, usb0_vbus_detect_pin;
+ usb0_id_det-gpio = pio 7 4 GPIO_ACTIVE_HIGH; /* PH4 */
+ usb0_vbus_det-gpio = pio 7 5 GPIO_ACTIVE_HIGH; /* PH5 */
+ usb0_vbus-supply = reg_usb0_vbus;
usb2_vbus-supply = reg_usb2_vbus;
status = okay;
};
--
2.4.2
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[linux-sunxi] [PATCH 03/20] ARM: dts: sun6i: Add USB Dual Role Controller
Add a node for the otg/drc usb controller to sun6i-a31.dtsi.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 008047a..5bc6933 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -512,6 +512,18 @@
#size-cells = 0;
};
+ usb_otg: usb@01c19000 {
+ compatible = allwinner,sun6i-a31-musb;
+ reg = 0x01c19000 0x0400;
+ clocks = ahb1_gates 24;
+ resets = ahb1_rst 24;
+ interrupts = GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = mc;
+ phys = usbphy 0;
+ phy-names = usb;
+ status = disabled;
+ };
+
usbphy: phy@01c19400 {
compatible = allwinner,sun6i-a31-usb-phy;
reg = 0x01c19400 0x10,
--
2.4.2
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[linux-sunxi] [PATCH 05/20] ARM: dts: sun8i: Add A23 usb-phy and otg nodes
Note these are added to the sun8i-a23.dtsi file rather then to the shared
sun8i-a23-a33.dtsi file as both the phy and the otg controller on the a33
are slightly different.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a23.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 8698f7a..60fde9e 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -58,6 +58,38 @@
clock-output-names = mbus;
};
};
+
+ soc@01c0 {
+ usb_otg: usb@01c19000 {
+ compatible = allwinner,sun6i-a31-musb;
+ reg = 0x01c19000 0x0400;
+ clocks = ahb1_gates 24;
+ resets = ahb1_rst 24;
+ interrupts = GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH;
+ interrupt-names = mc;
+ phys = usbphy 0;
+ phy-names = usb;
+ status = disabled;
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = allwinner,sun8i-a23-usb-phy;
+ reg = 0x01c19400 0x10,
+ 0x01c1a800 0x4;
+ reg-names = phy_ctrl,
+ pmu1;
+ clocks = usb_clk 8,
+usb_clk 9;
+ clock-names = usb0_phy,
+ usb1_phy;
+ resets = usb_clk 0,
+usb_clk 1;
+ reset-names = usb0_reset,
+ usb1_reset;
+ status = disabled;
+ #phy-cells = 1;
+ };
+ };
};
pio {
--
2.4.2
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[linux-sunxi] [PATCH 02/20] ARM: dts: sun5i: Add USB Dual Role Controller
Add a node for the otg/drc usb controller to sun5i-a1*.dtsi.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun5i.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 54b0978..53d3ead 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -416,6 +416,18 @@
#size-cells = 0;
};
+ usb_otg: usb@01c13000 {
+ compatible = allwinner,sun4i-a10-musb;
+ reg = 0x01c13000 0x0400;
+ clocks = ahb_gates 0;
+ interrupts = 38;
+ interrupt-names = mc;
+ phys = usbphy 0;
+ phy-names = usb;
+ allwinner,sram = otg_sram 1;
+ status = disabled;
+ };
+
usbphy: phy@01c13400 {
#phy-cells = 1;
compatible = allwinner,sun5i-a13-usb-phy;
--
2.4.2
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[linux-sunxi] [PATCH 5/7] musb: sunxi: Remove special MUSB_SUN4I flag for clearing ep0 addr on disconnect
We can cleanly handle this inside the sunxi glue, instead of adding special
casing to the core, but setting ep0 addr to 0 on a reset interrupt.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/usb/musb/musb_core.h| 1 -
drivers/usb/musb/musb_gadget.c | 6 --
drivers/usb/musb/musb_virthub.c | 6 --
drivers/usb/musb/sunxi.c| 8 +++-
4 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 30a3123..b1cb2c3 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -169,7 +169,6 @@ struct musb_io;
*/
struct musb_platform_ops {
-#define MUSB_SUN4I BIT(7)
#define MUSB_DMA_UX500 BIT(6)
#define MUSB_DMA_CPPI41BIT(5)
#define MUSB_DMA_CPPI BIT(4)
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index ec2e908..4c481cd 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -2003,12 +2003,6 @@ void musb_g_disconnect(struct musb *musb)
spin_lock(musb-lock);
}
- /* On sunxi ep0 FADDR must be 0 when (re)entering peripheral mode */
- if (musb-io.quirks MUSB_SUN4I) {
- musb_ep_select(musb-mregs, 0);
- musb_writeb(musb-mregs, MUSB_FADDR, 0);
- }
-
switch (musb-xceiv-otg-state) {
default:
dev_dbg(musb-controller, Unhandled disconnect %s, setting
a_idle\n,
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index fe98623..30842bc 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -226,12 +226,6 @@ void musb_root_disconnect(struct musb *musb)
usb_hcd_poll_rh_status(musb-hcd);
musb-is_active = 0;
- /* On sunxi ep0 FADDR must be 0 when (re)entering peripheral mode */
- if (musb-io.quirks MUSB_SUN4I) {
- musb_ep_select(musb-mregs, 0);
- musb_writeb(musb-mregs, MUSB_FADDR, 0);
- }
-
switch (musb-xceiv-otg-state) {
case OTG_STATE_A_SUSPEND:
if (otg-host-b_hnp_enable) {
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index 5db882f..8fc39af 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -183,6 +183,12 @@ static irqreturn_t sunxi_musb_interrupt(int irq, void
*__hci)
musb-int_usb |= MUSB_INTR_DISCONNECT;
}
+ if ((musb-int_usb MUSB_INTR_RESET) !is_host_active(musb)) {
+ /* ep0 FADDR must be 0 when (re)entering peripheral mode */
+ musb_ep_select(musb-mregs, 0);
+ musb_writeb(musb-mregs, MUSB_FADDR, 0);
+ }
+
musb-int_tx = readw(musb-mregs + SUNXI_MUSB_INTRTX);
if (musb-int_tx)
writew(musb-int_tx, musb-mregs + SUNXI_MUSB_INTRTX);
@@ -519,7 +525,7 @@ static void sunxi_musb_writew(void __iomem *addr, unsigned
offset, u16 data)
}
static const struct musb_platform_ops sunxi_musb_ops = {
- .quirks = MUSB_INDEXED_EP | MUSB_SUN4I,
+ .quirks = MUSB_INDEXED_EP,
.init = sunxi_musb_init,
.exit = sunxi_musb_exit,
.enable = sunxi_musb_enable,
--
2.4.2
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[linux-sunxi] [PATCH 20/20] ARM: dts: sun8i: sina33: Enable USB hosts
From: Chen-Yu Tsai w...@csie.org
The Sina33 SDK board exposes the EHCI/OHCI USB host pair.
VBUS for this port is always on and non-controllable.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 5788c29..1d5390d 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -63,6 +63,10 @@
};
};
+ehci0 {
+ status = okay;
+};
+
lradc {
vref-supply = reg_vcc3v0;
status = okay;
@@ -113,6 +117,10 @@
allwinner,pull = SUN4I_PINCTRL_PULL_UP;
};
+ohci0 {
+ status = okay;
+};
+
pio {
mmc0_cd_pin_sina33: mmc0_cd_pin@0 {
allwinner,pins = PB4;
@@ -127,3 +135,8 @@
pinctrl-0 = uart0_pins_b;
status = okay;
};
+
+usbphy {
+ status = okay;
+ usb1_vbus-supply = reg_vcc5v0; /* USB1 VBUS is always on */
+};
--
2.4.2
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[linux-sunxi] [PATCH 18/20] ARM: dts: sun8i: Enable USB DRC on GA10H-A33 tablets
Enable the otg controller on GA10H-A33 tablets, for now it is enabled
in host-only mode, because true OTG support requires support for
detecting and enabling Vbus through the axp221 pmic.
For this to work the Vbus on the port must be enabled by u-boot,
or a powered hub must be used.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
index 8667033..7520e06 100644
--- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
+++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
@@ -123,3 +123,12 @@
pinctrl-0 = r_uart_pins_a;
status = okay;
};
+
+usb_otg {
+ dr_mode = host;
+ status = okay;
+};
+
+usbphy {
+ status = okay;
+};
--
2.4.2
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[linux-sunxi] [PATCH 13/20] ARM: dts: sun7i: Enable USB DRC on A20-OLinuxIno-Lime
Enable the otg/drc usb controller on the A20-OLinuxIno-Lime.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 32 ++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 769726d..0423708 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -135,6 +135,10 @@
status = okay;
};
+otg_sram {
+ status = okay;
+};
+
pio {
ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
allwinner,pins = PC3;
@@ -149,6 +153,20 @@
allwinner,drive = SUN4I_PINCTRL_20_MA;
allwinner,pull = SUN4I_PINCTRL_NO_PULL;
};
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = PH4;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_UP;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = PH5;
+ allwinner,function = gpio_in;
+ allwinner,drive = SUN4I_PINCTRL_10_MA;
+ allwinner,pull = SUN4I_PINCTRL_PULL_DOWN;
+ };
};
reg_ahci_5v {
@@ -157,6 +175,10 @@
status = okay;
};
+reg_usb0_vbus {
+ status = okay;
+};
+
reg_usb1_vbus {
status = okay;
};
@@ -171,7 +193,17 @@
status = okay;
};
+usb_otg {
+ dr_mode = otg;
+ status = okay;
+};
+
usbphy {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_id_detect_pin, usb0_vbus_detect_pin;
+ usb0_id_det-gpio = pio 7 4 GPIO_ACTIVE_HIGH; /* PH4 */
+ usb0_vbus_det-gpio = pio 7 5 GPIO_ACTIVE_HIGH; /* PH5 */
+ usb0_vbus-supply = reg_usb0_vbus;
usb1_vbus-supply = reg_usb1_vbus;
usb2_vbus-supply = reg_usb2_vbus;
status = okay;
--
2.4.2
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[linux-sunxi] [PATCH 16/20] ARM: dts: sun8i: Enable USB DRC on Ippo Q8H-A23 tablets
Enable the otg controller on Ippo Q8H tablets, for now it is enabled
in host-only mode, because true OTG support requires support for
detecting and enabling Vbus through the axp221 pmic.
For this to work the Vbus on the port must be enabled by u-boot,
or a powered hub must be used.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index 95134c6..8d9da68 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -125,3 +125,12 @@
pinctrl-0 = r_uart_pins_a;
status = okay;
};
+
+usb_otg {
+ dr_mode = host;
+ status = okay;
+};
+
+usbphy {
+ status = okay;
+};
--
2.4.2
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[linux-sunxi] axp152 usb coexistence problem
Hello,
I tried to patch my kernel to load the axp20x driver to control the axp152 chip.
The power key works and I can power off the system.
However, on next power on the system would power off again when the ehci or
ohci controller is probed.
I disabled the controllers and everything appears to work OK otherwise.
Anyone has any idea why probing the USB controller would upset the axp?
I disabled the regulator part of the mfd so regulators should presumably not
get triggered.
Thanks
Michal
diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt
b/Documentation/devicetree/bindings/mfd/axp20x.txt
index 98685f2..7bbd8e9 100644
--- a/Documentation/devicetree/bindings/mfd/axp20x.txt
+++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
@@ -1,11 +1,12 @@
-AXP202/AXP209 device tree bindings
+AXP152/AXP202/AXP209 device tree bindings
The axp20x family current members :
+axp152 (X-Powers)
axp202 (X-Powers)
axp209 (X-Powers)
Required properties:
-- compatible: x-powers,axp202 or x-powers,axp209
+- compatible: x-powers,axp152, x-powers,axp202 or x-powers,axp209
- reg: The I2C slave address for the AXP chip
- interrupt-parent: The parent interrupt controller
- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
diff --git a/arch/arm/boot/dts/axp152.dtsi b/arch/arm/boot/dts/axp152.dtsi
new file mode 100644
index 000..fe2dc01
--- /dev/null
+++ b/arch/arm/boot/dts/axp152.dtsi
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * AXP202/209 Integrated Power Management Chip
+ * http://www.x-powers.com/product/AXP20X.php
+ * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
+ */
+
+axp152 {
+ compatible = x-powers,axp152;
+ interrupt-controller;
+ #interrupt-cells = 1;
+
+ regulators {
+ /* Default work frequency for buck regulators */
+ /* FIXME update regulators for AXP152 defaults */
+ x-powers,dcdc-freq = 1500;
+
+ reg_dcdc2: dcdc2 {
+ regulator-name = dcdc2;
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = dcdc3;
+ };
+
+ reg_ldo1: ldo1 {
+ /* LDO1 is a fixed output regulator */
+ regulator-always-on;
+ regulator-min-microvolt = 130;
+ regulator-max-microvolt = 130;
+ regulator-name = ldo1;
+ };
+
+ reg_ldo2: ldo2 {
+ regulator-name = ldo2;
+ };
+
+ reg_ldo3: ldo3 {
+ regulator-name = ldo3;
+ };
+
+ reg_ldo4: ldo4 {
+ regulator-name = ldo4;
+ };
+
+ reg_ldo5: ldo5 {
+ regulator-name = ldo5;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
[linux-sunxi] OrangePi with GC2035 camera
I have an OrangePi and I'm trying to get a gc2035 camera working. I'm using a 3.4.103 kernel and I'm writing a sun4i_csi0 driver. It works in single frame mode but in video mode I get the first four frames then it repeats a sequence of the first three frames followed by the latest frame. The maximum frame rate I can achieve (with streamer or guvcview) is about 2.5 frames per second. So I'm dropping most of the frames but what I can't understand is why I'm getting a repeat of the first three frames. The maximum frame rate is limited because the OrangePi is headless and I'm using X11 via ssh to access it. But if I get streamer to write a local file rather than send the stream I still get the repeat of the first three frames. I do see error messages from v4l2 reporting waiting for a free buffer and also rate: queueing frame twice messages. I have a GC2035 datasheet but the details are very limited and many registers are marked as reserved. Has anybody heard of my frame repeat problem or can anybody suggest where I can find the buffer list code ? Thanks, Steven -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
