[PEDA] Antwort: SLOTS?
You wrote on 11.05.2004 02:53:44: how does protel 99SE handle drilled slots? not at all, unfortunately Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Creating selective keepouts
Ray, try to draw a closed track on the bottom layer surrounding the area you don't want routes, and give the track the attribute keepout. With this, no route on bottom layer may cross this area. It may happen, that the router places short traces which stay only within this area. Anyway, you can try. You could place a fill or polygon to cover the area, and give it the attribute keepout, but then the router cannot place vias there also. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Ray Mitchell [EMAIL PROTECTED]An: [EMAIL PROTECTED] hlink.net Kopie: Thema: [PEDA] Creating selective keepouts 08.04.2004 17:26 Bitte antworten an Protel EDA Forum I'm using Protel 99SE SP6. I have components on the top and bottom of my board. In one area of the bottom I would like the autorouter to be allowed to place both vias and traces as needed. In another area of the bottom, however, I would like it to be able to place vias, as needed for routing on other layers, but I don't want it to be able to place any traces. I've tried specifying NOT USED in the design rules for the bottom layer but when I do that it will not route anything anywhere. Any thoughts on this? Ray Mitchell Engineer, Code 2732 SPAWAR Systems Center San Diego, CA. 92152 (619)553-5344 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] VME backplane
Hi, I would be grateful if someone had the pcb of a 21-slot 6U backplane to share (e.g.VME would be fine). I don't need any components or routing, just the mechanical (and maybe keepout) layers with the outline and mounting hole definitions. Thank you. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: BGA Tenting/Specifications
Yes Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Michael Biggs [EMAIL PROTECTED]An: 'Protel EDA Forum' [EMAIL PROTECTED] power.comKopie: Thema: [PEDA] BGA Tenting/Specifications 05.01.2004 23:10 Bitte antworten an Protel EDA Forum Can get I a few opinions about how you guys handle BGA components in your layouts? Do you generally tent (using tenting in Protel99SE via properties) the dog-bone vias that branch off of each BGA pad to prevent solder thieving or specify in your specifications to Plug top side vias. There may be other ideas and I'm sure the responses will vary on the assembly methods. Generally I see a reflow then wave on these mixed technology PWA I am prototyping. Thanks in advance. -MB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Silver Immersion, was: Trace Width Charts
Brian, we went completely away from gold, nothing but problems in the soldering process. Silver showed much better results for us. The price is about the same. Maybe it depends on the assembly house and the processes they are using. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Brian Guralnick [EMAIL PROTECTED]An: Protel EDA Forum [EMAIL PROTECTED] eotron.ca Kopie: Thema: [PEDA] Silver Immersion, was: Trace Width Charts 26.09.2003 09:56 Bitte antworten an Protel EDA Forum I have just attended a meeting of the IPC Designers Council where the subject of finishes for PCB's came up and it was revealed that Silver Immersion seems to have great benefits for assembly, shelf life, solderability, rework, etc... Can anyone give me their experiences with the process and its benefits and down sides? Have you personally used it, how long, what sort of problems have you seen, what are the cost issues? Best Regards, Bill Brooks Politics is more difficult than Physics - Albert Einstein Good question. I would also like to know how it compares to Gold Immersion. I've gone all gold on all of my current PCBs as a means to improve overall general quality. (eg: http://pages.infinit.net/helloftp/bd2.jpg A-LA-CARTE AV headend scalar switcher PCBs.) Is silver any better, or cheaper? _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: Brooks,Bill [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Thursday, September 25, 2003 4:16 PM Subject: Re: [PEDA] Trace Width Charts I have just attended a meeting of the IPC Designers Council where the subject of finishes for PCB's came up and it was revealed that Silver Immersion seems to have great benefits for assembly, shelf life, solderability, rework, etc... Can anyone give me their experiences with the process and its benefits and down sides? Have you personally used it, how long, what sort of problems have you seen, what are the cost issues? Best Regards, Bill Brooks Politics is more difficult than Physics - Albert Einstein * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE places hidden components
Hi Abd and Ian, unfortunately that does not work. I tried to do just what you suggested, but it selects nothing. What I do now is to place the PCB outline not in the center of the workspace, as it defaults to, but near the down-left corner of the workspace. That leaves enough room for all components. I don't use the autoplacer, it messes up things and fits only half of the components onboard. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Abd ul-Rahman LomaxAn: Protel EDA Forum [EMAIL PROTECTED] [EMAIL PROTECTED]Kopie: ign.com Thema: Re: [PEDA] 99SE places hidden components 28.07.2003 23:44 Bitte antworten an Protel EDA Forum There are autoplacement features of 99Se that might help with this problem, but I'd have to test it to be sure. What I would do if I had components stacked up off the workspace is to Select All, then Deselect Inside a box that I could draw to include all but a few components at the edge. Then I'd pick up one of the remaining visible selected components and pull the rest into the workspace, they should move together. All in all, it should take less than a minute to fix. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] 99SE places hidden components
Hi, did anyone notice the following bug in 99SE? I'm referring to SP6. When you draw a PCB outline from the scratch and then call the update PCB function in the corresponding schematic, in order to import your parts and nets into the PCB file, the synchronizer places the parts on the right side of the board outline; same parts horizontally, different parts vertically. If you have many different parts, i.e. the vertical column of components is high, some can be placed outside the reachable workspace (area on the screen reachable by move in/out and the scroll bars). If you do not notice this directly, you will notice that in every update PCB iteration you do when you change something in the schematic, the synchronizer adds a number of components and lots of nets that he had added before, but seems to have forgotten, as these components are invisibly and unreachable placed vertically outside the working place. You can bring them to the working place, if you know what is missing, by using the Move Component function. This brings them back. Very weird behaviour! Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] disappearing split planes
Leo, check again that there really is no overlap whatever small between the split sections. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Protel99SE and Specctra v7.1
Hi, SPECCTRA V7 works fine with Protel99SE. Just the usual small problem with via hole size, when read back to Protel. All via holes are set to 28mil, need to be gloablly changed after. This issue has been between SPECCTRA and Protel ever since, and still exists in DXP. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Loc Tran [EMAIL PROTECTED]An: [EMAIL PROTECTED] lobal.netKopie: Thema: [PEDA] Protel99SE and Specctra v7.1 05.03.2003 05:30 Bitte antworten an Protel EDA Forum Hello All, Has anyone used Protel99SE with Specctra v7.1? Are there any issues, major problems with this combination? Thanks, Loc Tran * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Antwort: 99SE start failure
Gisbert, OK, I'm lost, call me dumb, what's a STRG key ? JaMi JaMi, Strg is written on the key on my (german) keyboard. Maybe on a us keyboard it is named differently, Control, may be. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: 99SE start failure
Rene, while starting up 99SE hold the STRG key pressed in order to prevent 99SE to load any project. Then load the manually one after the other to see where the problem is located. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Rene Tschaggelar An: Protel EDA Forum [EMAIL PROTECTED] tschaggelar@dKopie: planet.chThema: [PEDA] 99SE start failure 30.01.2003 14:47 Bitte antworten an Protel EDA Forum Upon startup, it loads a few projects up until it fails with a modal form : Access Violation at ... in module CSRTL50.bpl. read of adress ... I have to kill the app with the task manager and the same repeats after a restart. 99SE SP6 on WinNT4 SP4 I vaguely remember some files will have to be deleted but lost which. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com commercial newsgroups - http://www.talkto.net * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Schematic component parts swapping around...
Hi Julian, this also happens when you update a schematic part from library. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Julian Higginson An: 'Protel EDA Forum' [EMAIL PROTECTED] J.Higginson@laKopie: ke.com.au Thema: Re: [PEDA] Schematic component parts swapping around... 23.12.2002 02:18 Bitte antworten an Protel EDA Forum Hey Darren, The parts will (can) swap when you re-annotate the schematic the best you can do is get them the way you want them and only re-annotate '?' parts after that. thanks for the info. I only ever annotate '?' parts, and I'm very sure that the first parts I'd noticed were swapped had already been given designators before they got swapped but I could be mistaken. I hope so. Strange though - I've never noticed this behaviour with Protel before, and I've placed a fair few multi part components before it always managed to keep the component parts right in the positions I'd left them, even if it doesn't always group the parts with the same designators I'd always like... thanks, Julian -- Julian Higginson - Design Engineer - Lake Technology. 502/51-55 Mountain St, Ultimo, NSW, 2007, Australia. mailto:[EMAIL PROTECTED] - http://www.lake.com.au * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Rules and PCB library definitions
could try to confirm this effect. If it is not a mistake on my side, it is a very serious bug. I would be grateful if someone could check if this behaviour also shows under DXP. I just received my copy of DXP, but have to start the learning curve first, which will take some time. So I cannot check myself now. Thank you. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com ga@nateurope. com An: Protel EDA Forum [EMAIL PROTECTED] Kopie: 03.12.2002 Thema: [PEDA] Rules and PCB library definitions 10:14 Bitte antworten an Protel EDA Forum Hello group, does anyone know how to overcome the following effect: When I define e.g. a BGA component in PCB library editor and include fanouts and preroutes for the pads, once I have that part placed on the PCB, the specified rules for clearance, power connection, etc. do not apply for the preroutes and fanouts, but default to the rules setting for board. Is this a bug, and is there some workaround? Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Rules and PCB library definitions
Hi, I posted the attached message on this forum some days ago, but got no reponse. Perhaps someone could try to confirm this effect. If it is not a mistake on my side, it is a very serious bug. I would be grateful if someone could check if this behaviour also shows under DXP. I just received my copy of DXP, but have to start the learning curve first, which will take some time. So I cannot check myself now. Thank you. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com ga@nateurope. com An: Protel EDA Forum [EMAIL PROTECTED] Kopie: 03.12.2002 Thema: [PEDA] Rules and PCB library definitions 10:14 Bitte antworten an Protel EDA Forum Hello group, does anyone know how to overcome the following effect: When I define e.g. a BGA component in PCB library editor and include fanouts and preroutes for the pads, once I have that part placed on the PCB, the specified rules for clearance, power connection, etc. do not apply for the preroutes and fanouts, but default to the rules setting for board. Is this a bug, and is there some workaround? Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Rules and PCB library definitions
Thanks, Robert, but no, this is not the explanation. I did just as you described before routing, in order to assign the signal names to the traces and vias which are part of the component. I also unlocked all primitives of that component. I do a complete DRC check which runs without errors. The traces and vias are assigned to the correct nets. They just don't obey to rules. E.g., I set a special rule for a special via size, and assign this size to all the vias which are part of the BGA decal by global change. The rule will not apply for them, but for all other vias with the same specification, which are free primitives. Global change works on these primitives, rules don't. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Robert M. Wolfe An: Protel EDA Forum [EMAIL PROTECTED] wolfe.rm@sneKopie: t.net Thema: Re: [PEDA] Antwort: Rules and PCB library definitions 12.12.2002 15:23 Bitte antworten an Protel EDA Forum Gisbert, One possibility might be? Protel is not an intelligent enough program to automatically know after synchronization that these traces now in a PCB and attached to pads that now have nets associated with should also be part of that net. That being said you need go to Design/Netlist Manager and click the Menu button in lower left corner to bring up menu then use Update Free Primitive From Component Pads This then makes ALL traces in the whole board that are attached to pads the net associated with that pad. So just be aware when doing this. My feeling is if it was built into the footprint the system should know to make i tpart of the net automatically. Not sure but this may be why your taces do not adhear to rules, I would think if you had online DRC turned on you would also see green for all these tracks vs pads as clear/short errors. Bob Wolfe - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, December 12, 2002 4:18 AM Subject: [PEDA] Antwort: Rules and PCB library definitions Hi, I posted the attached message on this forum some days ago, but got no reponse. Perhaps someone could try to confirm this effect. If it is not a mistake on my side, it is a very serious bug. I would be grateful if someone could check if this behaviour also shows under DXP. I just received my copy of DXP, but have to start the learning curve first, which will take some time. So I cannot check myself now. Thank you. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com ga@nateurope. com An: Protel EDA Forum [EMAIL PROTECTED] Kopie: 03.12.2002 Thema: [PEDA] Rules and PCB library definitions 10:14 Bitte antworten an Protel EDA Forum Hello group, does anyone know how to overcome the following effect: When I define e.g. a BGA component in PCB library editor and include fanouts and preroutes for the pads, once I have that part placed on the PCB, the specified rules for clearance, power connection, etc. do not apply for the preroutes and fanouts, but default to the rules setting for board. Is this a bug, and is there some workaround? Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED
[PEDA] Rules and PCB library definitions
Hello group, does anyone know how to overcome the following effect: When I define e.g. a BGA component in PCB library editor and include fanouts and preroutes for the pads, once I have that part placed on the PCB, the specified rules for clearance, power connection, etc. do not apply for the preroutes and fanouts, but default to the rules setting for board. Is this a bug, and is there some workaround? Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] update decals in PCB
Hi group, I have a design done some months ago. I want to do a redesign now. As in the meantime a number of PCB decals have been changed, and I want these changes to be taken into the redesign layout. Is there a possibility of doing an update parts from library function, which updates all used parts from all libraries? Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Update several PCB footprints from library, update decals in PCB
Robert, Ian, this answers my question also. Thank you. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Robert M. Wolfe An: Protel EDA Forum [EMAIL PROTECTED] wolfe.rm@sneKopie: t.net Thema: Re: [PEDA] Update several PCB footprints from library. 18.11.2002 14:03 Bitte antworten an Protel EDA Forum Ian Wrote, I think that the fact that we can't controllably update footprints from a library, in P99SE, is a big oversight. It should have been there and certainly in one of the service packs for P99SE as we have been asking for it for a long time - not a bug though. It is an area under discussion by DXP users. Those with long memories will remember the very useful component property Update Footprint checkbox in V2.8 and will also remember the comments on and off over the years about its removal in V3 and later revs. Ian , Yes I would say it was a big oversight. But looking at your responce to make a server, would it be possible to have the system report what footprints are out of date like you get to see what is being updated when doing a synchronization with schematic before you commit to the changes? I think some thing like that would be very handy. Or at the very least is there any way right now to at least get a report of what footprints do not match what is in the library, that way at least one could (much easier) keep track of what could or shold be updated. Still having to do it one by one but at least there is tracking of what changed easily. There may be times when one does not want to update a footprint. For that reason when the batch is done it would be nice to have the report prior to a commit to be able to control what gets updated. Just a thought, for who ever does do this or food for thought on DXP. I too have had little time and have not even looked at DXP yet so would hope that have improved it there??? Bob Wolfe - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, November 17, 2002 5:26 PM Subject: Re: [PEDA] Update several PCB footprints from library. On 09:45 AM 15/11/2002 -0600, Yuriy Khapochkin said: Hi, is there any way to update all footprints in the PCB from library? Currently I press Update PCB button after editing each component in library, but it's too annoying. Yuriy. This issue has cried out for a server for a long time. The problem is that there is no documented PCBLib process that does this task directly, so it is not possible to make a macro that uses the FirstComponent/NextComponent PCBLib processes to iterate over the library and update. The UpdatePCB button must cause execution of a number of steps not a single process - either that or the process is not documented. There would be solution for anyone wishing to write a server. When your server starts up it should check that a PCBLib window is active. It should then check that the Design Manager is active and the Browse PCB tab visible. Then the server should search all the child windows of the app for a button with a caption UpdatePCB and stash its handle. Then iterate over all the components in the library and send a WM_LBUTTONDOWN message followed by a WM_LBUTTONUP message to the saved handle. It may even be possible to find the Delphi TButton object from its handle and then use the higher level Delphi object functions to activate the button. Finding the button handle is not too hard as you can search down the chain from the top level window in a fairly consistent pattern. To find the window tree use something Spy++ that comes with the M$ compilers. Then at each level you can search for a known window caption to get to
[PEDA] Antwort: 99SE SP6 gerber file names transposed
Hi Dave, if you ever renamed layers in the layer stack manager you get these strange results. It is a bug I reported some months ago. If you remember how to rename them to their original names, that might help. If not, no chance (to my knowledge). Maybe a copy of layer by layer to a clean database would help also. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Dave ElorantaAn: Protel EDA Forum [EMAIL PROTECTED] eloranta@locKopie: usinc.com Thema: [PEDA] 99SE SP6 gerber file names transposed 07.11.2002 15:55 Bitte antworten an Protel EDA Forum Hi I have a 10 layer PCB design file in which the editor shows layer names normal, the design manager shows the color swatch and layer name properly. When the gerber files are generated the .g2 file has the tracks from midlayer4, .g3 file has the data from midlayer 2 , the .g4 file has the data from midlayer 3. Another side effect is that on the tools-preferences-colors dialog box the mid layers appear in this same shifted pattern 1-4-2-3. This layer sequence also occurs on the gerber output selection check boxes. The problem appears to be in the design file because I did a new install on a separate computer and the results are the same. I copied the file to a new name selected all, cleared all, cleared all nets, saved and reopened and the empty design file still exhibits the same shifted layer patterns. I saved the file to ASCII and found that line 2 had a number of definitions like layer?name=midlayer? in the shifted sequence but correcting that in the original ASCII file caused the file to get truncated after line 72. I suspect something I did early in the design using the layer stack management must have caused this but I have not found a way back. I need to correct this file for future revisions. Thank you Dave Eloranta Locus Inc. 5440 Research Park Dr. Madison, WI [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Error when creating and opening a new shematic.
Waldemar, I remember a similar situation. You could try two approaches: 1. save the DDB in spite of the error messages, close it. and do a repair on this DDB. This helped me in one case. 2. Create a new DDB, and copy all documents from the DDB with the error message into the new one, and then work from there. This also helps sometimes. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Kulajew Waldemar waldemar.kulajew@kuAn: ProtelForum (E-Mail) [EMAIL PROTECTED] ebler.com Kopie: Thema: [PEDA] Error when creating and opening a new shematic. 22.10.2002 11:10 Bitte antworten an Protel EDA Forum Hello everybody out there. Here is an ONtopic question and I hope there is somebody left to read it and give me a advice for a solution ;-) For I did not find any Answer in the manual and the Knowledge base. I have got a Problem during creating and opening a new schematic. Let me discribe: A colleague of mine (in fact, my Boss) created a new DDB on his Machine and put one schematic in it. For he is in a hurry like every important person, he still is working on 99SE SP2 (!) He passed the DDB to me to add an other schematic and do the Layout job. Now, I added the missing symbols and footprints to our LIB, added the PCB outlines, (VME3u629, from Protel3.4 examples) and tried to add the needed schematic by clicking File|New|SchematicDocument. Worked fine so far. Now I try to open the new schematic, and got the Error mesage: File format not recognized after clicking the OK button it opened (!) and I got the message: Access violation at adress 0D6C8179 in Module ADVSCH.DLL. Read of Adress one more OK and one more of the same message and one more OK, it seams like I can work normally. But I am an fearfull guy and dont trust a design with three error mesages. Maybe there will come up one more? Or my design will be destroyed without any further message??? So I desided to ask the gurus among you. Did Anybody see this behavior before? Any experience with such problems? Me I am working on 99SE SP6 on M$ WIN98. Thank you in advance for any Information Waldemar * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] what is Fan out?
Miker, you are of course correct, but I don't think that this meaning of fanout was questioned. Fanout also means routing a short trace to escape from a SMD pad, and then placing a via to connect to an inner layer or a plane. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Robison Michael R CNIN An: 'Protel EDA Forum' [EMAIL PROTECTED] Robison_M@craneKopie: .navy.mil Thema: Re: [PEDA] what is Fan out? 17.10.2002 15:18 Bitte antworten an Protel EDA Forum Fan out is when a signal driver is driving more than one input. Seems like every technology has got it's own little terminology. Fan out is an important design consideration. In the digital world, you have to watch fan out because driving too many receivers will exceed the current driving capability of the driver. Also, when you get into signal integrity, you have to worry about impedance balancing and nasty reflections. miker ** Hi, I have been hearing this Fan out. But what is fan out. What it for? Adeline * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Top Notch Talent for Troubleshooting.
Baseball bats are also sometimes used as weapons, if you don't have a gun handy (yes, in the U.S. you can still own guns, thank God!). Ivan, I am sure the people especially in the Washington area are very pleased about this fact at the moment. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - DXP Forums Membership
Ivan, I can back this. I opened 3 Yahoo member accounts with different email addresses for different purposes, and did not receive any spam so far. Of course, when opening the account, you must uncheck all the pre-checked options for information they want to supply you with. If you do that, no problem. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Matt wrote on 03.10.2002 16:27:21: Ivan, I'm a member of about a dozen Yahoo groups and have gotten *zero* spam because of them (I know because I set up separate email addresses just for Yahoo -- just in case, then I could track it's source). If you do sign up and get a Yahoo ID, make sure your user preferences are set to all opt-out of any Yahoo third party email (this is where I think lots of people go wrong). That will keep you spam-free. As far as harvesting email addresses goes... Yahoo obscures your email address on all web site posts (public view) so that makes harvesting very difficult also. I was really really skeptical of Yahoo groups in the beginning, but unless things change I'm very happy with their privacy policy. Matt Pobursky Maximum Performance Systems On Thu, 3 Oct 2002 09:53:57 -0400, Bagotronix Tech Support wrote: While it is true that you do have to sign up as a member of Yahoo! Groups, once you have done that you are free to join any of the Yahoo! Groups that have Open Membership. How much spam do I have to sign up for? Seriously, one reason why I like the TechServ list is that AFAIK they don't sell it to spammers. And no one who isn't in the PCB biz is likely to be lurking and harvesting e-mail addresses. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] GTC - Guaranteed To Crash
Hi, I cannot confirm this behaviour. The given procedure works absolutely fine here, just toggles the 3 layers. W2K SP3, 99SE SP6, but not all the other processes you mentioned, just Lotus. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: A30FAD721297374AA60F0A636143FDC750BD39B3 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] amount of mails on PEDA
Hi group, since this SP7 stuff is being discussed, I typically have 100+ emails from the forum every day, instead of 10-30 before. Yes, I also would like to have SP7, but I suggest going back to normal. If someone wants to add JaMi's Ceterum censeo ... to every mail as a reminder for Altium, feel free. Hope it helps. By the way, JaMi, I recall that some time ago (last year?) you were harshly complaining about the traffic on this forum, and had made up a list to show how many mails some people sent per day, blaming them they obviously need not work, as they had time for writing legthy mails. This was mainly targeted at Abdul, but I found myself also on your list of shame with 2 mails that day. May I humbly state, that from 0:15 AM (my time) to 10:00 AM you posted 15 mails to the forum in just 10 hours. 15 On vacation? Or you definitely must have changed your mind since then. Also topics like: which boardshop can you recommend? I would be grateful if you could put to OT forum. It has got nothing to do with Protel, and is useless information for all those forum subscribers not located in the country of the requester (US in this case). Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: 61F8487CA81A1845A296D03CA9DEAFAD42620722 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Bizzare and Repeatable
Hello JaMi, the effect you describe This time, however, rather than wait for Protel to load, I hit the minimize button while it still has its little Protel Logo Box in the center of the screen, and is starting to load files, and it dissappears into the taskbar, so I can launch PowerDesk (or Explorer, or something else) so that I can go directly to the other system and copy the netlist to the local drive before importing (to eliminate anything that may be be happening because of the import across the network). snip Protel seems to be running just fine, but the Logo Box is right on top in the center of everything, and will NOT go away unless and until you shut down Protel. was reported by me about a year ago or so and was added to the bug list Ian Wilson is updating regularly. You can avoid this bug by a simple amendment in the Client99SE.ini file. This was posted as workaround: In the Client99SE.ini under system preferences is a line called DisplaySplashScreen=True. Just change true to false and there will be no splash screen anymore. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: A6DB0E301D426A48A1AB4974B5958C66249A5211 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Service Pack 7 - or free DXP
JaMi, I support your views on another service pack. There are several long-known bugs, which should be fixed as far as possible. M$ still delivers service packs for Win2K, although Win XP is the product sold today. Altium should do the same. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: ADC5658B7913234D8E89246A9E2086EF8A4C6558 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] DXP and Specctra
Hello, just a short question, as I did not have the time to evaluate the DXP trial so far: In the documentation/tutorials Altium placed on their website concerning DXP I did not find a single word about a Specctra interface. Does DXP have such an interface like 99SE or not, and did anyone test it? Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: 9D4B1D0532A03D418FB343079AD700224F27D02D * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort2: 99SE Crashes when trying to close design
Hi Matt, another point I forgot to mention: If you have launched Protel without loading the DDB (by pressing the STRG key while Protel is loading), you can then try the repair function on the DDB that crashes your system (Down Arrow/Design Utilities/Repair). You can only repair DDBs which are not open. It does not help often, but it is worth a try. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com Matt Daggett An: Protel EDA Forum [EMAIL PROTECTED] mdaggett@mcnKopie: c.org Thema: [PEDA] 99SE Crashes when trying to close design 27.08.2002 17:09 Bitte antworten an Protel EDA Forum I've got a design open that I would like to close but each time I close it in Protel, it crashes. So I relaunch Protel and of course it auto-opens it since it was the last document... but then I cant close it because it will crash the program again. Anyone had a similar problem? Fixes? 99SE SP6 + Win2k on P4 2.0 Northwood, 1GB RDRAM, Ultra160 SCSI I/O, nVidia Quadro2 thanks, matt - Matt Daggett MCNC - Wireless Research Group 3021 Cornwallis Road Research Triangle Park, NC 27709 voice: 919-248-9278 fax: 919-248-1455 http://www.mcnc.org/wireless/ - * Tracking #: 9229EA426DBECD4A8604B3A380F355131E7BF9C0 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Speaking of Protel Bugs. - Flame start!
Keep this fight off the forum! Mail it directly to the person(s) you want to address, if you think it appropriate. Did they not teach you manners when you were young? Obviously not. Most probably you will start shouting at me now. Send your insults to my given eMail address, not to the forum. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: C46B0BA2332F3E41BF764B23A9C5C2977D745130 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Speaking of Protel Bugs. - Flame start!
Ian, as I never received a reply to the cited mail below, I resend it. Please drop me a line. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com - Weitergeleitet von Gisbert Auge/NAT am 14.08.2002 11:56 - ga@nateurope. com An: Protel EDA Forum [EMAIL PROTECTED] Kopie: 01.08.2002 Thema: Re: [PEDA] Speaking of Protel Bugs. - Flame start! 12:33 Bitte antworten an Protel EDA Forum You make your point very clear, Ian. I am with you. Concerning the bug list you manage: Did you add the bug in gerber generation of renamed layers and the bug in translating layer information to Specctra to the list, which I described some weeks ago? I never received any comment to these mails. Regards, Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: DCF393C1107C2A47BBBE13199FEFBB8D8CEB3B62 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber and Specctra bugs
Hi Ian, thank you for the quick response. Here are the details: snip What would be really really helpful would be you laying out the info in the following form so I can copy and paste. Date: 2002/01/28 sort of format (/mm/dd) Summary: PCB: Gerber gerneration of renamed layers is (wrong?) Details: P99SE SP6 PCB: a few sentences describing the problem and any workarounds... Reported by: yourself here Confirmed by: has anyone confirmed it? Do this for both of the bugs, if you could. I do not have Specctra so would not really know what I was writing anyway... I will do as you suggest. Here we go: Date: 2002/07/05 Summary: PCB: Gerber generation of renamed layers creates 2 layer files, one with old and one with new name Details: P99SE SP6 PCB: In the Layer Stack Manager, when you rename a layer, the Layer Stack Manager shows the new name, and so do all other PCB functions related to layers, but when you create Gerbers, there shows up a layer with the old name, plus a layer with the new name, but this one is empty apart from multi-layer elements. Reported by: Gisbert Auge Confirmed by: not until now to my knowledge Date: 2002/07/05 Summary: PCB: Autoroute/Specctra Interface/Export design file can generate a .DSN file with the wrong number of routing layers specified Details: P99SE SP6 PCB: There is a bug in the influence of Rules/Routing layers and the Autoroute/Specctra Interface/Export design file function. It is easy to reproduce. Do the following: Take a multilayer PCB (no matter how many layers, but at least one inner routing layer) and define the layers in Layer Stack Manager as usual. Go to Design/Rules/Routing Layers/Properties and define the layer directions as desired. Close with ok. Go back to the Layer Stack Manager and delete one inner routing layer. Check in Design/Rules/Routing Layers/Properties that the layer is not active (selected and editable) any more. Do an export to SPECCTRA. Check the resulting .DSN file, and you will see, that the deleted layer is exported to SPECCTRA as active routing layer, resulting in SPECCTRA routing the design with too many layers. A clear, reproducable bug. Workaround: Before deleting the layer in the Layer Stack Manager, go to Design/Rules/Routing Layers/Properties and reset the layer to not used. Then delete it in the Layer Stack Manager, and it is gone for good. Reported by: Gisbert Auge Confirmed by: not until now to my knowledge Still onward and upward. I gather there is lots of bad weather in Europe at the moment - are you very wet where you are? It is very dry in Eastern Australia at the moment and little chance of any significant rain till into next year apparently - full drought conditions in many parts. Not too bad in our part of the country, fortunately. But very bad in the southeast parts of Germany, Austria, and the Czech Republic. Most probably for the same reason why it's so dry in your place. And still the US refuse to sign the Kyoto agreement. They might get it next time. They will notice. No harm intended. Just my 2 Eurocents. Mit freundlichem Gruß Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: 610057760B0CD147AA97BEEE28250F60E375 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Speaking of Protel Bugs. - Flame start!
You make your point very clear, Ian. I am with you. Concerning the bug list you manage: Did you add the bug in gerber generation of renamed layers and the bug in translating layer information to Specctra to the list, which I described some weeks ago? I never received any comment to these mails. Regards, Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: DCF393C1107C2A47BBBE13199FEFBB8D8CEB3B62 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Speaking of Protel Bugs.
JaMi, aren't you mixing up some things in this discussion? See my comments below. I also eventually found this forum, which has been of some help. The problem here is that in general everybody refuses to realize or acknowledge that this (as with many other things) is a bug, notwithstanding the fact that it has been acknowledged in the knowledge base for years and pops up here in the forum on a regular basis. Most people here appear to love Protel and hate Microsoft, so the blame always gets shifted to Microsoft or if not them, the implied stupid user. It was only after several months of using the Microsoft wheel mouse with the Intellimouse software wheel disabled for Protel, that I realized that the mouse wheel had always worked well on a previous employers Protel 98 and Protel 99 (in both Windows 95 and NT) which used a Logitech wheel mouse, and also the trial version of Protel 99 SE that I had at home which also used a Logitech wheel mouse. I bought my own Logitech cordless wheel mouse for work, and installed the Logitech Mouseware, and magically the problems went away, and not just the problems with the keyboard, but all of the problems that I had been having. It was great to have both the wheel and the keyboard shortcuts all back at the same time, but more importantly, the system stopped crashing. Plain and simple. The system stopped crashing on a regular basis. I went from 7 or 8 crash and reboots a day, down to about 1 a week, if that. Microsoft Bashing is not the answer, anymore than Protel Bashing. The real answer is for a software developer the size of Protel / Altium to have a functional relationship with Microsoft. They should be a member of the Microsoft Development Network where they would get regular updates on software and problems, and more importantly, they would get real Microsoft Technical Support on issues such as this. Yes it cost a few sheckels to join the MDN, probably a few grand a year, certainly more than I can afford, but there is no excuse in the world for Protel / Altium not to be a member. Sometimes I wonder if they even know that the MDN and other forms of Microsoft Support available to OEM Software Developers exists. When you install a piece of hardware (e.g. a mouse), the driver software either goes with the hardware product, or you may chose to install the Microsoft driver (if supplied). The application SW (like Protel) should not need to mess around with any special HW feature (like it used to be in old DOS times), but just call system (Windows) functions and leave the rest to the OS. I am just a simple-minded hardware developer, but if you state that the application works fine with a Logitech mouse and does not with a Microsoft mouse, there cannot be any question about who is to blame. I have no preference for any OS; I want a working system, that's all. I just don't care about who writes drivers, be it the OS people, be it the hardware supplier. I dare to demand from SW the same as anyone takes for granted from any HW product they purchase: it shall function as specified. In consequence: If Microsoft mice don't work with Microsoft SW (MS is the OS provider, not Protel!), don't buy mice from Microsoft. It's as simple as that. The fact that use of the Logitech drivers eliminates the problem with Protel speaks for itself. I don't mind your devotion for Microsoft, I use their SW as well, as it is part of my work, but please let us stick to the facts. By the way, how do you know whether Altium is member of MDN or not? Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: 3AB2FBE7FC15B94F91B431E004355C6778F63EFA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Speaking of Protel Bugs.
Tony, you wrote on 23.07.2002 04:47:57: Speaking about the ability of any other Windows Application: I really HATE IT when I'm working on a document in MS Word and I decide to change my print driver for HP Laserjet to Acrobat and all my FRICKIN' PAGE FORMATTING CHANGES!! You what that to be our MODEL for success. Please! Why can't MS word and these damn print drivers just print what I see on my screen!??? Why does my screen change when I change drivers?? What a PITA that is! very true indeed! This has been annoying me fro a very long time!.. Regards, Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: E3EE99410948C448B45FF6E78DF48F61D2ACE4B6 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Routing Layers and Export to SPECCTRA
Hi, I don't recall if this was brought up before, but there is a very irritating bug in the influence of Rules/Routing layers and the SPECCTRA export function. It is easy to reproduce. Do the following: Take a multilayer PCB (no matter how many layers, but at least one inner routing layer) and define the layers in Layer Stack Manager as usual. Go to Design/Rules/Routing Layers/Properties and define the layer directions as desired. Close with ok. Go back to the Layer Stack Manager and delete one inner routing layer. Check in Design/Rules/Routing Layers/Properties that the layer is not active (selected and editable) any more. Do an export to SPECCTRA. Check the resulting .DSN file, and you will see, that the deleted layer is exported to SPECCTRA as active routing layer, resulting in SPECCTRA routing the design with too many layers. A clear, reproducable bug. Workaround: Before deleting the layer in the Layer Stack Manager, go to Design/Rules/Routing Layers/Properties and reset the layer to not used. Then delete it in the Layer Stack Manager, and it is gone for good. And another: In the Layer Stack Manager, when you rename a layer, the Layer Stack Manager shows the new name, and so do all other PCB functions related to layers, but when you create Gerbers, there shows up a layer with the old name, plus a layer with the new name, but this one is empty apart from multi-layer elements. Dangerous pitfall. Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: A54FA970A36B764CA055B071E0BC57D45CD668EB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Images and Schematic Templates
I have been following this thread (and others on the same topic before) with some astonishment. I placed a .TIF file with our company logo on the schematic templates long time ago, which is stored in only one location, far away from any protel files, and it just works fine with any project I have been doing since. There has never been any problem whatsoever with this feature. It is a local drive, though, where the graphic is located, not a network drive. WIN2K and P99SE SP6 (like most of you). Gisbert Auge N.A.T. GmbH www.nateurope.com Dennis Saputelli dsicon@integratedcontroAn: Protel EDA Forum [EMAIL PROTECTED] lsinc.com Kopie: Thema: Re: [PEDA] Images and Schematic Templates 03.07.2002 05:18 Bitte antworten an Protel EDA Forum after 'solving' this problem with the help of others here by putting copies of the bitmap all over the f'ing place it seemed to work well and then ... i opened a schematic today and there was no picture, only the text placeholder i give up, it just doesn't work IMHO for the record i have copies of the bitmap in: the local directory inside the DDB in the \system directory of protel on all the machines in the \Design Explorer directory in the library folders in the library DDBs probably other places as well so for some X thousand dollars we can hope that DXP will work in this very simple matter Dennis Saputelli DUTTON Phil wrote: Hello Matt, Make sure that your .bmp is in a known library location with your templates, and when you insert it into your template file, insert it from that library location. If you have it in a 'project' directory for example, and open your design from the 'recent edits' list, then Protel will not find the .bmp. Sometimes if you open another design, in a directory that the .bmp is in, then they will suddenly appear... regards, Phil. Phil Dutton C.I.D. Senior CAD Technician IPC Certified Interconnect Designer Tenix Defence Pty Ltd Electronic Systems Division Second Avenue, Technology Park, Mawson Lakes. SOUTH AUSTRALIA 5095 Phone (08) 8300 4400 (reception) (08) 8300 4481 (direct) Fax (08) 8349 7420 email [EMAIL PROTECTED] Internet Page http//www.tenix.com -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 3 July 2002 11:36 AM To: Protel EDA Forum Subject: [PEDA] Images and Schematic Templates I have added a bitmap image to the schematic template I normally use. However, when I apply the template to an existing document, then reopen the document, sometimes the image isn't there. Whether or not the image appears seems to be pretty much a random event. Does anyone know of a remedy for this? Cheers, Matthew van de Werken Electronics Engineer CSIRO Exploration Mining - Gravity Group 1 Technology Court - Pullenvale - Qld - 4069 ph: (07) 3327 4685 fax: (07) 3327 4455 email: [EMAIL PROTECTED] * Tracking #: BAF036FDA937A742932F213C4EBD744F37133143 * -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] BOM
Hi, when I try to generate a BOM from SCH in spreadsheet format, I receive an error message: CLIENT99SE: License information for TF1Book is invalid. What's that? Generation of BOM in Protel format works okay. Protel99SE SP6. Win2K. Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: 5B7186519A0BF646AE5849F792CAB254A88C30A0 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Power Planes in Layer Stack
Abd-ulRahman Lomax wrote: What does the Stack Manager show? What shows in the Design/Split Planes dialog? Stack Manager shows: TopLayer MidLayer1 MidLayer2 InternalPlane1 (+3.3V) InternalPlane2 (GND) MidLayer3 MidLayer4 MidLayer5 MidLayer6 InternalPlane3 (+2.5V) InternalPlane4 (VCC) MidLayer7 MidLayer8 BottomLayer Design/Split Planes shows: Split Plane (+1.5V) on InternalPlane4 Split Plane (+1.8V) on InternalPlane4 Split Plane (+3.3V_IN_L) on InternalPlane4 Split Plane (+3.3V_IN) on InternalPlane1 Split Plane (PRECHARGE) on InternalPlane1 Split Plane (SGND) on InternalPlane2 Split Plane (VCC_IN) on InternalPlane3 Split Plane (VDD_CORE) on InternalPlane3 Looks quite normal to me. Regards, Gisbert Auge N.A.T. GmbH www.nateurope.com I set up a board with 5 power planes; lateron I found out that by efficiently using split planes I could reduce them to 4. The obsolete power plane was named Internal Plane 4. So I deleted this plane and renamed Internal plane 5 to Internal Plane 4. All seemed ok, until I called the CAM manager and did Gerbers. Protel still produces 5 power planes, plane 4 being empty, and the real plane 4 still named plane 5. I found no workaround for that so far. apart from renaming Gerber files manually. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Power Planes in Layer Stack
Hi, I'd like to report a bug (?) in the layer stack management of power planes. I set up a board with 5 power planes; lateron I found out that by efficiently using split planes I could reduce them to 4. The obsolete power plane was named Internal Plane 4. So I deleted this plane and renamed Internal plane 5 to Internal Plane 4. All seemed ok, until I called the CAM manager and did Gerbers. Protel still produces 5 power planes, plane 4 being empty, and the real plane 4 still named plane 5. I found no workaround for that so far. apart from renaming Gerber files manually. Regards, Gisbert Auge N.A.T. GmbH www.nateurope.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] negation character redux
A workaround to those issues is: Print to Acrobat Writer, and then send to printer from Acrobat. Works fine with \ negation. Gisbert Auge N.A.T. GmbH www.nateurope.com Dennis Saputelli dsicon@integratedcontroAn: Protel EDA Forum [EMAIL PROTECTED] lsinc.com Kopie: Thema: Re: [PEDA] negation character redux 04.06.2002 18:35 Bitte antworten an Protel EDA Forum wait till you try printing on various devices as you may tell from this thread most (?) of us are not using that \ because of issues (love that word, it so neutral!) Dennis Saputelli Mira wrote: Thanks. Did you mean Tools/preferences? I checked it but it behaves differently. When \ is placed at the end it draws the line only after the last character. To get a single neation on the whole string I had to type \ in front of it. I like this flexibility. Mira --- Graham [EMAIL PROTECTED] wrote: Hi, Protel 99SE has, under options/preferences/graphical editing, a single negation check box. Graham Brown[EMAIL PROTECTED] Mira wrote: Hi, We use \. In PCAD you can type it once at the end. In Protel you have to type it after each character to get the same but it's possible. I don't see any problems with Protel itself. Mira --- Cliff Gerhard [EMAIL PROTECTED] wrote: We use a # after the signal name ala the PCI specification (GNT#, REQ#, etc.) ~~ Cliff Gerhard, P.E. E-M Designs, Inc. PH 949.661.3016 x 501 www.gerhardeng.com www.emdesigns.com www.emmanufacturing.com -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Saturday, June 01, 2002 10:58 AM To: Protel EDA Forum Subject: Re: [PEDA] negation character redux I know this has been widely discussed but ... re: pin naming on schematic symbols and the negation character thereof what was the consensus, or was there? i know the bar symbol is problematic and i have decided to never use it again i recall someone advocating the use of n as in nRW that doesn't look too bad but what about * or - i was scared to use those without some advice that those characters were not problematic (sometimes this sort of thing doesn't bite you until late in the game) as a functional issue i guess this question is probably more importantly applied to net labels than schem pin names but i think they should be done consistently Dennis Saputelli -- ___ www.integratedcontrolsinc.com Integrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003 San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * __ Do You Yahoo!? Yahoo! - Official partner of 2002 FIFA World Cup http://fifaworldcup.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings:
[PEDA] Antwort: Print preview bug on Arcs
David, I cannot support your experience. I am just doing a board containing routes using arcs on different layers, and the print preview works just fine. Protel 99 SE SP6, Win2K SP2. Gisbert Auge David.Watling@Z arlink.Com An: Protel EDA Forum [EMAIL PROTECTED] Kopie: 25.04.2002 Thema: [PEDA] Print preview bug on Arcs 13:05 Bitte antworten an Protel EDA Forum I have just discovered a bug. When using the print-preview tool to print a PCB containing 'Arc-mode' tracking, it locks up the application and I have to re-start Protel. Otherwise, I have found the print preview tool to be almost excellent. 2 questions: Is this old news, or have I found something new? Is there any way of printing a PCB with 'Arc-mode' tracking? Regards David Watling * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] flies in the archive
What the heck do the flies do in the archive? ;-) Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Menu hotkey letters
Steve and Heiko, thank you for the advice. Maybe I should have provided more details. Before posting the question, I had checked the menu properties, and they seem to be ok (including the ampersand at the correct position of the string). I have W2K pro SP2 installed, and Protel SP6. Perhaps Heiko's suggestion concerning the .rcs and .ini files may help. Heiko, I would be grateful if you could send me a set, so that I can compare that to my .rcs and .ini files. Thank you. Regards, Gisbert Auge N.A.T. GmbH www.nateurope.com Heiko Vachek Vachek@elektrAn: 'Protel EDA Forum' [EMAIL PROTECTED] onik21.deKopie: Thema: Re: [PEDA] Menu hotkey letters 28.03.2002 16:37 Bitte antworten an Protel EDA Forum Click the down arrow at the far left of the menu bar. Then choose Customize... You are now in the customize resources dialog. You can see that Shortcut Keys and Menus are two separate things. On the register card Menus press Menu. You should get a new dialog Menu Properties. You can double-click every item in the window to see its tree structure. The underlined character is marked by a letter directly before this character. You can also modify the client99SE.rcs file which is somewhat faster. All Protel .ini and .rcs files are to be found in the \WINNT directory. In Protel3 times it was almost normal that a crashing Client damaged its .ini and .rcs files. For this reason I used to save a backup of all .ini and .rcs files after installation. I can send you a set if you want. regards, Heiko Vachek elektronik 21 GmbH Webseite: http://www.elektronik21.de -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Thursday, March 28, 2002 3:27 PM To: Protel EDA Forum Subject: [PEDA] Menu hotkey letters Hi all, the underlining of the hotkey letters in the pull-down menus is gone in my Protel installation. The hotkeys still work, though. How do I get the underlining back? Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: P99SE SP6 tries to outsmart me
Rene, The update design has spurious errors. It may happen that changing a string ( 10k to 100k) in the schematic, leads to a hole bunch of actions during update design. Quite often remove a connection and redo the same connection. This appears to be some propagated errors. The probability is higher on reworked designs. what you describe often is a sign of double pins (same number on same device) or double component names within one design. You can check on double pin definitions within a library when opened for edit. I doubt that the update design function is buggy. Works fine with my designs, though. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Limitations on InternalPlane layers
Kiernan, I'm still on my first PCB under P99SE. I need to add quite a few extra routes, but the PCB is really dense. Can I route these on the InternalPlane layers? As the following text shows that you are talking about plane layers, I would strongly discourage you to do so, though it technically is possible. Seperated planes, especially ground planes, are a cause for trouble. If you absolutely have to place traces on them, take a 5V, 3.3V, etc. power plane for this purpose, but never a GND plane! Should I have used Polygon pours on ordinary layers instead? I would do that. If I am allowed to use the plane layers, then how can I tell whether I'm going to isolate some connections from others ERC should tell you that. I never tried such a design myself, though. But ERC works fine with split planes. and how can I clean up where the trace ploughing would leave nasty slices / lost copper? You must keep in mind that power layers are negativ layers. You can place fills and polygons on planes, which result in no copper for these areas. Also on plane layers can I pull the plane completely away from a particular area? Use fills, tracks, polygons, whatever you like and place them ther, where you want _no_ copper. And finally, if I use a polygon on a normal layer, then how do I create the thermal reliefs? When you place a polygon, select pour over same net. This does it. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: weird bug when clicking on tabs in workspace...
I don't know of any fix, but this also is a known, old bug. Is it on the bug list already, Ian and Abdul? Regards, Gisbert rimas [EMAIL PROTECTED]An: Protel EDA Forum [EMAIL PROTECTED] keley.edu Kopie: Thema: [PEDA] weird bug when clicking on tabs in workspace... 15.03.2002 03:50 Bitte antworten an Protel EDA Forum quick question - i've noticed some very annoying behavior recently when i've got a bunch of files open and i'm trying to switch between them by clicking on the tabs (which have the filenames on them) along the top of the work area. if i've got more tabs that will fit along the top of the screen, oftentimes when i click on a tab, instead of switching to the file i'd like it to, protel shifts the positioning of the tabs so that i wind up opening another file. this can be really annoying! anyone know what i'm talking about and/or know of a way to fix it? thanks so much, -rimas * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Writing messages all day . . .
JaMi, I spend about 20 - 30 minutes a day with this list; maybe more, if I decide to write detailed posts, which seldom happens. It is really worth the time. The members of this group are giving professional support to all kinds of problems related to this EDA product I earn my salary with. Problems I came across have been solved or explained in detail, which makes my work more effective than if I had to search other documentation (if available and often without success). I take the occasion and thank all posters for the effort they took. I appreciate the support given to me and try to pay it back by giving support to others when I think I can. No more than fair in my eyes. So you took another 5 minutes of my time today, and unproductive this time. :-) Regards, Gisbert JaMi Smith wrote on 15.02.2002 03:05:14: In 24 hours since 5:29 last night, there have been 63 post to this list. Most are just a few lines, while others are a few pages . . . Abd ul-Rahman Lomax [[EMAIL PROTECTED]] 14 posts Afshin Salehi [[EMAIL PROTECTED]] 1 post Anthony Whitesell [[EMAIL PROTECTED]]1 post Brad Velander [[EMAIL PROTECTED]]1 post [EMAIL PROTECTED]1 post Darryl Newberry [[EMAIL PROTECTED]] 1 post Dennis Saputelli [[EMAIL PROTECTED]] 2 posts Dwight [[EMAIL PROTECTED]] 1 post [EMAIL PROTECTED]2 post Geoff Harland [[EMAIL PROTECTED]]2 posts Harry Selfridge [[EMAIL PROTECTED]] 1 post [EMAIL PROTECTED] 1 post Ian Wilson [[EMAIL PROTECTED]] 5 posts Jason Morgan [[EMAIL PROTECTED]] 1 post Jon Elson [[EMAIL PROTECTED]]3 posts Ken Henrich [[EMAIL PROTECTED]] 2 post Michael Biggs [[EMAIL PROTECTED]] 1 post [EMAIL PROTECTED] 2 posts Mike Pilawa [[EMAIL PROTECTED]] 1 post Mike Reagan [[EMAIL PROTECTED]] 1 post Nick Piccinich [[EMAIL PROTECTED]] 1 post Peder K. Hellegaard [[EMAIL PROTECTED]]3 posts Philip J. Mayo [[EMAIL PROTECTED]] 1 post Rene Tschaggelar [[EMAIL PROTECTED]] 1 post Ros [[EMAIL PROTECTED]]2 posts Sar Saloth [[EMAIL PROTECTED]]2 posts Sean James [[EMAIL PROTECTED]] 2 posts Terry Harris [[EMAIL PROTECTED]] 1 post Tony Karavidas [[EMAIL PROTECTED]] 3 posts Waldemar Kulajew [[EMAIL PROTECTED]] 2 posts [EMAIL PROTECTED] 1 post Interesting . . . Some people just seem to have a lot of free time on their hands . . . JaMi Smith * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Net Violations (Help)
Probably the solution to your proble, is to uncheck the unrouted net constraint button in Tools/Design Rule Check menu, as long as the board has not been routed. Unrouted nets are always flagged the way you describe. This is very helpful when checking for remaining (partially) unrouted nets, or, even more important, for errors in placement of split plane vertices. Regards, Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Schematic symbols
I don't think there is. This would be on my wishlist, though. Regards, Gisbert Sean James SJames@telecast-An: Protel EDA Forum [EMAIL PROTECTED] fiber.com Kopie: Thema: [PEDA] Schematic symbols 14.02.2002 16:49 Bitte antworten an Protel EDA Forum Is there a way to have vertical oriented pins have horizontal pin names numbers? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: need help with Setup Mechanical Layers, please
If this is supposed to be joke, it is not funny. How did the attachment slip through the Techserv filter? Gisbert Ken Henrich khenrich@phaAn: Protel EDA Forum [EMAIL PROTECTED] zar.com Kopie: Thema: [PEDA] need help with Setup Mechanical Layers, please 13.02.2002 16:26 Bitte antworten an Protel EDA Forum Hi, When I open the Setup Mechanical Layers dialog box, many of the Mechanical xx titles are greyed as is the associated checkbox which is checked. Only two of these layers appear ungreyed and are displayable. All of the other greyed layers cannot be viewed in the pcb view though they can be used in a preview. Does anyone know how to enable these layers? [IMAGE]Regards Ken (See attached file: image001.gif) =?iso-8859-1?Q?image001.gif?= Description: Compuserve GIF
[PEDA] Antwort: Fun with PLD 99
Hi Jeff, I know this might be of little help, but you should seriously think about changing PLD development tools. You got the Altera tools, so why don't you use them? There sure is a reason for most of us Protel users, as far as I know, not to use the PLD tools from Protel. MAX Plus is freeware, and it is not that bad. It supports about 90% of all Altera devices, including pretty big ones. E.g. I just do a design with an EP1K100 device, a 484 pin fpBGA, and it's included in the free software package. Regards, Gisbert Auge N.A.T. GmbH Jeff Stout jstout@ncon.An: Association of Protel EDA Users com [EMAIL PROTECTED] Kopie: 06.02.2002 Thema: [PEDA] Fun with PLD 99 18:04 Bitte antworten an Protel EDA Forum Ok, I've finally got Protel's Altera PLD development system up and running. Now I'm really looking forward to some solid development with the Altera EPM7032 device. I configured the PLD compiler to produce PLA files, push the GO button, and found another problem. Protel's output converter for PLA files only outputs up to 254 characters; and wouldn't you know it, all pin names are put on the same line. This device has 32 inputs/outputs, so the last 12 outputs are left off the list with the first of the those last 12 cut off in the middle. Like this: #$ PINS 24 Input_1:37 Input_2:38 Input_3:39 Input_4:40 Output_5:2 Output_6:3 Output_7:5 Output_8:6 Output_9:8 Output_10:10 Output_11:11 Output_12:12 Output_13:13 Output_14:14 Output_15:15 Output_16:18 Output_17:19 Output_18:20 Output_19:21 Output_20:22 O There were suppose to be another 12 names at the end. GUU!! I've done several successful designs with Protel for the 22V10. Believe me when I say that getting Protel PLD to work was never this hard before. Jeff Stout P.S. I'll send a heads up to Protel as soon as I come to grips with the work arounds I'm now going to have to do. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Protel Multi License Special Pricing
According to Altium Germany the additional license fee is EUR 3875, which is significantly cheaper than 3995 US$, if you take into account the exchange rate, and it includes ATS and update to Phoenix. Sounds interesting to me. Regards, Gisbert Auge N.A.T. GmbH Abd ul-RahmanAn: Protel EDA Forum [EMAIL PROTECTED] Lomax Kopie: marjan@noho.Thema: Re: [PEDA] Protel Multi License Special Pricing com 03.02.2002 21:43 Bitte antworten an Protel EDA Forum At 10:51 AM 2/3/2002 -0800, John Williams wrote: FYI: http://www.protel.com/eproduct/p99se_pricing.htm The U.S. Protel sales manager me how much he wanted the resale price of licenses to be close to the regular price from the company, but the constant specials and uncertainty about upgrade pricing, etc., make this very difficult. This new additional license for half-price, does it include ATS? That's not stated I'd presume that it does, but I've learned that Protel does not always intend what one might think obvious. If it includes ATS, it is a real bargain. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Solder mask over via's
Why don't you generate 2 sets of Gerber files, one with and one without tenting, and select the top soldermask with tented vias from one set, and the bottom soldermask with not tented vias from the other set? Gisbert Auge Bryn Wolfe bwolfe@traclAn: Protel EDA Forum [EMAIL PROTECTED] abs.com Kopie: Thema: Re: [PEDA] Solder mask over via's 25.01.2002 13:43 Bitte antworten an Protel EDA Forum Actually, though, Hot Air Leveling should not cause the burst unless there is soldermask on both the top and bottom, or if it is a blind via. However, I can't think of a way in Protel to tell it to tent only the component side. You'd probably have to do some editing in the gerber file. This sounds like a feature that should be added to Protel, that is, selecting which side of the board tenting of through-hole vias occurs on: top, bottom, or both. Bryn Waldemar Kulajew wrote: Afshin just one more informotion: my Fab-house told me I should not tent vias complete. It couse problems because the soldermask will burst open during HotAirLeveling or wavesoldering because of the Air inside the via. They told me to leave the hole open and only put the cover the Copper. I did it in the way Ted Tontis suggested. Regards, Waldemar Ted Tontis schrieb: Afshin, To use the design rule go in the design rules, select manufacturing, select solder mask expansion, click add, select object kind, check via's, give the expansion a negative value, and click ok. Regards, Ted -Original Message- -- snipp -- Some of my via's are placed so close to pads after a route that I am afraid of bridging occurring when the PCB is soldered. -- snipp -- -- Name : Bryn Wolfe Title : Robotics Engineer Dept : Texas Robotics Automation Center (TRACLabs) Company: Metrica, Inc Addr : 1012 Hercules Drive Houston, TX 77058-2722 Voice : 281-461-7886 NASA : n/a FAX: 281-461-9550 Web: http://www.traclabs.com Email : mailto:[EMAIL PROTECTED] or mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Specctra Autorouter
Hi Gene, just keep in mind that the dongle drivers for V7 do not run under WIN2K (and probably not under XP either). There is no known workaround for that. No problems under W95 and W98. Regards, Gisbert Auge N.A.T. GmbH Gene Silvernail An: Protel EDA Forum [EMAIL PROTECTED] genes@belhavKopie: en.com Thema: [PEDA] Specctra Autorouter 24.01.2002 23:06 Bitte antworten an Protel EDA Forum Any wise words on using Specctra autorouter 7.1 before I attempt it * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autorouting or manual routing, or both?
Hi all, I agree with Remco, you always want to change something after the autorouter has finished. The DWIT command (do what I'm thinking) still has not been implemented :-) But I want to speak in favour of Swiss cheese, not only because of its excellent taste. It is true that an autorouter like e.g. SPECCTRA will not generate these parallel, evenly spaced bus structures on dense boards that you find on many hand-routed boards (especially PC motherboards, where you have all the space of the world for routing), which results in far less vias than what an autorouter will produce. But is this really desirable? There are pros and cons for both approaches. In very high speed design, every via creates a tiny reflection on the signal that may be intolerable with signal frequencies of several 100 MHz and above, whereas with frequencies below 100 MHz this will probably not be a critical issue. On the other hand, parallel bus structures can cause crosstalk problems hard to debug, which will simply not be there if the board was autorouted like Swiss cheese. Critical signals like fast clock traces or fast line interfaces I always route manually before invoking the autorouter. Of course also these signals can be routed satisfactory by a good autorouter, but it is necessary to define very precise rules for every critical signal and having purchased the router option needed to enable it to follow these rules (FST option with SPECCTRA, this option being about the same price as the complete router package including all other options). Gisbert Auge N.A.T. GmbH Remco v/d Heuvel R.vd.Heuvel@fusion-electAn: Protel EDA Forum [EMAIL PROTECTED] ronics.nl Kopie: Thema: Re: [PEDA] Autorouting or manual routing, or both? 22.01.2002 08:20 Bitte antworten an Protel EDA Forum Dear Matt, Normally I only route the boards by hand (4 6 layers) , my expierence with autorouting utillities (not only Protel) is that you still want to change tracks which you don't like so you will wind up re routing the whole board :) The only thing i sometimes use the autorouter for is routing the databus on the pcb, only if there aren't any other tracks routed or else you get your swiss cheese... Remco van den Heuvel. Hardware Engineer. Please feel welcome to visit our website at: http://www.fusionelectronics.org --- Willem Alexanderweg 87, NL-3945 CH Cothen email: [EMAIL PROTECTED] tel: (+31)343590600 fax (+31)343578599 --- - Original Message - From: Matt Polak [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, January 21, 2002 4:51 PM Subject: [PEDA] Autorouting or manual routing, or both? Hey folks, It seems that a majority of you are doing some very dense, high-speed layouts with 4-6 layers being quite a common occurrence. I'm just wondering how much you typically route by hand, and how much you let the auto-router whack away at. Being primarily self-taught in the ways of Protel, and with the help of a few 'older school' engineer friends here and there, I've done a number of successful design layouts thus far, but these have been relatively simple 2 and 4 layer designs without many small-pitch/high pin-count devices. I'm moving more towards laying out more high-speed designs in the near future where a lot of stuff needs to be fit into a small place, and all connect together without traces and vias meandering all over. When I look at sample six layer boards (such as the 5407 EVM reference design Motorola has released) the bussing and interconnects are extremely elegant and efficient in appearance. For fun, I unrouted the 5407 board and then let the autorouter chew on it. It immediately made 'via swiss-cheese' out of the board and created little more than a large mess. I'm GUESSING quite a bit of these sort of designs are laid out by hand, or at least pre-routed
Re: [PEDA] Antwort: AW: Lattice pld
You wrote on 17.01.2002 14:43:05: Georg, I had a similar problem, if I understand your question correctly. We have a product that used to use ispLSI2064 devices, and then we could only get the 2064A variant. Our programming software wouldn't work with it, as it detected the wrong signature. We were using an old Daisy Chain Download software for DOS, as it was only used in the production area, for final system programming on an old 386 PC. Anyway, an email to Lattice sorted out the problem - the text from them follows: Hi Steve, The 2064 and the 2064A are the same functionally but they have different programming algorithms. So in order to program these new devices you need to download the newest software ispVM System 8.2.2 if you like the ISP Daisy Chain Download software. Or you like ispVM System go for the ispVM System 9.0.1 Hope this helps -- I can't remember the exact process for programming the new device, but it is very straightforward, and no JEDEC changes were required. As they say, hope this helps. Steve. Unfortunately the 1016 and 1016E are not JEDEC compatible like 1016E and 1016EA. You have to recompile them. By the way, ispVM System9.2 is the up-to-date version to my knowledge. It's free from the Lattice server. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] SPECCTRA interface
Hi all, I did a design with blind and buried vias (7 signal layers, 3 power layers), which I had routed by SPECCTRA. All looks fine in SPECCTRA, but it won't read back to Protel (actually it will, but thousands of errors show up). I know I have to correct the drill size of vias manually, as either Protel or SPECCTRA messes this up. But as it looks like now, also the information of from which layer to which layer a via is defined gets messed up as well. To rework this manually is almost impossible. What am I doing wrong? Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: 1206 4xresistor network footprint in downloaded libraries. Where?
Hi, I can only warn you to use standard footprints without thorough check. Many of them are just useless without modification and should only be taken as examples. E.g. almost all QFP footprints have much too wide pads, and all DSUB and RJ connectors look nice, but do most probably not match the dimensions of the parts you use, as almost every supplier does them with (slightly) different dimensions. Do your own footprints wherever possible, that's the only safe method, even if it causes some work you want to avoid. Regards, Gisbert Auge N.A.T. GmbH Blandford, Simon \[BSS Audio UK\]An: 'Protel EDA Mailing List' [EMAIL PROTECTED] Simon.Blandford@Kopie: bss.co.uk Thema: [PEDA] 1206 4xresistor network footprint in downloaded libraries. Where? 20.12.2001 10:25 Bitte antworten an Protel EDA Forum Hi, Does anyone know which library the footprint for a 1206 size 4x resistor network is in and what it is called. I have downloaded just about every Protel library I can find, done text searches in the library spreadsheet for keywords network, array and resistor and still can't for the life of me find it. We want to avoid making custom footprints if we can and go with standard footprints as much as possible. Regards, Simon B. The comments expressed in this email are my own and not necessarily those of my employer. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Antwort: Altera and other
Hello Mark, we use Lattice and Altera for programmable logic. ispDESIGN Expert (Lattice) is freeware. They call it starter, but it covers the M4 family up to M4-512, the complete ispLSI1K, 2K, 5K families, and 8K up to 8840. That is more than 90% of all the devices they do. For Altera we use the MAX+Plus2 (freeware), which also covers the vast majority of their devices. The biggest Altera I ever used is the ACEX 1K100 (100K gates), and it is supported by this software. XILINX, Actel et, al. I do not use for the discussed reason, unless there is an absolute necessity to do so, which did not happen so far. I am definitely not willing to pay for software tools, which I can only use to design logic into the devices of the manufacturor supplying the software. This would be different, if I chose to use vendor-independent tools like Synario. They live only from SW, as they don't sell ICs. But so far, I get on quite well with the free development tools supplied by the IC manufacturors. Regards, Gisbert intellasys intellasys@csAn: Protel EDA Forum [EMAIL PROTECTED] i-net.netKopie: Thema: Re: [PEDA] Antwort: Altera and other 13.12.2001 23:10 Bitte antworten an Protel EDA Forum Gisbert, You make some nice products where your work. I couldn't zoom in enough to see what parts your using. I own the Lattice, Xilinx and Altera tools. None were free. Used Actel at one point. It also was not free. So, who's free tools are you using and what devices can they target? Mark You are invited to have a look at them under www.nateurope.com. By the way, do you have a name, intellasys? Gisbert That must limit your designs! Bastards... Do they want to sell ICs or software? It always makes me mad. Both, Tony, ICs and SW. Therefore, whereever possible, I implement only devices into my designs which supply development software for free. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Altera and other
You are invited to have a look at them under www.nateurope.com. By the way, do you have a name, intellasys? Gisbert intellasys intellasys@csAn: Protel EDA Forum [EMAIL PROTECTED] i-net.netKopie: Thema: [PEDA] Altera and other 13.12.2001 00:49 Bitte antworten an Protel EDA Forum That must limit your designs! Bastards... Do they want to sell ICs or software? It always makes me mad. Both, Tony, ICs and SW. Therefore, whereever possible, I implement only devices into my designs which supply development software for free. Please send all responses to the following address: [EMAIL PROTECTED] -BEGIN PGP SIGNATURE- Version: PGPfreeware 7.0.3 for non-commercial use http://www.pgp.com iQA/AwUAOr2gRcg7e58wctt6EQLy5ACghqr8dTZj/+LgybS+TDYB/nDSlRwAmgN2 PybNyfxUgoTf5bog1FXME4kQ =9EjO -END PGP SIGNATURE- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Test #2, Is this message getting through?
It sure does, Brian. :-) Gisbert Brian Guralnick An: Protel EDA Forum [EMAIL PROTECTED] brian@point-Kopie: lab.com Thema: [PEDA] Test #2, Is this message getting through? 13.12.2001 05:20 Bitte antworten an Protel EDA Forum Test #2, Is this message getting through? My last 3 posts are missing. Brian Guralnick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Find and delete Tracks without net
Hallo Waldemar, if it still is possible to go back one step to the PCB with the components to be deleted, I would suggest that you do so. Then, in PCB editor, select Tools/Unroute/Components and unroute the components you want to be deleted. Then do the update PCB from Schematic. There should be no no net tracks afterwards. Gruß, Gisbert Auge N.A.T. GmbH Waldemar Kulajew waldemar.kulajew@kuebleAn: ProtelForum [EMAIL PROTECTED] r-gmbh.de Kopie: Thema: [PEDA] Find and delete Tracks without net 13.12.2001 13:08 Bitte antworten an Protel EDA Forum Hello out there, I am currently working on a design based on an older one. There are a lot of parts in the Schematic that should disappear. After deleting them in the Schematic I updatet the PCB and found, naturely, a lot of tracks with no Net. Now here is my Problem: trying to select them with Global Edit to delete them, I discovered that these function only select the tracks who once belonged to the same net. Other No Net tracks are not touched. Is there a way to select/delete al tracks without a net? I would appreciate your help Waldemar * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Altium Total Support Brochure
You wrote on 12.12.2001 10:15:02: Bastards... Do they want to sell ICs or software? It always makes me mad. Rant off... goodnight.. Tony Both, Tony, ICs and SW. Therefore, whereever possible, I implement only devices into my designs which supply development software for free. Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Keepouts DRC
Not to my knowledge, but why would you want to do that? Gisbert Auge N.A.T. GmbH Sean James sjames@telecast-An: Protel EDA Forum [EMAIL PROTECTED] fiber.com Kopie: Thema: [PEDA] Keepouts DRC 12.12.2001 13:27 Bitte antworten an Protel EDA Forum Is there any way to ignore or bypass keepouts during a DRC? Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Altium Total Support Brochure
You wrote on 06.12.2001 06:36:49: Altium tech support is nearly irrelevant right now, since this forum is extremely helpful. The last time I used Protel support was in 1996, when I first started using the program. I haven't needed it since. I am quite sure that I would still need it if there wasn't this forum to ask. So, all most of us really need from Protel support are service packs to fix bugs. And those should be free and permanently available for download. Exactly my experience. I called their Swiss distributor a couple of times when 99SE was brandnew, but since I joint this forum every problem I came across and posted here was commented and mostly solved in a far more detailed and satisfying way than I ever experienced with any support group (applies not only to Protel). Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Protel Crashes
Hi, there is a small program called CTSPD (ftp://ftp.heise.de/pub/ct/ctsi/ctspd092.zip) that does conformity and plausibility checks on the EEPROM contents of SDRAM modules. If a module fails this check, it does not necessarily mean that it is not working properly, but that the EEPROM data analyzed by the BIOS are not as expected. You have this effect frequently with cheap no-name modules. This may lead to non-suitable SDRAM controller initialisation by the BIOS. Nice little program. Disadvantage for most of you: only German language, but delf-explaining. I had this program check SDRAM modules on Compaq Presario computers. The result was: Error, error, error, .. They seem to implement the cheapest stuff available on the market into their computers. I had a Presario PIII 500 until spring this year. Nothin but trouble. Regards, Gisbert Auge Bob Jones Digitized@maAn: Protel EDA Forum [EMAIL PROTECTED] il.com Kopie: Thema: Re: [PEDA] Protel Crashes 27.11.2001 21:03 Bitte antworten an Protel EDA Forum I too use a Compaq, although not the same as yours, and get maybe 2-5 lock-ups per week. I don't think they are Protel (Altium, whatever) related. I think they may be memory leaks or hardware related. Today, as a matter of fact I've downloaded a program called Memokit from MacAfee, suppose to improve memory leaks and memory performance and all that good stuff. I'll try to keep you posted. - Original Message - From: Jeff Adolphs [EMAIL PROTECTED] To: Protel EDA Forum (E-mail) [EMAIL PROTECTED] Sent: Monday, November 26, 2001 3:19 PM Subject: [PEDA] Protel Crashes Hello! I have had extended RAM removed from my computer thinking the RAM was bad. Computer is Compaq Ipaq, now with 64 meg of RAM, W2K. Day One: no computer crashes. Day Two: three Protel 99SE crashes. All three gave an error window starting with something like: Access violation at address 00444C65 in module 'Client99... All three crashes were in a span of 5 1/2 hours (10:15 AM EST, 11:15 AM EST, and 3:00 PM EST). Question: Could the 3 Protel 99SE crashes be from running with only 64 meg of RAM, Protel needs reloaded from numerous crashes with bad extended RAM, or other hardware problems suspected? Any guesses? Thank You! Jeff * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: router settings
Hi Mike, I have no problem with posting the reply I received from Altium to the group. I don't know why this is being made personal, anyway, it's helpful. Maybe Abd's comment gives the reason for it. But, as I learnt from this mail, there are some articles in the knowledge base I did not check before. Altium support, quote: In general you can find the reason that the Autorouter will not initialize in our Knowledge Base article #1694 (see below). If you have followed these guidelines and are still experiencing problems getting the Autorouter to start please email a copy of your file to us at [EMAIL PROTECTED] *** Item - 1694 Logged: 30-Mar-1998 Revised:12-Oct-2001 Item categories: Autorouting Products affected: Protel 98 (All Versions);99 (All Versions);99 SE (All Versions); Operating systems affected: Windows 95;98;NT; Query: Why won't my board autoroute? Details: Sometimes when attempting to route a PCB file in Advanced Route, it can remain in the Initializing shape based route pass, or stop after Initializing. Answer: Use the following points to help identify why the board will not route; 1. Check that the PCB outline has been placed on the Keep Out Layer and not a Mechanical Layer. (For example, make sure that the Keep Out Layer is used instead of Mechanical Layer 1 as these 2 layers are the same color). 2. Insure that there is some outline on the Keep Out Layer. It has been found that the outline need not be completely closed, i.e. the corners do not need to touch. Arcs are not supported in board outline on the Keepout Layer. They are ignored. This is the reason why a board outline defined by a full arc will not initialize and start routing. In the case where tracks and arcs make up the board outline, the arcs get ignored and in effect a straight line is used to close up the gap of where the arc was placed. Generally, in place of the arc there is a straight line assumed from and to the nearby tracks on the Keep out layer. 3. Enable all the layers that are needed for routing the PCB in the Design Rule » Routing Layers setup. When setting up the routing layers you will need to keep in mind that the present autorouter requires either the top or bottom layer to be enabled in the Routing Layers setup. Otherwise you will receive the error message Design Rule Error: no pads defined on any layers. Pressing OK will close down this error and it will appear to want to start autorouting by prompting you to change the routing grid to 0mil. The end result is that the autorouter will be unable to initialize. 4. Avoid using net names with hyphens, spaces; characters other than the alphabet and numbers. 5. Maintain net names less than 10 characters (pre P99SE only). 6. Maintain pad designator names to 4 characters or less (pre P99SE only). 7. In Route 98, the router requires all parts of the board to be within a 32x32 inch region from the absolute workspace origin (not the set-able current origin). Note that the coordinates on the Status bar display the distance from the set-able current origin, so if you are not sure reset the origin. To reset the origin select Edit » Origin » Reset from the menus. In Protel 99/99SE, the autorouter workspace is the same as the PCB workspace of 100x100 inch. 8. Avoid placing any polygons prior to routing. This includes split planes. 9. Polygons that are placed on the top or bottom overlay, or mechanical layers can prevent the autorouter from initializing and routing the PCB. This includes polygons that have been included in a footprint. You will need to edit the footprint and remove the polygon. 10. Locate and remove polygons that are not visible. See Item 2434 for more details. 11. Avoid placing components on a grid smaller than 1mil. It is recommended that components be aligned to a 5mil grid. On high density PCBs, too many components, tracks and other primitives placed on fractional grids (that is less than 1mil grid) can cause the autorouter to find too many contentions. A message similar to One or too many contentions have been found.. The only remedy to this situation is to place components and any routed tracks on at least 1mil grid. 12. Avoid placing tracks, arcs, etc on the multilayer. The router fails to start when it finds primitives other than pads/vias on the multilayer. 13. Check the PCB against the maximum capabilities of the autorouter listed in Item 665. This includes the number of components, pins, etc. * You can access our Knowledge Base at http://www.protel.com/kb/default.asp. There are a number of articles that focus on the Protel Autorouter and its use. End quote. Regards, Gisbert Auge N.A.T. GmbH Mike Ingle
Re: [PEDA] Antwort: Reply1 MS versus Linux
I can back that statement, Abd ul-Rahman. Last week I received a mail directed only to me from Protel support concerning the setup of the router. I had not turned to them directly; they had been reading my postings on this thread. Regards, Gisbert Auge N.A.T. GmbH Abd ul-RahmanAn: Protel EDA Forum [EMAIL PROTECTED] Lomax Kopie: marjan@noho.Thema: Re: [PEDA] Reply1 MS versus Linux com 23.11.2001 21:49 Bitte antworten an Protel EDA Forum At 10:24 AM 11/23/01 -0500, Fred A Rupinski wrote: Has anyone seen Protel reply directly to this forum? Yes, on 11/20/01, from Samual Sattel, regarding Protel usage I did not find that post in my archive. I suspect that Mr. Sattel may have written directly to Mr. Rupinski in response to a Rupinski post on this list. That is not uncommon. Protel, I was informed perhaps two years ago, has a policy that employees do not post to this list except for Protelcsc, Protel Customer Service Center, which occasionally pops in when they can easily clear up some mystery that we have not handled for ourselves within a reasonable time. Exceptions are quite rare. We are pretty sure that very many employees do read this list, though perhaps fewer than was the case at one time, and perhaps once in a while an employee gets carried away and responds directly. I have been asked by an employee on occasion to convey some information to the list, a way around the restriction. At one time Protel and the users had a fairly serious adversarial stance toward each other; I think that the rule originated at that time. It was far too easy for flame wars to start. There would be other reasons as well; it can take a lot of time to write thoughtfully and it is perhaps not the best usage of employee time. I know that Mr. Foley of Accel wrote on the Accel user support list with a serious anti-time-wasting message directed at the users as well as, perhaps, at employees. But we know what happened to him, I don't think he is in the CAD business any more. I can say that there were many Accel customers who, while they were insecure about the future of the product when Protel took over, nevertheless were not sorry to see Mr. Foley go. Obviously, it is up to the users and their companies what is a waste and what is not. However, I *would* recommend a certain level of participation by certain kinds of Protel employee. Imagine how we would feel if a development engineer were actively asking us questions and reflecting on the answers. Relations have improved to the point that serious rudeness from a few users would be pretty strongly damped by the user community. Rules for employee participation could be developed, such as, for example, that employees would not respond to flames, that employees would need to be authorized by Protel to participate here, and limits might be placed on what the employees could reveal. I do think, however, that the value of secrecy is vastly overblown. Some matters properly remain secret, but secrecy clearly hampers communication (well, duh!), and good communication between the developers and users could greatly increase the pace of program improvement. On the other hand, there are also other ways that communication could be improved. A user panel is one possibility that has been mentioned; these users would be under NDA so the secrecy issues would not be such a problem; but they would be allowed to let the user community know that they were in communication with Protel and could serve as a conduit for surveys, etc.
Re: [PEDA] Antwort: Antwort: Autorouter
Steve, same here. Even medium designs won't route and end up with an unable to initialise. Does anyone know a reason and workaround for this effect? Regards, Gisbert Auge N.A.T. GmbH Steve Wiseman steve@steves-houAn: Protel EDA Forum [EMAIL PROTECTED] se.org.uk Kopie: Gesendet von:Thema: Re: [PEDA] Antwort: Autorouter Steve Wiseman,SJC,57852 4 [EMAIL PROTECTED] 16.11.2001 19:44 Bitte antworten an Protel EDA Forum On Fri, 16 Nov 2001, Tim Fifield wrote: Ivan, I'm also interested in what button you push. Same here. I've got Specctra, so I don't care so much about the ARs inability, but I've just convinced a customer of mine to buy Protel so they can do their own maintenance of the board I've just done for them - it doesn't require Specctra, but to hand-route it would be very very dull. I suspect I'll need to know answers pretty soon. (My experiences with the autorouter normally end up with an unable to initialise, or a design where the router seems to paint itself into a complete no-hope situation, and gives up / stops trying. All very depressing). Specctra, of course, may not be available as a standalone product - I have little love for Cadence. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Protel usage
Hi, my use of Protel is - Schematic yes - PCB yes - Powerprint no - CAM Manager yes - Simulator no - Autorouter seldom - 3D Viewer no - PLD no - Arrange Components no - Autoplacer no, much worse than AR - PCB Miter no - Signal Integrity no - Database Linkno Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Autorouter
Hi Tim, we route large designs with SPECCTRA. Gisbert Auge N.A.T. GmbH Tim Fifield tfifiel1@irfAn: Protel EDA Form [EMAIL PROTECTED] .comKopie: Thema: [PEDA] Autorouter 16.11.2001 15:07 Bitte antworten an Protel EDA Forum Just curious... Does anybody use the 99SE autorouter for large PCB designs? Do the majority of board designers do everything manually? I don't even bother with the autorouter anymore, it's to messy. Perhaps I'm not setting it up properly. What do you people do? Tim Fifield * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Autorouter
Ivan, what buttons do you push, i.e. what rules did you find significant playing around with? Just being curious ... Regards, Gisbert Auge N.A.T. GmbH Bagotronix Tech Support An: Protel EDA Forum [EMAIL PROTECTED] techsupport@bagotKopie: ronix.comThema: Re: [PEDA] Autorouter 16.11.2001 16:06 Bitte antworten an Protel EDA Forum How large is large for you? I use the 99SE autorouter for my large designs, but not for small designs. It takes a lot of practice and trial/error to figure out how to set up the autorouting rules for each board. And each board may take different rules. You just have to have patience. Typically I will spend a half day tweaking rules and testing them with trial routing runs. After you get an acceptable run, you will need to do some manual cleanup. Yes, it doesn't seem very productive. But it is still faster than routing the whole thing manually. When I say large, perhaps a better metric is difficult. Our DOS Stamp is a 6-layer PCB with only 10 ICs on it, but it is very small (2.6 x 2 in.) and has SMT parts on both sides. Not a large design, but quite difficult given the small area and parts on both sides. The router does a good job on this board with the right rules. Another board I did recently was a PC/104 form factor 486-class custom SBC. 8 layers (2 power, 1 ground, 5 signal), 2 large PQFP208 devices and 12 other ICs. The router did a good job on it. An afternoon to tweak the rules, and 30 minutes to clean up afterwards. If you have lots of replicated circuitry with parallel, ordered busses, you can probably do better with manual routing. But if the circuitry lays out randomly, as most of mine do, autorouting is a more productive choice. The pinouts of most of the chips and the placement of I/O connectors are constraints you cannot do anything about. If you have PLD/FPGAs, you can control the pinout of these devices somewhat. I tend to let the PLD/FPGA fitter do pin assigment, because I want the best utilization of chip resources. But the more large chips you have in your design, and the more vendors of chips, the more random your layout will be. Work with the router for a while. Everything in autorouter lore says it should be a pushbutton process. They don't say how many buttons you have to push to get good results! Also, keep in mind that an autorouter will never be as smart as you, only faster than you. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Tim Fifield [EMAIL PROTECTED] To: Protel EDA Form [EMAIL PROTECTED] Sent: Friday, November 16, 2001 9:07 AM Subject: [PEDA] Autorouter Just curious... Does anybody use the 99SE autorouter for large PCB designs? Do the majority of board designers do everything manually? I don't even bother with the autorouter anymore, it's to messy. Perhaps I'm not setting it up properly. What do you people do? Tim Fifield * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Multi-Part Components
Wow, thank you, Colin, I did not know about this feature, and it's smart. Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: vias vs. pads
works also fine in Protel. G. Auge Sean James sjames@telecast-An: Protel EDA Forum [EMAIL PROTECTED] fiber.com Kopie: Thema: Re: [PEDA] vias vs. pads 13.11.2001 15:23 Bitte antworten an Protel EDA Forum also don't have thermal reliefs like pads. (This works in PCAD, though). Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, November 12, 2001 11:09 PM Subject: [PEDA] vias vs. pads The differences between vias and free pads are artificial. Vias in Protel 99SE are essentially free pads with the following limitations: (1) Vias cannot have names (2) Vias cannot be any shape except circular. (3) Vias cannot exist on a single layer only. (I'm not sure about this, it is conceivable that one could configure a buried/blind via with one layer only. But my expectation would be that it would not work, or if it works it would set up many bugs, being thoroughly unconsidered and untested, I would think. Pads can do all of the above. on the other side, free pads are vias with the following limitations: (1) Free pads cannot be blind or buried, i.e., if they have a hole, it goes all the way through the board. (2) If they are in a footprint (i.e., not free) their net assignments are affected by netlist load. Give us blind/buried layer attributes for pads and free pads will do everything that vias will do, plus they can be named, which means that it is easy to assign special rules to them. Vias, however, should be maintained for backward compatibility and the occasional via that one wants to be part of a footprint -- and/or a way should be introduced to cause a pad to behave under netlist load and DRC like a via. Perhaps a via checkbox. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: ATS - PIGS MIGHT FLY
Don Ingram wrote: I don't accept that the solution to this is to move to another product. We have spent a hell of a lot of blood, sweat tears over the years while trying to turn out a living with this product. That is exactly it !! Perhaps we should all buy some Altium shares and show up at their general meeting of shareholders. :-) Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Bus in schematic
Hi Yuri, it cannot be done. What you can do is define a bus like SIGNAL[1..10] and place text strings on the wires showing the names originally wanted (DATA1-8, CLK,GND). Be careful with adding power signals to a bus! This may be a cause for serious trouble. Regards, Gisbert Auge N.A.T. GmbH ElectronTrad e (info)An: Protel EDA Forum [EMAIL PROTECTED] info@electraKopie: de.ru Thema: [PEDA] Bus in schematic 30.10.2001 15:35 Bitte antworten an Protel EDA Forum Dear Sir, My customer want to use bus with wires miscellaneous names on schematic. Is it posible? For example, in one bus must be next wires: Data1 Data2 . . . Data8 CLK GND How to create this bus correctly? -- Best regards, Yuri V. Potapoff Technical Director ElectronTrade, Ltd. 8 Ukrainsky boul., Moscow, 121059, Russia Tel: +7-(095)-243-72-50 Fax: +7-(095)-243-44-16 E-mail: [EMAIL PROTECTED] http://www.electrade.ru * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: True statement?
*** Todays forums are sponsored by Ian Martin Limited Engineering/Technical Placement Specialists www.ianmartin.com *** Hello, just another 2c: Try Mentor's Integra Work Station package, if you are looking for trouble. g Never saw anything comparably illogical and arbitrary. Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: Conflicting footprints and decals
*** Todays forums are sponsored by Ian Martin Limited Engineering/Technical Placement Specialists www.ianmartin.com *** Hi Brian, this will not be of much help for you, but consider like many of us co-Protel-Users not to rely on Protel libraries, but to create your own. You will have to check Protel library entries anyway and rework them according to your needs. Regards, Gisbert Auge [EMAIL PROTECTED] za An: Protel EDA Forum [EMAIL PROTECTED] Kopie: 03.10.2001 Thema: [PEDA] Conflicting footprints and decals 09:42 Bitte antworten an Protel EDA Forum Hi All, May be I missed this thread, but needed to lay out a pcb with amongst others two low power 5 volt regulators. In addition needed a TO-247 footprint and opened the the Transistors.lib as well as PCB Footprints.lib libraries. If you browse the two libraries and examine the TO92(A or B or C) in the Transistors.lib and the TO- 92(A or B) in the PCB Footprints.lib that positions of pad 1 are reversed. The same applies in the schematic libraries. I selected a LP2950CZ5.0 from the NSC Power Supply Circuit Library and a Voltreg from the Miscellaneous library and the Input and Output pins on the two decals are also reversed. A good way to destroy some regulators! I am using Protel99SE /SP6 Thanks, Brian Brian Merskey Institute for Maritime Technology Phone: (2721)7861092 Fax: (2721)7862189 E-mail: [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Spectra Interface to 99SE
*** Todays forums are sponsored by Ian Martin Limited Engineering/Technical Placement Specialists www.ianmartin.com *** Gordon, there is (was?) a special offer in connection with an OrCAD PCB license. Buy OrCAD, though you don't need it, and get it in a package with SPECCTRA for about $15K (without FST option, though). As far as I know, FST option for this package is another $20K. There is no limitation of SPECCTRA, i.e. you can strip off the OrCAD part (actually I didn't install it at all) and still have a fully functional SPECCTRA. This was a special offer for American customers, but we achieved in negotiations with Cadence that their German distributor was able to sell the package at a comparable price. Regards, Gisbert Auge Gordon Price An: 'Protel EDA Forum' [EMAIL PROTECTED] GordonP@LoroKopie: nix.com Thema: Re: [PEDA] Spectra Interface to 99SE 01.10.2001 19:03 Bitte antworten an Protel EDA Forum Mike, Thanks for the answer. This is also to Ivan who asked me a question about how large my design is. The answer to that question is that it is a small physical design but TOO DENSE FOR PROTEL'S ROUTER.(1000 traces, 1500 vias) It is a PCI card with a couple of DSP's and 12 layers and a lot of 16 and 32 bit data busses. It really is not a large part count, but has a lot of surface mounts. We are experimenting with some new CADENCE STYLE footprints on surface mounts that may help out the auto-router by having adjacent thru-hole pads next to each surface mounted fill area(pad). We did this on BGA's and it really helped Protel's router out. The Protel auto-router just gives up completely part way through the final routing stages, maybe 95% done. One of my big beefs with Protel's router is that most of the rules are not actually followed when established, but only flagged for DRC review. At this point, everything is usually so screwed up that you can't manually find a solution either. Mike, how did you buy SPECTRA without getting the full dog and pony show that they try to jam in your ear?? They want $50k per year just to get started. Is there a back door way to get SPECTRA at a more reasonable price?? Mike, I agree about a good engineer. Unfortunately, I am both the engineer and the designer and have to live with my own messes. We are an RD shop and our company makes me wear a dozen hats or so. I even have to figure out the device driver software (C) and HDL glue to boot!(usually Verilog) -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED]] Sent: Friday, September 28, 2001 8:22 PM To: Protel EDA Forum Subject: Re: [PEDA] Spectra INterface to 99SE Gordon, I have to respond to this one. We are designing high speed panels for the Telecom industry. Some of our boards are as large as 20 inch square, several thousand components, multiple processors, FPGAs both sides, BGAs etc, I/O count for connectors as much several thousandall done on Protel less the routing. We have invested in Spectra for routing. but I am confident that you probably have not exceeded Protel's limitations but the limitation of Protel's router, It does not work period. ( I know some of you guys are going to blast me for this but until you walked both sides with Spectra and Protel, Please do not respond)I take exception to your comment about buying a real product like Cadence, which will not give you any more capabiltity than you can buy in a package costing 1/5 less. I will also add that to make Protel a real product for
Re: [PEDA] Antwort: FYI: addresses @ ib-systems (was spam trawlers)
Hello aj, in a recent post to PEDA you wrote You simply add the discalimer that by sending ANY further email to your address they have legally agreed to the terms in your following statement (I'm not posting it unless someone really wants it as a template, in which case send a private email...) I am very interested in receiving such a disclaimer. Please send me a copy. I tried to send this mail to your mail account given in your mail header, but it bounced. TIA, Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: ibsystems info
Hi aj, thank you for the text. I tried to answer you directly, but it bounced again. Your server is refusing to accept mail to your address. ... while talking to mailhost.columbus.oh.ameritech.net.: RCPT To:target address 550 you are not allowed to send mail to target address 550 target address... User unknown The address used is okay, I doublechecked. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Spam trawlers in this group
Hi, there seems to be a coincidence in receiving spam (with PEDA as subject !!) and posting to this group. After I sent some posts during the last fortnight, I received about half a dozen of spam mails, half of them from .au servers, the rest from elsewhere. Someone seems to collect addresses for advertising. One example, where one might argue if it's spamming or not, is the EDA Tools Cafe News I received twice since last week. I did not ask for it, nor am I interested in all the US job offers it contains, nor in the weak rest of it. So I count this under spamming also. Quote of Mr. Abd ulRahman: They (Techserv) do offer advertising to the list -- no one has purchased it, it was pretty expensive last time I checked; but such mail would come as a normal post to the list.) Hopefully they stick to their steep prices, as I would think it as really annoying if we also would receive authorized spamming in the future. Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: tenting vias
Hello Ivan. tent the vias. You will most probably risk short under the BGA if you don't. By the way, I never understood why many PCB designs come with open vias, unless you want to use them as testpoints. Regards, Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Preview Setup
Hi all, is it possible to make global changes to the properties of a layer set in Print/Preview? It is somewhat annoying to have to make changes to layer settings 25 times for one set of layer definitions. Regards, Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: duping parts in a multi-part component ??
I do the parts just as you describe, and it works fine. In detail: - Place the 1st part (the one you completed already) on the screen - Mark it by selecting the complete area and do Edit/Copy - Click on a reference point - Place the 2nd part on the screen ( button). This screen should still be empty, just showing the grid. - Click into the empty window (maybe that is the secret!) - Edit/Paste should bring the copied part to the screen. Place it. - Repeat for the remaining parts to be defined. Please don't think I want to play a joke on you, because I explain simple steps in such detail. But, as the Copy functions without problems, it must be a simple thing that you are doing wrong. Regards, Gisbert Robison Michael R CNIN An: 'Protel EDA Forum' [EMAIL PROTECTED] Robison_M@craneKopie: (Blindkopie: Gisbert Auge/NAT) .navy.mil Thema: [PEDA] duping parts in a multi-part component ?? 15.08.2001 16:05 Bitte antworten an Protel EDA Forum hello, i've set up a 6-part component in my component library and i built up the first part and now i want to copy this first part into the second part and then edit the pin numbers and remove the vcc and gnd, but i can't figure out how to copy the first part into the second part. i tried to just drag around the entire first part and do a copy/paste but that won't work. thank you, miker * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Antwort: Protel 99 cannot auto-route BGA components
Hi Gordon, could you possibly share your knowledge with the forum members? There are more participants interested in this thread (like me :-) ). TIA, Gisbert Auge N.A.T. GmbH Gordon Price An: 'Protel EDA Forum' [EMAIL PROTECTED] GordonP@LoroKopie: (Blindkopie: Gisbert Auge/NAT) nix.com Thema: Re: [PEDA] Protel 99 cannot auto-route BGA components 14.08.2001 01:32 Bitte antworten an Protel EDA Forum Hi, I use 256 pin DSP BGA's and have been there and got the hat and shirt!! Call me and I will be happy to explain the different ways to solve your problems. R. Gordon Price Director of Research Engineering Loronix Indormation Systems, Inc. Del Mar CA (858) 523-9424 -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Monday, August 13, 2001 7:58 AM To: proteledaforum Subject: [PEDA] Protel 99 cannot auto-route BGA components I have been unable to autoroute a 10 layer design which has 2 fine grid BGA packages. Protel support has not been able to assist me and has cause a 3 MONTH delay of this design. Protel's auto-router simply locks-up or does not initialize. The autorouter give no reason for the problem and Protel is either unwilling or unable to address the problem. Therefore, I am under the impression that there is a major software problem with respect to the autorouter and BGA components. Has anyone else seen this problem? If any other user has had this problem or know of a fix, PLEASE contact me ([EMAIL PROTECTED]). Thanks you for any feedback. Loop. Posted from Association web site by: Gerard Vanderloop * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Logo's for FCC, UL and CE ?
Jon Elson wrote: Right, the CE requirement is that all electrical components must bear the CE mark at the full accepted size (I think it is around 5 cm?). This includes EVERY component, including 0402 resistors! There are no exceptions permitted, and any unit bearing even one such unlabeled or improperly labeled component can be seized and destroyed by customs agents. Supposedly, there are even criminal penalties in Germany, maybe other places, too, for such violations! Very practical regulations! Jon (happy to live in the US) Funny, on most of my equipment the CE mark (which indeed is obligatory in the EU, not only in Germany) is just printed on a label fixed to the box or packaging. Size depends on size of the label. Only the form is to be genuine. I place a small CE mark (in copper on top or bottom layer) on all PCBs I do. It does not comply 100% to the official mark, but to 95%, and at a size of 3mm to 10mm, depending on available board space, nobody will notice if not viewed under a microscope. If anyone is interested, drop me a line. So I am sorry, Jon, but you should inform yourself better before issuing statements, that may read funny, but unfortunately do not contain real information. Gisbert (happy to live in Germany) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Logo's for FCC, UL and CE ?
Your description is more precise than mine. Thank you. Gisbert Heiko Vachek [EMAIL PROTECTED] on 09.08.2001 15:45:19 Please respond to Protel EDA Forum [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] cc: Subject: Re: [PEDA] Logo's for FCC, UL and CE ? Not quite correct, Brad. It is not illegal, to place a CE mark on a power supply, it only is not necessary, as the power supply will not work for its own, but only together with e.g. a PC. The complete system has to carry the CE mark, but system designers often ask for the components they implement to carry a CE mark also, in order to get proved that the single components (boards, power supply, drives, etc.) passed an EMC test. Regards, Gisbert Auge N.A.T. GmbH That also is not the whole truth. CE Mark is mandatory for every Part that is sold to any end user inside the european community. So, a PC PSU must carry a CE mark if Customers (end users) can buy it as a separate unit. Consequently, this applies to every PC component that is sold as retail version. EMC testing for these components is made in a typical environment. Which leaves the question what is typical. So in doubt the system integrator has the responsability that his system is CE conform. All CE marking of components that are not sold in the end user market and that are not subject to a particular european standard is a misuse of the CE mark and therefore illegal. There are clear standards and laws about the application of the CE mark. regards, Heiko Vachek elektronik 21 GmbH [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Bug when opening Protel
Thank you, Konrad, that's a nice work-around. Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Which library is used in UpdatePCB
Hi, I also think it works like Andrew describes, for instance as for my experience. I came across this behaviour already in version 2.8, when I was merging libraries from different developers. But, for normal working situations why not organise libraries in a way, that there are no different footprints with the same name in the PCB libraries? This avoids any unwanted effects of this kind from the very beginning. Regards, Gisbert Auge Jon Elson [EMAIL PROTECTED] on 16.07.2001 21:23:53 Please respond to Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] cc: Subject: Re: [PEDA] Which library is used in UpdatePCB Andrew Ircha wrote: You're close but not quite there. I was making modification in one library, hiting UpdatePCB (which presents as a button in the explorer panel), and instead of putting my new, freshly changed footprint into the open PCBs, it was taking a footprint with the same name *from a totally different library* and using that instead - it didn't appear to be taking other footprints. It was ignoring my hard work :-| Yes, I think it searches the names on all open libraries in order, and takes the first match of that name, whether it is the newly edited part or not. Definitely a poor way to do things. In so many other cases, if there is a question about which thing you intend to change, you get a dialog box to select the right one. This is why it is a good practice to open libraries, place the parts, and then close all the libraries, and make a project library from the placed parts. I think I'd understand Protel updating *all* open PCBs with my new changes, even if it isn't a great thing to do, but it wasn't even doing that. It was taking the altered footprint's name, and updating my open PCB with a footprint from another library which happened to have the same name. Nasty. Yes, at least this behavior should be thoroughly documented, and suitable warnings given that this can cause unexpected results. But, your hard work isn't lost. It is still in the library part that you modified. If you close the other libraries that have interfering part names, and do the update again, it will work right. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Bug when opening Protel
Hi, I just noticed a bug which was new to me so far. If you open Protel and click on the little minimize window button in the upper right window corner while the files are loading, and then renew the normal window size some time later, the entrance picture Design Explorer 99 SE does not close, although the database has been opened in the background. No way to make it disappear. You have to close the application completely and start it anew (and keep the window open during file loading time). Not really serious, but a bug. Regards, Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Matched Net Length Rule
Hi all, in the definition of the rule for Matched Net Length there is an item called gap. Does anyone know what this is supposed to be and how to alter it? In the respective properties window there is no such item. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] [PROTEL EDA USERS]: Global edit
Just another question in the same context. Is it possible in SCH to do a global rename of net labels with all different names, in order to add a letter to them? Example: I want to rename signals ABC, DEF, GHI, ... to Z_ABC, Z_DEF, Z_GHI, ..., without having to change every signal name manually. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the reply command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
Re: [PEDA] [PROTEL EDA USERS]: Database Linking...a suggestedimproveme nt
We disregard it. Gisbert Coleman, Tim [EMAIL PROTECTED] on 09.03.2001 09:51:03 Please respond to Protel EDA Forum [EMAIL PROTECTED] To: [EMAIL PROTECTED] cc: Subject: Re: [PEDA] [PROTEL EDA USERS]: Database Linking...a suggested improveme nt Hi, To answer your question: Does anybody else actually use database linking or is it largely disregarded? I haven't yet worked out what to use it for so I have disregarded it. However, I am keen to know how to get the most from this tool so tell me, what do you use it for? Anyone? Cheers TC -Original Message- Fr From: Linden Doyle [mailto:[EMAIL PROTECTED]] Sent: Friday, March 09, 2001 2:11 AM To: Multiple recipients of list proteledausers Subject: [PROTEL EDA USERS]: Database Linking...a suggested improvement Hi all, Just a quick suggestion to add to the list concerning the database linking functions. I know they're s-l-o-w and a little extra speed would'nt go astray but could we please have some indication that the process is proceeding? At the moment my computer is busy liking which means I can't use Protel for anything alse while this is going on. Maybe a percentage completed counter or bargraph? I'm hitting the OK button when I think of it to see if its reached the end. Does anybody else actually use database linking or is it largely disregarded? Best Regards, LINDEN DOYLE Product Development Engineer Zener Electric Pty Ltd [EMAIL PROTECTED] Ph: +61 2 9795 3600 Fax: +61 2 9795 3611 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?bodyleave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Does newest version of Orcad import well into Protel...
Confirmed. I made the same experience when translating back from Specctra. Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel default Vcc hidden power pins
I would suggest to drop this feature completely. It is a relic from the times when a chip had a power supply of 5V, and that was it. Abd ul-Rahman wrote: The feature remains almost as useful as it ever was. Further, it should be considered that there is a huge base of legacy designs which would be wrecked if Protel no longer supported hidden pins. In addition, the ability to load OrCAD schematics would be trashed. *But* it would not be difficult to provide tools that would make the use of hidden pins less hazardous, or the elimination of hidden pins in a design easier. On second thoughts, I agree. We tend to look at things under a point of view which is mainly influenced by personal experience, and so do I. The fact of not being able to use the standard library parts (mainly TTL) without having to rework the power pins (unhide them and replace them to some place where they can be wired manually a n d still result in a readable schematic) is not really important for my kind of designs. As most of my designs are processor boards with several different telecom parts (framers, etc.) the percentage of parts I can take from a pre-defined schematic library provided by Protel is less than 5%. This is not because I don't like the way parts are defined in the Protel libraries - the parts I need to place simply are not there. Parts I need to define myself never have hidden power pins, and, I agree, it is usefull to define a special part within a component definition which carries only power pins, and another one, which shows possible no-connects. Regards, Gisbert Auge N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Strange behavior on unconnected pins
Hi Terry, sorry, but I do not at all agree with you. As for showing no connect pins - it is about as useful as adding a few ficticious components to the schematic and marking them as not fitted and nothing to do with the design? These pins are not fictitious and have everything to do with the design. May be it is not absolutely necessary to show them in all cases, but it is helpful for checks. For example I defined some weeks ago in a library a northbridge which exists in 2 versions: with and without an additional PCI bus connection. Some 60 pins of the 480 pin BGA are defined as NC in one version, as signal pins in the other. I find it explicitly useful to show them as unconnects in the version without second PCI bus. Elsewhere in this thread Ivan Baggett said [Off topic] I also hate assembly language code written with macros. Same concept (hidden code). It makes it very difficult to figure out what's really happening. This is quite telling, and actually exactly wrong - macros and hidden code make it easy to figure out what is going on - that is the whole point of using them and the founding principle of all Object Oriented Languages. I am just a hardware designer, so I would never dare judging the founding principle of Object Oriented Languages. But I spend hours with a logic analyzer searching for strange effects happening with microcontroller port pins, just because my software colleague swears he never touched that pin setting in his code, but it changes state when it should not. He was right, the code he had written himself was clean, but the macros written by someone else touched it. Macros and hidden code make it easy to figure out what is going on? I doubt it, as far as hardware-related software is concerned. But may be you did not notice that Ivan was talking about assembler. IMHO this is not an Object Oriented Language. ;-) Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Cadence has been watching!
Cadence runs a SPECCTRA forum under [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Solder Paste (further suggestion added)
Hello Ian, stupid me. I get your point. Of course you are right. Sorry for not thinking twice. Regards, Gisbert Auge * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
