Re: [casper] Multi-instance hashpipe "pktsock" on single interface

Hi, Wael, I think I know what's going on here. You don't say how the reported data rate differed from expected, but I suspect the reported data rate was higher than expected. Packet sockets are a low level packet delivery mechanism supported by the kernel. It allows the kernel to copy

Re: [casper] Dropped packets during HASHPIPE data acquisition

Hi, Mark, Sorry to hear you're still getting a segfault. It sounds like you made some progress with gdb, but the fact that you ended up with a different sort of error suggests that you were starting hashpipe in the debugger. To debug your initial segfault problem, you can run hashpipe

Re: [casper] Multi-instance hashpipe "pktsock" on single interface

Hi Wael, I currently have other issues with pkt_sock, but I have multiple instances working with the standard socket version of hashpipe (an older version) so maybe I can help. It's possible that I may run into the same issue with pkt_sock later on though. I don't think I've had this particular

[casper] Multi-instance hashpipe "pktsock" on single interface

Hi Folks, Hope everyone's doing well. I have an application I am trying to develop using hashpipe, and one of the solutions might be using multiple instances of hashpipe on a single 40 GbE interface. When I tried running 2 instances of hashpipe I faced a problem. The data rate reported by the

Re: [casper] Dropped packets during HASHPIPE data acquisition

Thanks for the response John! Yes, I have ensured that those numbers add up. I did it a little while ago, but I just verified it to make sure. The PKT_UDP_SIZE macro includes both the UDP header as well as our packet header (each 8 bytes) which we do not want included when copying the payload

Re: [casper] ADC ROACH2 clock signal, or Function generator

With response to the previous question regarding clock source: Dan, do you find a difference in feeding of the clock source, be it a sine wave -or- a square wave ? For example, do you see any increase in S/N or sensitivity when fed by a square wave as opposed to a sine, and when clocking is fed

Re: [casper] ADC ROACH2 clock signal, or Function generator

Hi Dan I appreciate your recommendation, now I understand better, I think very expensive equipment is not necessary. Well, I would like to have my portable system and I didn't know which generator to use as a clock signal. Cheers Javier Ulloa El mar, 1 dic 2020 a las 13:52, Dan Werthimer ()

Re: [casper] ADC ROACH2 clock signal, or Function generator

hi javier, most casper ADC boards want a 0dBm sine wave. square wave is fine too. with frequency at the adc sample rate, or perhaps 1/2 sample rate if the ADC is interleaved. i like the small ~$500 synthesizers from DS instruments:

[casper] ADC ROACH2 clock signal, or Function generator

Hello everyone, I hope you are well. I am working with a ROACH2 and I had a question, what clock signal do you use for your ADC, and I would like to know if you know of any signal generator that is portable? best regards Javier Ulloa -- You received this message because you are subscribed to

Re: [casper] Wideband FFT using Xilinx blocks as primitives

Hi all, Sorry for the late follow-up. I wanted to add to Jeb's comment: The FFT we are using on the RFSoC is 16x4096 meaning it processes 16 complex samples each clock and runs at 512 MHz. We used the Xilinx SSR FFT available in System Generator versions 2019.1+. It can be configured for a

[casper] 32 port 100Gbe switch for $1400

dear casperites, if you are seeking a 32 port 100Gbit ethernet switch, terabit systems has arista DCS7060 for $1400. these are "used", but the one we bought looked new, and had arista packaging. we've bought a few switches from daniel at terabit and all have worked well so far. they test every

Re: [casper] Dropped packets during HASHPIPE data acquisition

Hi Mark. Spelunking through the hashpipe_pktsock.h header file I see that #define PKT_UDP_DATA(p) (PKT_NET(p) + 0x1c) In your code you posted earlier, you have this: memcpy(dest_p, payload, PKT_UDP_SIZE(frame) - 16) // Ignore both UDP (8 bytes) and packet header (8 bytes) Have you verified

Re: [casper] Dropped packets during HASHPIPE data acquisition

Hi David, Hope everything is fine. It's okay if you haven't seen it yet or forgot, but I'm still struggling with this issue. Would you mind giving me some thoughts on it if you have any? Here is the issue again, along with a summary of what I did to catch you up, just in case you need it: I was

[casper] Question on Sync_gen block

Hi all, I'm playing with the tutorial 3 on a roach-1 board, and trying to understand the sync_gen functionality, I have the Caper Memo #25, and the first question that I have is, how do I know or what effect can I expect if the sync_gen is not working with the proper values?, and the second one,

[casper] SNAP 10G CPU Interface ("tapcp") corruption fix

Howdy all, HERA (and other users) were seeing flaky casperfpga transactions when doing SNAP board control over 10GbE. I'm not sure who else uses SNAPs this way, but after some playing around I believe the three most recent commits at https://github.com/realtimeradio/mlib_devel/tree/snap-debug

Re: [casper] Wideband FFT using Xilinx blocks as primitives

Thanks guys :) On Thu, Nov 19, 2020 at 9:30 AM Jeb Bailey wrote: > Check out the Xilinx SSR FFT block in the system generator blockset. It > will make timing on the ZCU111 in 8x4096 at 512 MHz and is very efficient. > They also have and HLS SSF FFT that isn’t quite as performant (but has >

Re: [casper] Wideband FFT using Xilinx blocks as primitives

Check out the Xilinx SSR FFT block in the system generator blockset. It will make timing on the ZCU111 in 8x4096 at 512 MHz and is very efficient. They also have and HLS SSF FFT that isn’t quite as performant (but has public sources. It is in the Vitis IP library on github. We are using the

Re: [casper] Wideband FFT using Xilinx blocks as primitives

Hello Morag, AFAIK, Xilinx's FFT IP block only accepts a single block at a time. I think that was a large part of the reason why there's a CASPER FFT in the first place - because we needed multiple samples at once. We have used the Xilinx core in narrowband designs in the past - KAT-7's

[casper] Red Pitaya Black Friday Sale

Just noticed -- Red Pitatya are having a sale... https://www.redpitaya.com/Catalog Cheers Jack -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to

[casper] Wideband FFT using Xilinx blocks as primitives

Hi all, Has anyone ever put together a wideband FFT (i.e an FFT that accepts multiple demuxed samples per FPGA clock cycle) using the Xilinx sysgen FFT block? Looking at the docs, it seems the IP core can't be configured to accept multiple parallel inputs (but I could be wrong), so one would need

Re: [casper] Timing issue with System Generator

Hello Idir, Do you have the SLX file? Can you share which version of matlab that you're using? I can possibly take a look tomorrow. (Email me directly if you don't want to share it in a public space.) Regards, James On Mon, Nov 9, 2020 at 5:49 PM Idir Mellal wrote: > Hi James, > > Thanks

Re: [casper] Timing issue with System Generator

Hi James, Thanks for your answer. I do not use a CASPER. I am using a ZCU102 platform. For the frequency, you're right. The initial period was 10ns, but I didn't get the expected response. So I started changing the frequency. Please do not hesitate if you have any other suggestions. Best

Re: [casper] Timing issue with System Generator

Hello Idir, It's been a while since I've played around with this, but it looks as though you've chosen some fairly strange settings there. We don't usually manipulate the settings in the Xilinx Sysgen block directly - it's usually done through one of the CASPER yellow blocks - depending on what

[casper] CASPER wiki / SSL obsolescence

Hi CASPERites, Somebody helpfully pointed out to me that the latest Firefox updates prevent access to the CASPER wiki because the https encryption scheme the server uses is ancient and deemed insecure. The casper wiki is currently being moved to a new system, which, amongst other improvements,

Re: [casper] Debugging on MPSOC with PYNQ image

Hi Jeb, Sorry, I didn't make it clear before. The PL registers I mean is AXI4-Lite registers in the PL design. In casper toolflow, we have a server running on the PS part, which can help us download bit files and access to the PL registers, so we don't use pynq.Overlay and pynq.mmio. I was

Re: [casper] Debugging on MPSOC with PYNQ image

What you mean by PL registers? All the PL IO I’ve done has, at one level of abstraction or another, been either using pynq.mmio (most often either with direct address offsets, the .array[] attribute of the instance, or the auto-generated .register_map attribute. I’ve also loaded in date using

Re: [casper] Debugging on MPSOC with PYNQ image

Hi Jeb, At the beginning of the test, I had the cpu hanging issue. I followed the instructions here, and fixed the issue: https://discuss.pynq.io/t/problem-with-using-integrated-logic-analyzer-ila-for-debugging-with-pynq/435/4 Then I downloaded the bit file via JTAG, the PS part didn't hang

Re: [casper] Debugging on MPSOC with PYNQ image

Hi Wei, Is there any chance this workaround is related to needing cpu.idle=1 on your kernel command line? I know trying to use the system ilas will cause the PS side to hang without it. -Jeb Sent from my mobile. > On Nov 2, 2020, at 15:57, Wei Liu wrote: > >  > Hi Casperites, > > I'm

[casper] Debugging on MPSOC with PYNQ image

Hi Casperites, I'm working on porting casper toolflow on ZCU111. I want to share some debugging experiences, which may be helpful. We have PYNQ image running on the PS part, which is based on Ubuntu18.04. I found PL registers can't be accessed after the bit file is downloaded via JTAG. Because

RE: [EXT]Re: [casper] Re: ADCs in CASPER

Ross, Thanks for the suggestion. It’s an intriguing idea. One of the applications for this is for the next-gen EHT data acquisition system. It’s likely that we don’t need to do fine phase correction for that system, since only a few bits of ADC data is kept. The other application is single-dish

Re: [casper] ADCs in CASPER

Hi Dan, This is the first I’ve heard of a ~$2K RFSoC education board. I couldn’t find any information with a quick web search. Does it have a part number? Is information available from Xilinx, or is it a hush-hush thing? Regards, Ross > On Oct 26, 2020, at 11:32 AM, Dan Werthimer wrote:

Re: [casper] Re: ADCs in CASPER

Hi David, Just to point out — there’s an alternate solution to achieve interleaving of pairs of ADCs on an RFSoC board. This solution doesn’t require a custom input board. It assumes you’re designing for a particular sampling rate, not a variable sampling rate, because it uses fixed time

[casper] High Density FPGA 1U Server with 3.2 Tbit/sec ethernet

Hi Casperites, If you are seeking a 1U server with four large ultrascale+ VU13P FPGA's (each with 2TB DDR4), 32 100Gbit/sec ethernet ports (3.2 Tbit/sec full duplex), and a motherboard with two zeon processors and lots of DRAM, here's a blurb: Pack Four Achronix, Intel, or Xilinx FPGA-based

Re: [casper] ADCs in CASPER

Hi all Thanks for all this feedback, it has been very useful and informative. At the moment we don't have a specific array in mind. At SARAO we are busy in the initial design stages of a new correlator with both the F- and X-Engines implemented on a GPU. We are hoping that the short software

Re: Re: [casper] MKID ADC-4x problem the clock rate of FPGA

Hi,Dan Thanks for you reply. The adc_mkid_4x yellow block for ROACH2 was designed by Madden, Timothy J. From mail list I found that it has some different from the yellow block for ROACH. If you have some results,please inform me Thank you. Cheers!

Re: [casper] MKID ADC-4x problem the clock rate of FPGA

hi ZHANG Laiyu, from rick, who designed that ADC board: "The ADC produces full-parallel data at 550 or 400MHz DDR, so the ADC core would normally run at half of this- I don't see any reason to run it slower. I can't remember who did the yellow block; I have code that runs on a mini-roach for

Re: [casper] ADCs in CASPER

hi gareth, can you tell us a bit more about your project? sample rate? number of ADC bits? number of ADC's? ADC analog bandwidth ? then people might be able to provide better advice. some random thoughts: you probably know the SNAP board has a ZDOC connector on it, so the old CASPER ZDOC

[casper] Re: ADCs in CASPER

Gareth, I’m working on next-generation wideband digitizing with the Black Hole PIRE group. We at the U of Arizona have taken the approach of using the most readily available ADC, the one in the Xilinx RFSoCs. The platform is currently the ZCU111. We plan to migrate to its follow-on, the

Re: [casper] ADCs in CASPER

On 10/26/2020 10:38 AM, Jack Hickish wrote: Hi Gareth, On Mon, 26 Oct 2020 at 12:49, Gareth Callanan > wrote: Hi Casper Community Now that roach2 has been deprecated, I have been wondering where the CASPER community is heading in terms of future ADC

Re: [casper] ADCs in CASPER

Hi Glen, The CASPER tools support the Red Pitaya -- https://www.redpitaya.com/Catalog/p57/stemlab-125-10-starter-kit?cat=c99 -- which is ~200 EUR. Somewhat similar in price to the Pluto but admittedly without the RF front end. This support was added in the last couple of years by our South

Re: [casper] ADCs in CASPER

Hello Casperites, I’ve been following quietly, since I’ve not built any useful Casper-like-devices since we built “Ruppi” a decade ago. It was a clone of the Green Bank Observatory’s Guppi pulsar device (now deceased I think). We did publish a few pulsar results using the NRAO 140ft. As

RE: [casper] ADCs in CASPER

Jack, Should anyone in the group need any Xilinx FPGA, we can supply at a steep discount off of Digikey pricing, if Xilinx will not provide them for free. We have supplied Xilinx for both the Cameras on the Orion space mission, and for Harvard Smithsonian on the EHT (Digicom), and also for the

Re: [casper] ADCs in CASPER

Hi Gareth, On Mon, 26 Oct 2020 at 12:49, Gareth Callanan wrote: > Hi Casper Community > > Now that roach2 has been deprecated, I have been wondering where the > CASPER community is heading in terms of future ADC work. > > As far as I can tell there are three options available: > >1. SNAP

Re: [casper] ADCs in CASPER

Hi Gareth, Jack, Jonathon, Nima, and I have been discussing a low-cost board to serve the N>1000 space, w/ digitization at the antenna (2 ch; ≤ 500 GS/s; ≥ 12 bits; SOC; low power; 10 GbE out). Do the above parameters overlap what you'd like to see, and do you have a price point in mind?

[casper] ADCs in CASPER

Hi Casper Community Now that roach2 has been deprecated, I have been wondering where the CASPER community is heading in terms of future ADC work. As far as I can tell there are three options available: 1. SNAP boards - The SNAP boards seem to support the largest number of options 12 x 250

Re: [casper] ROACH 2 10 GbE Troubleshooting

Thanks for sharing, Ben! It's not easy to acknowledge solving "silly" problems of one's own making, but it is very valuable/helpful to have these explained on the mailing list. Things like this are far more common than one would perhaps care to admit, especially among more experienced CASPER

Re: [casper] ROACH 2 10 GbE Troubleshooting

Hi Marc and Jack, Thank you again for all the suggestions. After fiddling for a while, the answer ended up being sillier than I expected: I had selected the wrong slot number on the ten gbe yellow block, and I was also using the wrong SFP+ port on the PC side of things. No doubt there will be

[casper] Re: Roach 2

Hi My, the first couple of tests look pretty interesting: 11 and 3 devices are detected. I can't remember such details so I'd have to check versus a working board and look for differences in the messages. Perhaps the latter tests are being performed correctly. See "TDO seems to be stuck at 1".

Re: [casper] Jasper error while compiling

Hi Jonathon, Thanks for the ideas, I installed the KDE desktop, and I has available to compile the tut_intro and tut_spec doing a update_casper_blocks(bdroot), but they run only once, the second time as before they seems to never end I guess I have some bad environment config.I'll keep

Re: [casper] ROACH 2 10 GbE Troubleshooting

Hi Hmm... if you are capable of pinging things in one direction, then tcpborphserver is at least partially up - amongst other things, it is responsible for picking up frames from the fpga and handing them off to the kernel, which then does the IP logic and vice versa. You seem to have problems

Re: [casper] ROACH 2 10 GbE Troubleshooting

On Tue, 20 Oct 2020, 9:42 am 'Benjamin Godfrey' via casper@lists.berkeley.edu, wrote: > Hi Jack, >Thank you for all your suggestions. Really appreciate all the > troubleshooting help. Going through your suggestions in order: > > - EOF is going low with the final valid signal in simulation >

Re: [casper] ROACH 2 10 GbE Troubleshooting

Hi Jack, Thank you for all your suggestions. Really appreciate all the troubleshooting help. Going through your suggestions in order: - EOF is going low with the final valid signal in simulation - But valid is always high when I read the snapshot block, which is unexpected (need to dig further

Re: [casper] ROACH 2 10 GbE Troubleshooting

Hi Ben, Before getting too far into the power PC software side, some basic checks in firmware which are probably worth doing - - does EOF go high with (not after) the last valid sample? - can you (using a snapshot block) verify that what is happening in firmware with the vld / EOF signals

Re: [casper] Jasper error while compiling

> I'm working on Ubuntu 18, matlab 2019a and vivado 2019.1.3 > > So I hadn't tried these tutorials in 2019a, only 2018a. (See recommended versions here: https://casper-toolflow.readthedocs.io/en/latest/src/Installing-the-Toolflow.html Vivado/Matlab are extraordinarily picky about which

[casper] Re: Red Pitaya SDRlab 122-16

Hi Sean, just in case you are in a rush to use this platform.. You could use the Pavel Denim IP-cores (https://github.com/pavel-demin/red-pitaya-notes) which gives you the ADC-DAC interface plus some other blocks, and you always could import a simulink design into vivado following the

Re: [casper] Jasper error while compiling

Hi Jonathon, Thanks for your quick answer, I'm using the designs from tutorial_devel directly, I have the same issue with tut_spec and tut_corr I also tried tut_intro and I didnt get any error but it reaches Skipping diagram update Running system generator ... and never finishes. I'm

Re: [casper] Jasper error while compiling

Hi Guillermo, I'm not sure what is causing that specific error - normally it's that there's something like an invalid input (somewhere) in the signal chain leading up to the block it is complaining about (though it looks like it's complaining about the register block yellow block itself). Did

[casper] Jasper error while compiling

Hi all, I'm having trouble compiling the SNAP tutorial designs, I guess that I'm missing some (silly) variable config but after a week of looking around I couldn't find it, I did a fresh tool-flow installation and I'm using virtual env for python 3...If any one has any idea. the error that I got

[casper] ROACH 2 10 GbE Troubleshooting

Hi everyone, I've been getting my feet wet the last little while introducing myself to using the ROACH 2 toolset. After being unable to get Tutorial 2 to work out of the box, I took a step back and am trying to just transmit packets using the SFP+ port to my PC and read them out. My design

[casper] Frequency planning in RFSoC

Hello everyone! I am quite new to RFSoCs. Lately, I tried to do a loopback test on the ZCU111 evaluation kit using Avnet's RFSoC explorer. I followed the two reference examples given in Avnet's product guide and implemented it successfully. However, I didn't quite understand the concepts behind

Re: [casper] Red Pitaya SDRlab 122-16

Hi Sean, We currently only support the 125-10 and 125-14 Red Pitaya hardware modules, but if you or your organisation wanted to add this board as part of the ongoing CASPER support for hardware then go for it. You can always do a pull request to casper-astro/mlib_devel once done and then we can

[casper] Red Pitaya SDRlab 122-16

Hello Casperites, I was looking at the new Red Pitaya board that has come out recently: https://www.redpitaya.com/Catalog/p52/sdrlab-122-16-standard-kit?cat=c102 It features wider out-of-the box bandwidth (no front end filtering), a bigger FPGA, and 16-bit ADCs. Are there any plans to add

[casper] FPGA/DSP Postdoc Position

Hi Everyone, I send news of a postdoc position in Dublin, Ireland, for an FPGA/RF-SoC DSP programming role. An Electronics Engineering/DSP postdoctoral position is being advertised at the Dublin Institute for Advanced Studies (DIAS). The two-year position is on a Science Foundation Ireland

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Jeb, The PYNQ sd card image is V2.5(*ZCU111 v2.5 PYNQ image* ), and the vivado version is 2018.3. If you use vivado2019.1 or vivado2019.2, you may need to make some changes in ./mlib_devel/jasper_library/hdl_sources/infrastructure/zcu111.tcl. In line23, it's "set

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Wei, What version of the PYNQ sd card image and vivado is this based on? -Jeb —— Dr. J.I. Bailey, III (Jeb) / Project Scientist Mazin Lab / Department of Physics, UCSB jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone > On Oct 7, 2020,

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Colm, Currently, I put the code in my github, and you can get it here: https://github.com/liuweiseu/casper_zcu111.git Before you use it, you may need to read "Preparations for zcu111.docx" in ./preparations_for_zcu111. We will make it available on the CASPER Github after I finish the

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Dan, That's great news re. the CASPER Yellow Blocks for the ZCU111 ADC. Does Wei have a github to share that? Or does he intend to make it available on the CASPER Github? Thanks a million, Colm On Wed, 7 Oct 2020 at 02:59, Dan Werthimer wrote: > > > hi jeb, > > regarding your ZCU111 RFDC

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

hi jeb, regarding your ZCU111 RFDC question: here's some info that might be helpful from wei liu, cc'ed on this. btw, wei liu recently made casper yellow blocks for the ZCU111 ADC's. he's now working on ZCU111 yellow blocks for 1, 10, and 100 Gbit ethernet. from Wei Liu:

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Lewis, While that does get rid of the sysref KeyError, executing overlay.usp_rf_data_converter_0 now locks up the whole board and I’m forced to power cycle. The contents of ol.ip_dict['usp_rf_data_converter_0’] are (excluding the parameters): {'addr_range': 262144, 'device': ,

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Jeb, A workaround you can do is to edit the file "/usr/local/lib/python3.6/dist-packages/xrfdc/config.py" on the board. Comment out lines 46,47,60,90,91. These relate to: _DAC_DDP: FifoEnable, AdderEnable _ADC_DDP: FifoEnable Config: MasterADCTile, MasterDACTile Hopefully that works for

[casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Folks, Has anyone here had any success configuring the RFDC block from python using pynq with a bitstream built in Vivado 2019.2? I’m working with the 2.5 ZCU111 SD image with pynq updated to 2.5.4. By using ignore_version=True with loading the overlay I can get the xrfdc driver

Re: [casper] Dropped packets during HASHPIPE data acquisition

Hi David, Sorry it's been a while, I've been working on other tasks besides the packet socket implementation and I've gotten the opportunity to come back to it. I know you have access to the previous emails, but just to catch you up with a summary of what the issue was in implementing packet

Re: [casper] Red Pitaya Wide(-ish)band Spectrometer Tutorial

Hi Paul, Glad you came right! @Mathews: thanks for supporting Paul! Kind regards, Adam Isaacson South African Radio Astronomy Observatory (SARAO) Hardware Manager Cell: (+27) 825639602 Tel: (+27) 215067300 email: aisaac...@ska.ac.za On Mon, Sep 21, 2020 at 12:08 PM Paul Akumu wrote: > Hi

Re: [casper] Red Pitaya Wide(-ish)band Spectrometer Tutorial

Hi Mathews and Adam, It seems the problem was with the incorrect installation of casperfpga. After the reinstallation of casperfpga, everything worked fine. The version number was initially returning *0.0+unknown.202008281536 *and after reinstalling I got the correct version number as

Re: [casper] ROACH2 jtag booting

Hi Alec, thanks for the offering, but yesterday I did manage to make exactly what you told. Thank you anyways! ps: I dont think the macro is dumb, as usual the user who run its (me) without knowing the consecuences is the dumbest haha. El mié., 16 sept. 2020 a las 7:55, Alec Rust () escribió: >

Re: [casper] ROACH2 jtag booting

Once that is set up it's easy to set uboot to netboot as well, I can help with that. Just for interest what happened was that by running tftpuboot, a macro was run that expects the uboot image to be served via tftp. The macro is pretty dumb, so if the file is not there it erases the flash anyway.

Re: [casper] ROACH2 jtag booting

Hi Sebastian, I actually dusted off our old ROACH2 test machine yesterday and did exactly this. To be honest the easiest will be to set up a "roach2 test machine" as per attached instructions and then you just use the menu option to load uboot. This will load the uboot via xmodem over the ftdi USB

Re: [casper] Casper Workshop 2019 - Group Photo

Wow, thanks for the quick answer!! Cheers El mar., 15 sept. 2020 a las 12:26, Arabadjis, Christina (< carabad...@cfa.harvard.edu>) escribió: > The Workshop group photo may be downloaded here: > > https://1drv.ms/u/s!AjCXwKF98lsth6AozLQcBN2WFT_AZw?e=qTprGF > > When I first clicked on it the

Re: [casper] Casper Workshop 2019 - Group Photo

The Workshop group photo may be downloaded here: https://1drv.ms/u/s!AjCXwKF98lsth6AozLQcBN2WFT_AZw?e=qTprGF When I first clicked on it the preview, was pretty low resolution. It is possible to download a nicely resolved version about 13 MB by pressing the right button. With thanks to Arash

[casper] Casper Workshop 2019 - Group Photo

Hi all, Does anyone have at hand the group photo from the 2019 CASPER workshop? I just could find it.oh the memories... Thanks!! -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop

Re: [casper] ROACH2 jtag booting

Finally I could resuscitate the ppc os with the bring up script that Cesar recommends. It's a little difficult to get all the dependencies, but the script uploads the u-boot by the usb port using the python xmodem package, I had to comment the log functions because they are not supported by the

Re: [casper] ROACH2 jtag booting

So one way of recovering a roach with erased flash is to jtag a very small program into the cpu cache/SRAM. That doesn't require the DRAM to be initialised. From there one can then program the flash. Such a program exists in

Re: [casper] ROACH2 jtag booting

Thanks for the responses! I think the Matt guessing is a good starting point, also in page 26 of the schematics says that to debug the ppc you need the halt signal, my jtag programmer has it but I am going to take a closer look there. I had seen the binging up doc, but I had the feeling that it

Re: [casper] ROACH2 jtag booting

Em 12/09/2020 18:08, Sebastian Antonio Jorquera Tapia escreveu: > When I was playing trying to make a netbooting with the ROACH2 and I > issue the command: "run tftpuboot" and making the story short I ended up > with no uboot :( I was able to successfully update the U-Boot on a ROACH2 by

Re: [casper] ROACH2 jtag booting

is the Roach2 test machine bring up manual of any help? https://docs.google.com/document/d/1tqw4C6uZ6EULl1OykTFL_vQTnK52UBr0aYqTg44E5wg/edit this link is found at https://casper.ssl.berkeley.edu/wiki/ROACH-2_Revision_2 On Sat, 12 Sep 2020, Matt Dexter wrote: Date: Sat, 12 Sep 2020 15:26:16

Re: [casper] ROACH2 jtag booting

I don't know enough to help with loading uboot. Perhaps the following bits of low level information on the Roach2 Rev2 might be of use. In the Roach2 rev2 schematics U77 (page 26 of 27) drives the JTAG TCK signals. There are 11 loads: V6, CPLD, PPC, PPCNET, V6NET, QDR0, QDR1, QDR2, QDR3,

[casper] ROACH2 jtag booting

Hi Casperiters, When I was playing trying to make a netbooting with the ROACH2 and I issue the command: "run tftpuboot" and making the story short I ended up with no uboot :( Luckily I have access to one xilinx jtag so I was thinking in connecting via xmd to the ppc and send the uboot with

Re: [casper] ROACH2 DRAM parameters

Here are the files that Mike kindly share, in case someone in the future is looking for a DRAM with ppc interface. https://drive.google.com/file/d/1sdp1kHDDB5wNqE2S14-5lguI5oUv0kL3/view?usp=sharing By the way setting the row address in 15 indeed allows me to access 1.2GB of the DRAM, now I think

Re: [casper] NIC tuning and IRQ binding : Regarding

Hello, most of recent (I don't say modern, as it implies some progress) Linux ethernet drivers split IRQs on at least six instances. We operate two download channels at 1.1GB/s, which is close to the 10Gb ethernet capacitty. The role of the ROACH is here to tag each 8K block with a 8byte

Re: [casper] NIC tuning and IRQ binding : Regarding

Hello David, Thank you for the detailed pointers to the networking issue, I'll certainly have a look at your suggestion about the NUMA topology. We use a bifrost framework for our application that subscribes to the application code to the multicast network. I had already checked the

Re: [casper] Re: TDM data FIR LP filter

Hi Indrajit, I think your best bet is probably the Xilinx FIR compiler -- see https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.pdf, especially the "Interleaved Data Channel Filters section. I'm not sure if that will do what you want, but glancing

[casper] Re: TDM data FIR LP filter

Hi, I'm Andrea Mattana and I have used for the Medicina Team a customized PFB with few taps for the x64ADC designed by the "Oxford Team" (a different repo not linked with the official one) many years ago. Jack Hickish was a member of that team and maybe he has some answers... :) Cheers, Andrea

[casper] TDM data FIR LP filter

Hello all, Medicina team / GMRT team Is there any TDM (X64 ADC )data 32 tap FIR LP filter green block or custom Xilinx block. I am looking into the VEGAS design but it is a parallel streams of the data going into the filter section. Thanks and regards Indrajit Barve indra...@iiap.res.in

Re: [casper] NIC tuning and IRQ binding : Regarding

> I think modern Linux network drivers use a "polling" approach rather than > an interrupt driven approach, so I've found IRQ affinity to be less > important than it used to be. This can be observed as relatively low > interrupt counts in /proc/interrupts. The main things that I've found >

Re: [casper] NIC tuning and IRQ binding : Regarding

Hi, Hari, I think modern Linux network drivers use a "polling" approach rather than an interrupt driven approach, so I've found IRQ affinity to be less important than it used to be. This can be observed as relatively low interrupt counts in /proc/interrupts. The main things that I've found

[casper] Fwd: NIC tuning and IRQ binding : Regarding

Hello Everyone, I'm trying to tune the NIC on a server with Ubuntu 18.04 OS to listen to a multicast network and optimize it for throughput through IRQ affinity binding. It is a Mellanox card and I tried using the "mlnx_tune" for doing this, but haven't been successful. I would

Re: [casper] RedPitaya Compilation Error: "script generated with Vivado <2019.1.1> beign run as <2019.1>"

Hi Xavier, Option 3 is the correct choice. I think if you had installed Vivado 2019.2 then it should have just compiled. Vivado is mostly backwards compatible and so Vivado 2019.1 won't necessarily recognise vivado 2019.1.1 scripting. I think that is your issue. Anyway, great tips from Jonathon

Re: [casper] RedPitaya Compilation Error: "script generated with Vivado <2019.1.1> beign run as <2019.1>"

Hi Jonathon, Thank you for your response. SOLVED! I opted to follow option 3) i.e.: install 2019.1.1 and it worked like a charm! ReadTheDocumetns webpage is correct, asks for 2019.1.1, I am surprised by the level of version dependency of these TCL scripts. Thank you again, Best, XB On Tue, Sep

Re: [casper] RedPitaya Compilation Error: "script generated with Vivado <2019.1.1> beign run as <2019.1>"

Hi Xavi, As I found recently, the block diagram tcl scripts are *really* pedantic about the version they are run in. If it doesn't match, they just don't run, and then the design can't be compiled. Checking out git, it looks like this happened during the last hardware porting workshop, and the

Re: [casper] ROACH2 DRAM parameters

Hi Sebastian, A couple of years ago I managed to get the ddr3 working in a design with a PPC interface to read the memory. I think the design was based on the ska-sa mlib-devel repo and only caters for firmware read/write. We modified the roach1 dram controller to get the ppc interface to

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