Dear Rudolf/All,
Today I patched superiotool to add support for Fintek F81803A and dumped both
superios, and I found that LPC clock must be set at 24MHz on Fintek global
control register #26 from the default 48MHz.
So, now I am working on it, looking how to set correctly this register.
Thank
Good day Rudolf/All,
> OK so it does work.
Yesterday I copy/pasted the subroutine and its definitions used to enable
SERIRQ and set the mode (sc_enable_serial_irqs) and now I can see serial output
but no input on ttyS0.
At this point I am trying to understand what you already told me:
1.- To
Thank you Rudolf,
Good day,
> Can you get coreboot serial console on your fintek superio?
Yes, serial console works fine on fintek.
> If yes, then likely something is wrong with interrupts.
I am thinking about SERIRQ
> You can use isadump to try to obtain UART1 and UART2 configurations (LDN 1 /
Hello All:
I hope you are doing great.
The system: Baytrail E3845, 4GB DDR3, fintek (f81803a) @0x4e and Winbond
(w83627dhg) @0x2e, etc...
I just built coreboot (master) the last few days, everything works wonderfully
except 2 things:
- Libgfxinit probably because this board is using the AUX
Dear Michal:
Thank you very much for all your guidance.
The problem was resolved.
The code was OK but was not executed at the right time (was executed before LPC
and SIO were initialized).
The attached code did the job
Have a great day.
Jose Trujillo.
‐‐‐ Original Message ‐‐‐
On
Thank you Michal:
(you) Just use the appropriate 0xa00 base +
REG OFFSET from the table and you should be allright.
(Me) This is what I believe I did: 0xa00 + 0x040 = GP51/DCD_2 Function Select.
Page (272) top
Maybe I am not setting the code in the right place or executing at the right
time?
Dear Michal,
I am sorry for the late reply but on Friday something went wrong with my
coreboot installation and was unable to boot and I have to reinstall it again
and I just resumed this morning on this issue.
(you) don't think loading the watchdog module will help in any way, actually
the
Dear coreboot engineers & enthusiasts:
Doing dmesg:
[X@localhost ~]$ dmesg | grep "tty"
[ 0.336779] printk: console [tty0] enabled
[ 1.521090] 00:04: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
[ 1.542192] 00:05: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A
[
Hello Mogens,
If you want to use LIBGFXINIT please disable VGA_BIOS and for SeaBIOS choose
"Legacy VGA text mode" as framebuffer mode in "Display".
Let us know if the problem remains after this.
Jose Trujillo.
‐‐‐ Original Message ‐‐‐
On Thursday, January 23, 2020 12:41 PM, Mogens
Happy holidays to all:
My project is unable to compile/build on 4.11/master but do well with 4.10.
It shows the following error:
/home/fw_dev/Program_Files/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd:
build/bootblock/southbridge/intel/bd82x6x/early_pch.o: in function
`early_pch_init':
Hello:
I am also interested and will help test and I think it will be the best to
leave it as CMOS option.
Thank you
Jose.
Sent with ProtonMail Secure Email.
‐‐‐ Original Message ‐‐‐
On Tuesday, December 17, 2019 5:12 PM, Evgeny Zinoviev via coreboot
wrote:
> Hi.
>
> As for HT,
Hello All:
I am sorry about the delay.
> are you able to tell what's reading/writing the EFI variables?
> what are the few lines right before the loop starts?
Loading driver at 0x0007FB1B000 EntryPoint=0x0007FB1E34A EmuVariableRuntimeDxei
InstallProtocolInterface:
will check the documentation on Monday and try to enable it.
Thank you,
Have an excellent weekend.
Jose Trujillo
‐‐‐ Original Message ‐‐‐
On Friday, December 6, 2019 7:36 PM, Patrick Georgi wrote:
> Am Fr., 6. Dez. 2019 um 17:23 Uhr schrieb Jose Trujillo via coreboot
> :
>
>>
Dear Matt/All:
I enabled Tianocore debug in coreboot and the serial debug dump showed me
Tianocore was trying to open a ATA / ATAPI device and was getting stuck there,
so, i disabled a still driverless "ATA" device devicetree until I attach some
driver.
After flashing this change, the first
Dear Nico:
I am not a programmer to understand what you are saying.
I will analize the involved code to try to understand.
But I understand the general idea.
I will do the changes and perform the tests and send you my proposal as soon as
I can.
Thank you,
Jose.
> Hi Jose (sorry for the name
fig?
>
> When I was first testing this years ago, it took 8 mins to boot on one board
> because of this
>
> cheers,
> Matt
>
> On Wed, Dec 4, 2019, 8:33 AM Jose Trujillo via coreboot
> wrote:
>
>> Hello All:
>>
>> I am using the default Tianocore stab
Hello All:
I am using the default Tianocore stable (Mr. Chromebox Matt version?) but is
taking:
2minutes 30seconds from the appearance of the logo to the Tiano menu / grub
bootloader.
After entering the payload there is no more serial debug output.
Anyone had this issue and knows the fix.
Dear Nico:
The libgfxinit solution works!
Thank you very much
What to do next?
> If you get that working, we can try to design a reasonable API for pre-
> defined modes. For instance, the `gma-mainboard.ads` could provide a
> set of Pipe_Configs and we'd only scan for additional displays.
I have no idea bro may be I am doing something wrong.
This original FW of this embedded system is FULL OF BUGS... even the latest
release.
I can guess many of you don't have problems doing it this way.
Maybe I have an early release of VBIOS which doesn't work with coreboot as
expected.
The
Hello Friends
> > Hello All!
> > This is my first try in booting coreboot on a LVDS panel.
> > This is a Sandybridge-M system using video option ROM and VBT extracted
> > from the original FW.
>
> if you ever want to get open-source gfx init running instead, let me know. It
> would only need a
Hello All!
This is my first try in booting coreboot on a LVDS panel.
This is a Sandybridge-M system using video option ROM and VBT extracted from
the original FW.
The coreboot source was created using autoport.
This same project boots to the OS using regular external DVI display.
The panel
Hello Roman,
You need to provide the serial dump logs because I think very little amount of
people here has access to the list of FSP post codes for every processor family
(may be I am wrong but so far I don't know of someone who has them).
Which coreboot platform are you using?
Jose
Sent
Hello Naresh:
> Just to add thought in HW perspective, Is VBUS to USB ports are stable
> during S3 transition. Do you see any OC# lines getting asserted ?
I do not have an oscilloscope on hand until Monday BUT I just borrowed from
my programmer's colleagues another model of COM express
Hello Naresh,
Sorry for the delay,
I had to rebuild the Linux kernel with the following flags disabled in order to
get access to /dev/mem.
CONFIG_STRICT_DEVMEM=n
CONFIG_X86_PAT=n
[root@localhost user]# ./iotools mmio_dump 0xd1220500 0x80
0xd1220500: 0x0603 0x 0x
Naresh:
> Can you provide kernel logs
Partial kernel logs are attached showing failed and successful s3.
> Also can you provided MMIO dump of PORTSC before & after S3 entry.
I still don't know how to dump memory from fedora (could you suggest some
tool?).
> XHCI MMIO base can be found using
Hello Naresh,
> You mean connecting device to USB3 cause wake immediately after S3 entry?
No, if I use only USB mouse and keyboard connected to USB2 ports the computer
will suspend correctly (if I click or execute the S3 command) and will not wake
up (I did 60hour test) unless I push the power
Dear coreboot engineers:
My Skylake system S3 suspension fails because it wakes up immediately.
If I connect the keyboard and mouse to USB2 ports and remove all USB devices
from the USB3 ports then USB wake up works correctly until I connect something
in the USB3 ports.
If I disable XHCI as
Hello Ranga:
From where you got this information / guide because I will try to do it myself.
Jose.
‐‐‐ Original Message ‐‐‐
On Wednesday, November 21, 2018 7:28 PM, galla rao
wrote:
> Hi All,
>
> am trying to save NVRAM variables which are modifed in Uefi Payload, but i
> could not
d do a follow up and fix this issue. BTW same goes for SPI
> flash
>
> protection which should be interfaced globally, platform independent.
>
> BR, Zaolin
>
> On 19.11.18 13:04, Jose Trujillo via coreboot wrote:
>
> > Thank you Christian,
> > Works in my
even in CHIPSET_LOCKDOWN?
But now this system boots fast.
I owe you one bro.
Jose Trujillo
‐‐‐ Original Message ‐‐‐
On Monday, November 19, 2018 1:15 PM, Christian Gmeiner
wrote:
> Hi
>
> Am Fr., 16. Nov. 2018 um 15:57 Uhr schrieb Jose Trujillo via coreboot
> coreboot@
Hello coreboot engineers:
My Kabylake H system "HM175" with coreboot "bsl6" and "kblrvp" platforms with
properly configured I/O failed to save Memory training data to the SPI cache
'RW_MRC_CACHE'.
FMAP: Found "FLASH" version 1.1 at d0.
FMAP: base = ff00 size = 100 #areas = 4
I never needed to make changes to vga.dat on my E3845 system.
The vga.dat was taken from the FSP package the same as you.
The coreboot version that I used was 4.7.
‐‐‐ Original Message ‐‐‐
On Thursday, November 8, 2018 2:02 PM, galla rao wrote:
> Hi Jose,
>
> Thanks for a quick response
Dear Lance:
Yesterday I managed to make internal GbE to work with the following:
# Enable Root port 4 (PCIe port 5) for GbE
register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[0]" = "0"
Works fine
But I am trying to enable NVMe and
Check the GPIOs in your schematic.
maybe you need to enable something.
‐‐‐ Original Message ‐‐‐
On Thursday, November 8, 2018 2:02 PM, galla rao wrote:
> Hi Jose,
>
> Thanks for a quick response
>
> Enabled framebuffer in Config as given in inserted picture and am using
> uefipayload
Hello Ranga:
If you are using tianocore as payload you should choose vesa framebuffer option
and text mode in seabios
JT
‐‐‐ Original Message ‐‐‐
On Thursday, November 8, 2018 1:08 PM, galla rao wrote:
> Hi All,
>
> Am facing Gfx Enablement failure, i don't see any Video output on my
Hello coreboot developers:
Looks that coreboot development has been very active lately integrating FSP,
adding new platforms and getting ready for the 4.9 release.
And also I can see new payloads "WOW" (like LinuxBoot, Yabits)... what a
revolution of features and code.
I am using coreboot
treamed recently. I
> will suggest you to sync up your code base and try again.
>
> Lance
>
> On Tue, Oct 30, 2018 at 7:10 AM Jose Trujillo via coreboot
> wrote:
>
>> Hello coreboot engineers:
>>
>> I am using the "coffeelake RVP11" to test the code on my
offeelake-h related ID(CPUID and MCH/PCHID) had been up-streamed recently.
>>> I will suggest you to sync up your code base and try again.
>>>
>>> Lance
>>>
>>> On Tue, Oct 30, 2018 at 7:10 AM Jose Trujillo via coreboot
>>> wrote:
>>&
treamed recently. I
> will suggest you to sync up your code base and try again.
>
> Lance
>
> On Tue, Oct 30, 2018 at 7:10 AM Jose Trujillo via coreboot
> wrote:
>
>> Hello coreboot engineers:
>>
>> I am using the "coffeelake RVP11" to test the cod
Hello coreboot engineers:
I am using the "coffeelake RVP11" to test the code on my "non RVP" system.
The payload doesn't load.
I found several errors in the attached log:
1.- Device ID's of the system are still not existant in coreboot.
2.- Misconfigured # of MAX CPU CORES.
3.- Maybe memory is
Corrected link:
http://opensecuritytraining.info/IntroBIOS.html
‐‐‐ Original Message ‐‐‐
On Wednesday, October 24, 2018 1:07 PM,
wrote:
> Can any one recommend a source for basic pc bios info? There's a lot to
> learn and some good links would be greatly appreciated. I'm a geek but
Hello:
opensecuritytraining.info/introBIOS.html
Good day.
‐‐‐ Original Message ‐‐‐
On Wednesday, October 24, 2018 1:07 PM,
wrote:
> Can any one recommend a source for basic pc bios info? There's a lot to
> learn and some good links would be greatly appreciated. I'm a geek but I
>
Zvika:
The microcode you downloaded doesn't include the binary for your system... read
the release notes.
6, 55, 9 = 06-37-09
Download this:
https://github.com/platomav/CPUMicrocodes/blob/master/Intel/cpu30679_plat0F_ver090A_2018-01-10_PRD_252563C5.bin
Rename this bin to:06-37-09
Good day Zvika:
Looks typical the configuration
But for DIMM Density to get this information you should run the command I told
you yesterday or check the memory chip datasheet.
About the 0xCE postcode you need to set the microcode (or the correct one, or
the correct path) in menuconfig.
Jose.
Zvika:
In my experience with my Baytrail system I can tell you my system is "really"
memory down because has soldered memory chips on the motherboard BUT has also a
soldered SPD memory so, if keep "Enable Memory Down = Disabled" in BCT the
system fetch memory timings from SPD so, no need to
Hello Zvika,
Add your device in Konfig and configure it under devicetree.
Look for examples and/or previous threads in this mail list.
Jose.
‐‐‐ Original Message ‐‐‐
On Monday, October 8, 2018 12:02 AM, Zvi Vered wrote:
> Hello,
>
> I have to port coreboot to a "Bay Trail" board
>>>>>
>>>>>>>> I hope this answered your questions.
>>>>>>>> Jose..
>>>>>>>>
>>>>>>>> ‐‐‐ Original Message ‐‐‐
>>>>>>>> On Saturday, September 29, 2018 12:24 AM, Zvi Vered
s 8M file (using
>> any hexeditor) or use something like below from command line:
>>
>> dd if=coreboot.rom of=corebootout.rom bs=1M skip=3
>>
>> (before doing that double check if original vendor`s rom file size is
>> 5242880 bytes long)
>>
>> Mariusz
>>>>>> I just forgot the troubles this caused me.
>>>>>> I am sorry Vika... My mistake.
>>>>>>
>>>>>> I can confirm with Nico:
>>>>>> ROM chip size = 8MB (your case)
>>>>>> CBFS_SIZ
Sorry,
I cannot help you with this maybe I still don't understand.
The only thing I can tell you that I use for this same SOC processor all the
header files ".h" included in the kit and they work without problems.
It would be good if you can enable the serial debug console and dump the log
but you can try.
>>>>
>>>> To have better chances of success you should be dumping hardware settings
>>>> booting with your original "BIOS" (look for the attached file).
>>>>
>>>> Check if the system is "Memory down"or/and ECC beca
Hello Ranga:
It is ASCII just not properly formatted
Just remove the text from this:
0x0001, /* Header Version */
0x0901, /* Patch ID */
0x04212014, /* DATE */
0x00030679, /* CPUID */
0x69c4e6f1, /* Checksum */
0x0001, /* Loader Version */
Zvika:
You are lucky If the model of your board appears in the list of supported
nodels because you have to do not much, but, if not, you have to do a
"motherboard porting" for your specific system.
Is essential you add the correct microcode and configure correctly FSP on
memory settings
-perl
>> sudo modprobe eeprom
>> decode-dimms
>>
>> If you have not done this already there is still a long way to go.
>> Don't get intimidated, just do it, if you have questions just ask I will
>> try to help
>>
>> Good luck,
>> Jose.
>
elp
Good luck,
Jose.
‐‐‐ Original Message ‐‐‐
On Wednesday, September 26, 2018 6:28 PM, Nico Huber wrote:
> Hi,
>
> On 9/26/18 9:19 AM, Jose Trujillo via coreboot wrote:
>
> > No, don't change it, you change the size of coreboot only if during the
> > building process &q
You are welcome,
No, don't change it, you change the size of coreboot only if during the
building process "make" complain that there is not enough space but in your
case your build was already successful leave it like that.
In the rare circumstance that more space is required you can increase
Zvika:
Sorry I Forgot:
"CB_baytrail.bin" is just a renamed copy of "BYT_orig.bin".
After that command a new file will be named: "BYT_orig.bin.new"
Jose.
‐‐‐ Original Message ‐‐‐
On Tuesday, September 25, 2018 10:16 AM, Jose Trujillo
wrote:
> Hello Zvika:
>
> First get the correct
Hello Zvika:
First get the correct original full 8MB FW from the manufacturer or dump it
from the board with the command in EFI:
"ftp -d BYT_orig.bin" and double save it.
2.- in coreboot/util/ifdtool do make and sudo make install.
3.- in terminal go to the FW directory and do:"ifdtool
ot on behalf of Nico Huber
>
> Sent: Thursday, September 20, 2018 1:16 PM
> To: Jose Trujillo; Naresh G. Solanki
> Cc: coreboot
> Subject: Re: [coreboot] Kabylake unable to boot with post code 0x71 "SGX:
> pre-conditions not met"
>
> Hi Jose,
>
> On 20.09.2
till end of ramstage.
>
> On Thu, Sep 20, 2018 at 1:25 PM Jose Trujillo via coreboot
> coreboot@coreboot.org wrote:
>
> > Hello Nico,
> > Yes, I am using Intel Kabylake DDR4 RVP8 board.
> >
> > > Never use another board's GPIO settings.
> > > Reading t
elp.
Jose Trujillo
‐‐‐ Original Message ‐‐‐
On Wednesday, September 19, 2018 10:15 PM, Nico Huber wrote:
> Hi Jose,
>
> On 12.09.2018 15:12, Jose Trujillo via coreboot wrote:
>
> > To begin with the system didn't find memory attached...
> > but there is memory attach
chematics.
> Especially check: domain_vr_config
>
> Additionally can you provide info like when the hang happens, what is
> state of SLP_S0/3/4/5.
> Also check voltage level for VCC_CORE/GT/SA
>
> Regards,
> Naresh G Solanki
> On Tue, Sep 18, 2018 at 3:01 PM Jose Trujill
ld have received fsp header along with fsp binary in single package.
> > However you can get FSP binaries and header from
> > https://github.com/IntelFsp/FSP
> > Also make sure you copy FSP header version equal fsp binary version.
> > All the best!
> > On Mon 17 Sep, 2
rsion you are using versus FSP
> header version checked-out in coreboot(which is currently 2.9.2).
> They should be
>
> On Fri, Sep 14, 2018 at 7:55 PM Jose Trujillo via coreboot
> coreboot@coreboot.org wrote:
>
> > Here is Naresh
> > ‐‐‐ Original Message ‐‐‐
> &
Here is Naresh
‐‐‐ Original Message ‐‐‐
On Friday, September 14, 2018 4:49 PM, Naresh G. Solanki
wrote:
> Can you also provide latest complete log.
>
> On Fri 14 Sep, 2018, 2:10 PM Jose Trujillo via coreboot,
> wrote:
>
>> Thank you Naresh,
>>
>&g
form.c#n73
>
> as well.
>
> Additionally you can enable config DEBUG_BOOT_STATE to understand where
> exactly its stuck.
>
> Regards,
>
> Naresh G. Solanki
>
> On Wed, Sep 12, 2018 at 9:24 PM Jose Trujillo via coreboot
> wrote:
>
>> Dear All,
>> A
hile sending command 0x0d to EC!
> recv_ec_data: 0xff
> recv_ec_data: 0xff
> SPD index 7
> No memory dimm at address A0
> No memory dimm at address A2
> No memory dimm at address A6
>
> 0 DIMMs found
>
>
> ‐‐‐ Original Message ‐‐‐
> On Wednesday, 12
dimm at address A6
0 DIMMs found
‐‐‐ Original Message ‐‐‐
On Wednesday, 12 September 2018 13:29, Jose Trujillo via coreboot
wrote:
> Dear coreboot engineers:
>
> Right now I am stuck with a Kabylake system with the following message:
>
> CPU #1 initialized
Dear coreboot engineers:
Right now I am stuck with a Kabylake system with the following message:
CPU #1 initialized
apic_id: 0x06 done.
microcode: updated to revision 0x8d date=2018-01-21
CPU #3 initialized
bsp_do_flight_plan done after 220 msecs.
CPU: frequency set to 3600 MHz
Enabling
gt; What should i do now to get the to show
> output on the screen?
>
> On 2018-08-14 11:53, Jose Trujillo via coreboot wrote:
>
> > Hello h42
> > If you are using Tianocore you must use VESA framebuffer
> > If Seabios use text mode
> > Jose
> >
Hello h42
If you are using Tianocore you must use VESA framebuffer
If Seabios use text mode
Jose
‐‐‐ Original Message ‐‐‐
On August 14, 2018 2:41 PM, wrote:
> I dont get anything on the screen from coreboot. The later os is
> displaying fine.
>
> How i build the image: ran on a fresh
Dear coreboot developers:
I am trying to create CB firmware for Broadwell-D 1559 system using CamelBack
Mountain CRB as mainboard selection, and the system boots Windows and Linux
operating systems but USB keyboard and mouse doesn't work.
I already enable/disabled EHCI/xHCI devices in
My system Baytrail E3845:
DisplayPort audio in Linux works fine but in Windows is not detected.
I am sure that the OS has the proper graphics drivers because DP Audio works
with original BIOS in the same HDD Windows OS.
Anyone could give me a hint?
Thank you,
J. Trujillo.--
coreboot mailing
If you don't enable a device in devicetree the initialization routine will not
be executed.
To test just insert a SD card and use DMESG or other command to see if device
ID is found, also in device manager in Windows.
JT.
‐‐‐ Original Message ‐‐‐
On June 21, 2018 2:06 PM,
Hello Thomas,
It is not enough just to disable it from the devicetree ?
JT.
‐‐‐ Original Message ‐‐‐
On June 21, 2018 1:43 PM, Thomasheidler via coreboot
wrote:
> Thanks for your response and suggestions.
>
> Luckily I don’t need the SD card reader and would rather completely
any other information ?
> How can I write it from scratch ? Can Intel provide information on how to
> implement this initialization ?
>
> Thank you,
> Zvika
>
> On Mon, Jun 18, 2018 at 11:22 AM Jose Trujillo via coreboot
> wrote:
>
>> Hello Zvika:
>> 1.
ek UART ports worked fine and ttyS0 from
Winbond is just working fine too.
I just need to do some fine tuning on the UART ports and configure correctly
HWMon and Fan control in Fintek.
Thank you All,
J. Trujillo
‐‐‐ Original Message ‐‐‐
On June 15, 2018 6:30 PM, Jose Trujillo via coreb
Hello Zvika:
1.- Usually it is not necessary to change the CBFS size unless the compiler
complain of lack of space.
2.- You should not worry about this setting to make your system to work.
3.- You should not use FSP_PACKAGE_DEFAULT if your plan is to use SIO because
it will enable SOC internal
Dear All,
After following the recommendations from Rudolf and other people on this mail
list I was able to make the following to make my LPC SIO to work (with issues).
1.- Enable SERIRQ in CONTINUOUS_MODE
2.- Add SUPERIO_WINBOND_W83627DHG driver to the Konfig file.
3.- Add the SIO
Dear Rudolf/All,
Today I tried several things to try to make COM1 to work unsuccessfully.
In my last test today I crossed the COM configuration from:
COM1 (not working)COM2 (OK)
0x3f8, IRQ4 0x2f8, IRQ3
to:
0x3f8, IRQ3 0x2f8, IRQ4 (Both not
Thank you Rudolf for your advise,
I checked the interrupts in Linux and showed me that the interrupts were
already in EDGE mode but anyway I changed the interrupt mode in southcluster.c
from quiet to edge.
The default PNP configuration for the Winbond SIO was crashing Windows 7 and 10
and
Dear coreboot developers:
My system is Baytrail FSP E3845
2 LPC SIO WINBOND_W83627DHG and FINTEK_F81803 (disabled at this moment)
SERIRQ has been enabled.
I have the following issue in the W83627DHG SIO:
ttyS2 @ 0x3e8, irq 4 doesn't work. (changing IRQ 4 to 6 does not make any
difference)
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