ysg>
*Od:* John Woodgate
*Poslano:* sobota, april 27, 2024 4:18:41 PM
*Za:* EMC-PSTC@LISTSERV.IEEE.ORG
*Zadeva:* [PSES] IEC 62368-1: clearance and creepage
*CAUTION:*This email originated from outside of our organisation. Do
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Zadeva: [PSES] IEC 62368-1: clearance and creepage
CAUTION: This email originated from outside of our organisation. Do not click
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It isn't clear to me whether the requirements of 5.4.2 and
It isn't clear to me whether the requirements of 5.4.2 and 5.4.3
(Edition 4) apply if the product remains safe with relevant clearances
and creepages short-circuited (one at a time). The specific case is at a
point fed by a 1 kV DC source behind two 4.7 megohm resistors in series.
Please
Thank you to all who provided a response to my question. Your input and
comments are, as always, greatly appreciated.
Happy Holidays to all I look forward to seeing you at ISPCE in Dallas in May.
Best regards,
> On 12/01/2022 3:51 PM Steve Brody wrote:
>
>
> I have a client who
rts
> transient voltages in secondary circuits?
>
>
>
> Best wishes for the holiday season,
>
> Rich
>
>
>
> *From:* Steve Brody
> *Sent:* Thursday, December 1, 2022 12:51 PM
> *To:* EMC-PSTC@LISTSERV.IEEE.ORG
> *Subject:* [PSES] Secondary creepag
creepage/clearance
I have a client who has a secondary pwb that has traces and vias that may have
100 vdc on them adjacent to ground.
Per 61010-1 there is a requirement for spacing and/or dielectric test, both
depending on what the mains voltage is.
The question is why is the mains
(340 - 245 BC)
On 2022-12-02 19:15, Joe Randolph wrote:
Hi Steve:
I work mostly with the 60950-1 and 62368-1 standards for ITE, so I’m
not familiar with the details of the requirements in 61010-1.
That being said, I’ve seen many cases where someone misinterpreted
the creepage/clearance
for ITE, so I’m
not familiar with the details of the requirements in 61010-1.
That being said, I’ve seen many cases where someone misinterpreted the
creepage/clearance/dielectric requirements in 60950-1 and 62368-1, not
realizing that their specific configuration was exempt from those
Hi Steve:
I work mostly with the 60950-1 and 62368-1 standards for ITE, so I’m not
familiar with the details of the requirements in 61010-1.
That being said, I’ve seen many cases where someone misinterpreted the
creepage/clearance/dielectric requirements in 60950-1 and 62368-1
The simple answer is that you need to provide creepage and clearance
distances in secondary circuits to avoid arcing when the circuit is
subjected to the absolute worst case surges and transients that the circuit
might see. Since this can be difficult to determine, most people just use
the tables
I have a client who has a secondary pwb that has traces and vias that may have
100 vdc on them adjacent to ground.
Per 61010-1 there is a requirement for spacing and/or dielectric test, both
depending on what the mains voltage is.
The question is why is the mains voltage a consideration or
All,
I was reviewing the rationale document IEC TR 62368-2 and found a comment
in 5.4.3: "*However, there is no rationale why the creepage distances are
different for printed wiring boards and other isolation material under the
same condition (same PD and same CTI). *"
Apparently some
Chances are the isolation between primary and secondary are in place. But, for
the purpose of certification, to avoid creepage and clearance requirements
between primary and secondary, I said to DESIGNATE the secondary as
non-isolated from the primary. This does not mean
t: [PSES] SV: [PSES] Creepage and clearance requirements
Pete,
I can follow your thoughts and that special things can happen with such a
product in the long run. But the manufacturer will probably make designs that
support product functionality and design as original intended. Taking into
Boštjan,
Good advice. Any conductive materials in non-conductive enclosures are risky
business.
BR Amund
Fra: Boštjan Glavič
Sendt: 15. september 2021 07:02
Til: EMC-PSTC@LISTSERV.IEEE.ORG
Emne: Re: [PSES] Creepage and clearance requirements
Hi Amund,
If plastic enclosure
Aldous
Sendt: 14. september 2021 18:19
Til: EMC-PSTC@LISTSERV.IEEE.ORG
Emne: Re: [PSES] Creepage and clearance requirements
It's also important to consider servicing operations. If servicing is intended
on the unit while powered, considering the secondary as not isolated from
primary (and so
, then
it is of course positive.
Best regards Amund
Fra: Pete Perkins
Sendt: 14. september 2021 16:51
Til: EMC-PSTC@LISTSERV.IEEE.ORG
Emne: Re: [PSES] Creepage and clearance requirements
Amund,I support Rich’s approach.
It does leave a lingering question, though
on mechanical tests on enclosure.
Best regards,
Boštjan
From: Scott Aldous <0220f70c299a-dmarc-requ...@ieee.org>
Sent: Tuesday, September 14, 2021 6:19 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] Creepage and clearance requirements
It's also important to consider ser
details to properly implement this.
>
>Where in the report do you clearly state that the
> requirements, including isolation/insulation (creepage and clearance) were
> not evaluated and the ‘secondary’ is considered mains in a clear way?
>
>With this u
that the requirements,
including isolation/insulation (creepage and clearance) were not evaluated and
the ‘secondary’ is considered mains in a clear way?
With this understanding the designer will know that the full
mains isolation/insulation will have to be done for the output
Hi Amund:
If no accessible conductive parts, then you can designate the secondary
circuits as part of the primary circuits, which means there is no need for
isolation between primary and secondary circuits. No creepage or clearance
requirements! OVC would not apply primary
:16 AM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] Creepage and clearance requirements
IEC60950-1:
How about the Creepage and clearance requirements for an AC driven radio HUB
device.
* One input: 230VAC (direct into wall socket)
* No physical output ports, just radio communication
IEC60950-1:
How about the Creepage and clearance requirements for an AC driven radio HUB
device.
* One input: 230VAC (direct into wall socket)
* No physical output ports, just radio communication.
* Insulated plastic enclosure (UL94 V-0)
The Creepage and clearance
securely with nylon tie wrap.
Product should not be accessible when mains are powered without adequate PPE.
Chris
From: John Woodgate
Sent: Saturday, October 26, 2019 4:11 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] Terminal block pitch pcb creepage/clearance 400VL:N/G;
600/690
If you have room for the 7-position block, go for it to save a lot of
argument about other 'solutions'.
Best wishes
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK
On 2019-10-26 20:36, Chris Wells wrote:
I want to monitor mains of polyphase
I want to monitor mains of polyphase power systems VA/VB/VC/VN using EN/UL
61010-1
Ratings: 400VL:N/G; 600/690 L:L CAT III, PD2, 3Km elevation
Issue I see is to get the phase to phase spacings on my terminal block.
Requirements in Annex K are 5.5mm at 2Km but go up to ~ 6.3mm at 3Km.
I
ed. 3.1.
(3) There is a lot more to creepage and air clearance & table 7 are the Test
voltages for Means of Operator Protection not for Creepage & Air-clearance for
Means of Operator Protection.
Remember the std is based on the concept of a min of 2 levels of protection so
the devic
Is this not in IEC 60601-1 3.1ed?
Peter Tarver
From: Vincent Lee [mailto:08e6c8d35910-dmarc-requ...@ieee.org]
Sent: Thursday, May 18, 2017 07:03
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] Surface Creepage & Air Clearance Calculator - IEC 60601-1 3.1ed
Hi all,
Good day,
(1)
Hi all,
Good day,
(1) Does anyone know where can we get a Surface Creepage & Air Clearance
Calculator based on IEC 60601-1 3.1ed ?
(2) I was told that surface creepage and air clearance distance stated in IEC
60950-1 2ed is used as Mean of Operator Protection (MOOP) while those stated in
minimum values of CREEPAGE DISTANCES and
AIR CLEARANCES specified in IEC 60950-1 are derived from IEC 60664-1 and
are based on assumptions about possible overvoltages in mains and other
circuits, particularly the frequency of occurrence of various levels of
overvoltage. According to the understanding
Hi, Vincent.
As Bernd pointed out, IEC 60664 gives the best information on the scientific
basis for Clearance and Creepage distances.
Paschen’s Law will (theoretically) have no effect on Creepages. Theoretically,
Creepages exists in two dimensions. Realistically, even the thinnest copper
that might be helpful.
You are right that the definition of air clearances refers to Paschen's Law,
while the definition of creepage distances is based on a statistical evaluation
of long-term measurement results (e.g. impulse withstand voltage, insulation
resistance) for different insulation mater
Hi all,
Good day,
1) May I know what is the scientific relationship between Paschen's Law
(https://en.wikipedia.org/wiki/Paschen%27s_law) and surface creepage and air
clearance distance ?
2) If there is a relationship, how can one calculate the surface creepage and
air clearance distance
Hi all,
Good day,
Does anyone know where can we get a Surface Creepage & Air Clearance Calculator
based on IEC 60601-1 3.1ed ?
I was told that surface creepage and air clearance distance stated in IEC
60950-1 2ed is used as Mean of Operator Protection (MOOP) while those stated in
IEC 606
Conformal coating is acceptable for safety compliance while solder resist is not
Rodney Davis
From: Joe Randolph <j...@randolph-telecom.com>
Sent: Tuesday, April 19, 2016 8:10 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] IEC60950-1, Table 2N - cr
of my
employer.
From: Joe Randolph [mailto:j...@randolph-telecom.com]
Sent: Tuesday, April 19, 2016 5:10 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] IEC60950-1, Table 2N - creepage
Hi Ralph:
I have also wondered why solder resist could not help qualify for a lower
pollution degree. I
ndolph-telecom.com
<http://www.randolph-telecom.com> http://www.randolph-telecom.com
From: McDiarmid, Ralph [mailto:ralph.mcdiar...@schneider-electric.com]
Sent: Tuesday, April 19, 2016 7:46 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] IEC60950-1, Table 2N - creepage
I have long
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] IEC60950-1, Table 2N - creepage
I have long wondered why solder resist on a PCB cannot be used to reduce
pollution degree and therefore creepage distance. Ever try to scrap it off? I
am sure that all product standards today, assume bare FR4 material
I have long wondered why solder resist on a PCB cannot be used to reduce
pollution degree and therefore creepage distance. Ever try to scrap it
off? I am sure that all product standards today, assume bare FR4 material
with no coating (no solder resist).
I know that IEC60664 calls out a bunch
SES] IEC60950-1, Table 2N - creepage
Thanks, folks!
Appreciate all your feedback.
I have some problems with Maxwell, but rather Maxwell than 60950 :)
And I must get Amendment 2.
In our case: We have a multilayer pcb with high voltage AC in all layers.
Functional, basic and reinforced insulat
[PSES] SV: [PSES] IEC60950-1, Table 2N -
creepage
Thanks, folks!
Appreciate all your feedback.
I have some problems with Maxwell, but rather
Maxwell than 60950 :)
And I must get Amendment 2.
In our case: We have a multilayer pcb with high
voltage AC in all layers. Functio
...@ieee.org]
Sendt: 18. april 2016 20:59
Til: EMC-PSTC@LISTSERV.IEEE.ORG
Emne: Re: [PSES] IEC60950-1, Table 2N - creepage
Hi Amund:
2.10.6 addresses printed wiring boards.
2.10.6.3 addresses insulation between conductors on the same inner surface
of a printed board which invokes
Hi Amund:
2.10.6 addresses printed wiring boards.
2.10.6.3 addresses insulation between conductors
on the same inner surface of a printed board which
invokes 2.10.5.5, which is cemented joints.
Table 2N (Amendment 1) applies to the creepage
distance of the cemented joint
Creepage is only defined for the surface between INSULATOR and AIR. (and
the insulator having and insulation function of course; so on the
surface be limited by conductors)
The shortest path over the defined surface from conductor1 to conductor2
is called creepage.
Gert Gremmen
ce-test
ot;:
1) Creepage distance (distance across a surface) only applied on the
outer surface of a printed circuit board.
2) This creepage distance on the outer surface could be reduced by
complying with some complex requirements for "coated printed boards." Few
people used this option.
Two columns in Table 2N are covering . Those distances, they
are only for inside the PCB layers, right?
Regards
Amund
-
This message is from the IEEE Product Safety Engineering Society emc-pstc
discussion list. To post a
. That is, the application
must be part of the FUS audit. Potting and coating requires recurring test.
Brian
From: Richard Nute [mailto:ri...@ieee.org]
Sent: Thursday, March 12, 2015 12:28 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] Encapsulation for Creepage Clearance
Hi John:
Clearance
In message
b87b3216c599564e9071daf63e06e7491eb07ab...@exchange.wonderwarene.com,
dated Thu, 12 Mar 2015, John Cochran jcoch...@strongarm.com writes:
? I am trying to dispute MetLab requirement for testing to IEC
60079-18 when the minimum creepage and clearance of a 100-240VAC power
supply
In IEC 60079-15 Table 10 - Minimum creepage distances, clearances and
separations, Encapsulated or solid insulation is allowed to reduce the minimum
clearance requirements. Note 4 of the table states completely encapsulated in
compound to a minimum depth of 0.4 mm. What tests are required
Hi John:
Clearance is defined as the shortest distance
between conductors in air.
Creepage is not an insulator, but the interface
between air and solid insulation. Creepage is
defined as the shortest distance between
conductors across the surface of the interposed
solid
In IEC 60079-15 Table 10 - Minimum creepage distances, clearances and
separations, Encapsulated or solid insulation is allowed to reduce the minimum
clearance requirements. Note 4 of the table states completely encapsulated in
compound to a minimum depth of 0.4 mm. What tests are required
Subject: RE: [PSES] Creepage and RMS
Thanks all, for your point(s) of view and 2-cents.
Resuming my conclusions:
- Creepage cannot be shorter than clearance. I think that is clear to most of
us.
- Clearance is essentially based on peak voltage stressing an specific
insulator. Even short time
In message FCA549BE3ECF9D4CB8CB8576837EA48920A740@ZEUS.cetest.local,
dated Tue, 13 May 2014, ce-test, qualified testing bv - Gert Gremmen
g.grem...@cetest.nl writes:
- Creepage breakdown is an essential long time process governed by
dissipation effects on a surface layer covering the creepage
was compromised.
This is neither clearance or creepage but a *bulk* effect of the
electric field on the nylon. It may simply be due to heating caused by
dielectric loss, but nylon is not usually considered a poor insulator at
tens of MHz. However, that applies to *dry* nylon, and some grades of
nylon absorb
Hi John,
What I learned the last few days
The difference with clearance is that creepage needs
time to create a path
Electrochemical reactions behave like charging a battery, it is the rms value
that determines the charge, not the peak value.
And about being prudent, in my case
*
assumption. If it proves costly, a lower creepage distance should be
tested, but it's difficult and costly to test anything that depends on
pollution. Again, you can be *prudent* and test with a worst-case
pollutant, soot or carbon from motor brushes.
--
OOO - Own Opinions Only. With best wishes. See
In message 20140513090333.303...@gmx.com, dated Tue, 13 May 2014,
Anthony Thomson ton...@europe.com writes:
If Gert means 'charge' in the number of Coulombs flowing, then the RMS
value holds.
How do you arrive at that conclusion?
--
OOO - Own Opinions Only. With best wishes. See
checking creepage for years based on the same voltage as
clearance, just because the standard did not mention the difference
clearly.
(It has never been a problem either as most products were largely
over-insulated). Ther fore I want to ask anyone on this list involved
in safety standardization
Original Message
From: ce-test, qualified testing bv - Gert Gremmen
Sent: Tuesday, May 13, 2014 3:58 AM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Reply To: ce-test, qualified testing bv - Gert Gremmen
Subject: Re: [PSES] Creepage and RMS
The analogy I made with a battery was (very) loose, strictly spoken it's
Again, you can be *prudent* and test with a worst-case pollutant, soot or
carbon from motor brushes.
That would always constitute a failure, as a creepage failure is not a defined
discharge as with clearance, but more a leakage current phenomena. If you fill
up the gap with a conductive
. That is not an
unreasonable model of salt pollution of a creepage distance, although
salt itself does no produce permanent degradation of most insulators.
Apparently the committee writing IEC 60664 found the application of RMS
more suitable then using an average (=voltage integrated over time
In message FCA549BE3ECF9D4CB8CB8576837EA48920A743@ZEUS.cetest.local,
dated Tue, 13 May 2014, ce-test, qualified testing bv - Gert Gremmen
g.grem...@cetest.nl writes:
That would always constitute a failure, as a creepage failure is not a
defined discharge as with clearance, but more a leakage
The point is that creepage distances are
determined such as that within the limits of pollution degrees
1-3 , no substantial leakage current(eventually leading to breakdown of
the insulation) develops. Yes the reaction starts immediately
(salt/electrodes) but the deterioration takes time
In message FCA549BE3ECF9D4CB8CB8576837EA48920A744@ZEUS.cetest.local,
dated Tue, 13 May 2014, ce-test, qualified testing bv - Gert Gremmen
g.grem...@cetest.nl writes:
The point is that creepage distances are
determined such as that within the limits of pollution degrees 1-3 , no
substantial
is
created on the surface that may lead to further damage.
This is a more or less statistical process.
The size and frequency of these scintillations and affected areas seem
dependent of
the voltage and total damage is therefore a time integration of voltage over
the creepage path.
In my opinion
and affected areas seem
dependent of the voltage and total damage is therefore a time
integration of voltage over the creepage path.
Not really. The carbon track resistance progressively reduces as more
degradation occurs. This is probably a mixture of thermal and
electrochemical degradation
John Wrote:
The carbon track resistance progressively reduces as more degradation
occurs.
True, but at that moment the creepage insulation path is already broke
down.
A leakage current is flowing and heating up the surface.
It's the end of the process, and soon after a fuse will blow.
The time
I have a question on creepage distances.
A product creates a saw tooth High voltage
of 2000 Vpeak The VRMS measured on the scope
on a full period equals 1120 V
Creepage is based on the RMS value of the voltage
so is based on 1120 V.
Now the frequency of the sawtooth is 3 Hz.
Should I still
/in/dougp01
Original Message
From: ce-test, qualified testing bv - Gert Gremmen
Sent: Monday, May 12, 2014 8:21 AM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Reply To: ce-test, qualified testing bv - Gert Gremmen
Subject: [PSES] Creepage and RMS
I have a question on creepage distances.
A product creates a saw
cables with
an insulation breakdown of 1200 V, or even 1500V. I’d expect that to be in
excess of the 2000V peak value.
Just my thoughts.
T
- Original Message -
From: ce-test, qualified testing bv - Gert Gremmen
Sent: 05/12/14 03:20 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] Creepage
.
The standards CREEPAGE table (PCB or NOT) explicitly mentions to use RMS (or
DC) values.
So the (air)clearance in my example isi ndeed based on 2 kV as well as
distance through insulation) while
the creepage over PCB is based on RMS value (with the clearance as a minimum of
course
The issue with some 60664 tables is that it is (for 0 to 2km) based on
Paschen's Law, which is for a simple homogenous e-field. So creepage via RMS is
an incomplete analysis.
As others have stated, spacing should be determined by both peak and RMS. And
because too many do not measure WV
Something to keep in mind,
Peak Voltages (spikes, impulses, flyback, laser ignition, etc.) are more a
concern for clearances than for creepage. Committees build creepage tables
in slightly different ways and they sometimes ignore the relationships of
Vrms, Vpk and Vdc which are often related
To: Brian Oconnell
Cc: emc-pstc
Subject: Re: [PSES] Creepage and RMS
Something to keep in mind,
Peak Voltages (spikes, impulses, flyback, laser ignition, etc.) are more a
concern for clearances than for creepage. Committees build creepage tables in
slightly different ways and they sometimes ignore
EN 61010-1 states clearly that creepage is based on RMS values of
the working voltage of the creepage way. A table is provided. (K13 2010 version)
Of course there are multiple columns for OV and CTI and working voltage.
The other 2 of your list are ignored in this standard.
WV is defined
12, 2014 12:07 PM
To: Brian Oconnell; EMC-PSTC@LISTSERV.IEEE.ORG
Subject: RE: [PSES] Creepage and RMS
EN 61010-1 states clearly that creepage is based on RMS values of
the working voltage of the creepage way. A table is provided. (K13 2010 version)
Of course there are multiple columns for OV
Thanks all, for your point(s) of view and 2-cents.
Resuming my conclusions:
- Creepage cannot be shorter than clearance. I think that is clear to most of
us.
- Clearance is essentially based on peak voltage stressing an specific
insulator. Even short time transients may breakdown insufficient
Experts,
I have some questions about 61010 creepage and clearance testing
It looks like much of the testing requirements apply to over voltage
category (OVC) II circuits (e.g., 6.7.2 6.7.3).
a) How does one demonstrate a circuit is
OVC I instead?
b) If it is OVC I, are those tests
completely
Hi Lauren,
I just joined on to this list, so I'm not sure where you're at in the
process, but based on your description of this circuit you should be
looking at 6.7.3 for creepage and clearance. This section is for secondary
circuits like those supplied by bricks on strings.
You should
, supplementary, or reinforced
insulation, including clearances and creepage distances.
Consequently, IEC 61010-1, IEC 60950-1, and IEC 62368-1
have requirements based on overvoltage category.
Overvoltage category II is the common household and
commercial voltage levels, 120 in North America and 230
in most
Dear Experts,
I have some questions about 61010 creepage and clearance testing...
It looks like much of the testing requirements apply to over voltage category
(OVC) II circuits (e.g., 6.7.2 6.7.3).
a) How does one demonstrate a circuit is OVC I instead?
b) If it is OVC I
of IEC61010-1, HBSE would be a good tool here; and Mr.
Nute could provide something interesting on this subject.
Brian
From: Crane, Lauren [mailto:lauren.cr...@kla-tencor.com]
Sent: Wednesday, March 26, 2014 10:36 AM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] 61010 testing fine points for creepage
fine points for creepage and clearance.
Dear Experts,
I have some questions about 61010 creepage and clearance testing...
It looks like much of the testing requirements apply to over voltage category
(OVC) II circuits (e.g., 6.7.2 6.7.3).
a) How does one demonstrate a circuit is OVC I
'
Subject: FW: Test Voltages for secondary circuit creepage distances IEC/EN
61010:2010 section 6.7.3
Ray
You kindly helped me a few months ago on the changes between Ed 2 Ed 3 of
the standard, and we have been getting into it in quite a lot of detail in
my new contract job - but we have run
In message 000f01cdfe22$c5c88b50$5159a1f0$@blueyonder.co.uk, dated
Tue, 29 Jan 2013, John Allen john_e_al...@blueyonder.co.uk writes:
You kindly helped me a few months ago on the changes between Ed 2 Ed
3 of the standard, and we have been getting into it in quite a lot of
detail in my new
for secondary circuit creepage distances IEC/EN
61010:2010 section 6.7.3
In message 000f01cdfe22$c5c88b50$5159a1f0$@blueyonder.co.uk, dated Tue, 29
Jan 2013, John Allen john_e_al...@blueyonder.co.uk writes:
You kindly helped me a few months ago on the changes between Ed 2 Ed
3 of the standard, and we have
Hi Ian:
I think the short answer to your question is that under 60950 there are
no requirements for creepage and clearance distance between the Ethernet
circuit and ordinary SELV circuits that are user-contactable. This
is because under 60950, Ethernet is classified as an SELV circuit
for international safety standards which may impose
creepage and Clearance distances.
Also people forget there can be a lot of current coming from a shared PoE DC
supply and eventhough safety requirement creepage and clearances do not apply
between the high and low voltage rails it is good to impose
is a limited power source (LPS).
However, TNV-1 creepage/clearance requirements would apply if the POE were to
be exposed to overvoltages from telecommunication networks (essentially off
premise) requiring Basic insulation. I make this distinction as Ian did not
mention where the POE circuit originates
back to Ian's original question, though, one could ask what the
effect would be of classifying his Ethernet port as a TNV-1
circuit. I'm speaking from memory here, but as I recall the TNV-1
classification does not invoke explicit creepage and clearance distances
(these are only called out for TNV-2
rpick...@equinoxpayments.com
To:
EMC-PSTC@LISTSERV.IEEE.ORG,
Date:
11/26/2012 12:38 PM
Subject:
Re: [PSES] POE creepage clearances
Hi Joe,
I agree that an Ethernet circuit would be considered to be an SELV circuit
and that would be true if the POE circuit were completely on premise
generally
@LISTSERV.IEEE.ORG
Subject: Re: [PSES] POE creepage clearances
The external DC power supply needs to be SELV too, not just energy limited.
___
Ralph McDiarmid | Schneider Electric | Solar Business | CANADA
the creepage and clearance and keep moving.
ps. I am not a safety engineer and have no clue...
I suspect that the 1500 v isolation came from a single fault introduced at the
PoE injector that tied primary to secondary and thus the PoE device needed to
also have the isolation to withstand that fault
) and
(2) the DC-DC converter input and output (provided by the
equipment).
However, 60950-1 does not require clearance or creepage
across these isolations.
Best regards,
Rich
-Original Message-
From: Bill Owsley
Sent: Monday, November 26, 2012 5:48 PM
To: ralph.mcdiar...@schneider
Dear colleagues
We are developing a hand held product that is powered from +48V DC over
Ethernet or from an external +12V DC wall wart PSU. The maximum internal
voltage will be the +48V POE.
Can anyone let me know what the creepage and clearance requirements between the
primary Ethernet
. The maximum
internal voltage will be the +48V POE.
Can anyone let me know what the creepage and clearance requirements
between the ?primary? Ethernet circuit and the ?secondary? circuit.
Insufficient data. Is the secondary circuit electrically accessible to
the user?
The product
-global.com
www.allen-heath.com
A DMH Pro Company.
-Original Message-
From: emc-p...@ieee.org [mailto:emc-p...@ieee.org] On Behalf Of John Woodgate
Sent: 23 November 2012 11:40
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: POE creepage clearances
In message
7b970d3d82cee74c920c2e6b0d3b837720be4
In message
7b970d3d82cee74c920c2e6b0d3b837720be5...@sn2prd0610mb358.namprd06.prod.o
utlook.com, dated Fri, 23 Nov 2012, Mcburney, Ian
ian.mcbur...@dmh-global.com writes:
I have not started applying IEC 62368-1 as the testing agency I use has
not recommend it. Is IEC 62368-1 the preferred
Does anyone know of where l can find a creepage and clearance calculator on the
net please for EN611010-1:2010
Thanks,
Regards
Ian White
Compliance and Reliability Engineer.
_
Spirax-Sarco Engineering Plc. This e-mail has
: emc-p...@ieee.org [mailto:emc-p...@ieee.org] On Behalf Of Richard
Nute
Sent: zaterdag 27 februari 2010 2:40
To: Petrie, Craig D
Cc: emc-p...@ieee.org
Subject: Re: Creepage/Clearance and Altitude
Hi Craig:
With regard to clearance, air is the insulator.
As you go up in altitude
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