On Tue, Dec 04, 2007 at 08:38:17PM -0800, Ben Jackson wrote:
On Tue, Dec 04, 2007 at 09:21:29AM -0500, John Luciani wrote:
Using my ancient version of PCB (2005) I created a simple PCB by placing
my DIP-28-300 footprint on a component-side polygon.
This seems to be the exact same bug I
DJ Delorie wrote:
I've been pondering the your first board chapter of the getting
started guide. I want to start small enough that it can be done
without confusion or overload, but not so small that it's useless.
Maybe I should do a few steps.
First board: two-pin jumper, resistor, LED.
В сообщении от Tuesday 04 December 2007 16:58:22 David Griffith написал(а):
Does anyone have footprints for USB jacks?
I have one.
Element[35827 44094 0 0 0 100 ]
(
Pin[-8488 -110 4331 2000 4931 3931 10 edge2]
Pin[8835 -110 4331 2000 4931 3931 11 edge2]
Pad[3324
On Wednesday 05 December 2007, DJ Delorie wrote:
Comments? Ideas?
Another project I am working on has a need for a line amp
card.
The project is listener supported community radio. There are a
bunch of community organizations all just getting started, all
on very tight budgets. I am
One way you can do this today is to at the schematic level add a
footprint attribute to each symbol as you place them. The pain is that
if you have a thousand resisters you have to do each one individualy.
I tend to create symbols that have a predefined foot print and then only
override it at the
Good. Just like you proposed. I like it better than the incremented
proposals... KISS
Alain
DJ Delorie escreveu:
I've been pondering the your first board chapter of the getting
started guide. I want to start small enough that it can be done
without confusion or overload, but not so small
Hi, I am new to gEDA, but I used orcad+tango for many years.
I would like to suggest something in this light versus heavy library thread:
Could it be that when the user inserts a light symbol in the schematic,
he also adds a light footprint (in the schematic editor) and from then
on, it
Ben Jackson wrote:
I'd actually like to see a video that goes through the entire process
so you can't cheat and skip steps...
Video sells. That's a fact.
John G
--
Ecosensory Austin TX
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Dave,
Well the netlister needs to be able to read in the schematic files and
eco file and then modify the schematic files. I have a version of a
netlister that generates a netlist the traditional flat netlist way and
then reads in an eco file which it uses to modify the netlist. It isn't
100% so
Steve Meier wrote:
Eventually, I would also like to see being able to define the logic
level for a group of pins, can the pins be used differentialy? if so
which pins are paired? Can we swap pins if so which ones?
The pin swapping question brings up another of my pet peeves -- when the
same
On Dec 5, 2007, at 12:52 PM, Dave N6NZ wrote:
I've been pondering the your first board chapter of the getting
started guide.
555? People still use them? They cost as much as a whole
microcontroller
these days.
All the time. I used one in a commercial design two years ago.
On Dec 5, 2007 12:01 PM, DJ Delorie [EMAIL PROTECTED] wrote:
I would probably add a pot to this one (or a header for a pot).
The trimmers all have different footprints; I figured pretty much
everyone has a generic resistor and LED.
I was thinking of a pot with a knob. You could do a header
On Wed, Dec 05, 2007 at 11:35:03AM -0500, DJ Delorie wrote:
Comments? Ideas?
Don't shy away from new symbol and footprint creation. That's a very
necessary part of building any but the simplest boards.
The problem I remember with existing tutorials is that they gloss over
things like how to
DJ Delorie wrote:
I've been pondering the your first board chapter of the getting
started guide.
555? People still use them? They cost as much as a whole microcontroller
these days.
But a microcontroller isn't a good first project, so a 555 has it
merits -- you don't need a device
Congratulations! You win the humor challenged slow reader award for
today :)
-dave
Dave McGuire wrote:
On Dec 5, 2007, at 12:52 PM, Dave N6NZ wrote:
I've been pondering the your first board chapter of the getting
started guide.
555? People still use them? They cost as much as a whole
DJ Delorie wrote:
I've been pondering the your first board chapter
First board: two-pin jumper, resistor, LED.
Second board: 555 blinky light. power jack,
Third: 555 SMT blinky. mostly SMT, with a ground plane
Comments? Ideas?
Sounds great DJ. We could also divide up into multiple
On Dec 5, 2007 12:08 PM, DJ Delorie [EMAIL PROTECTED] wrote:
I was thinking of a pot with a knob. You could do a header in
parallel with a resistor in a resistor divider. With or without the
pot you would still get the light.
Perhaps a pot on the 555?
I really want to keep the first
On Dec 5, 2007 11:35 AM, DJ Delorie [EMAIL PROTECTED] wrote:
I've been pondering the your first board chapter of the getting
started guide. I want to start small enough that it can be done
without confusion or overload, but not so small that it's useless.
Maybe I should do a few steps.
I've been pondering the your first board chapter of the getting
started guide. I want to start small enough that it can be done
without confusion or overload, but not so small that it's useless.
Maybe I should do a few steps.
First board: two-pin jumper, resistor, LED. All stock symbols and
Doh! Do I get a hat for that? ;)
-Dave
On Dec 5, 2007, at 1:17 PM, Dave N6NZ wrote:
Congratulations! You win the humor challenged slow reader award for
today :)
-dave
Dave McGuire wrote:
On Dec 5, 2007, at 12:52 PM, Dave N6NZ wrote:
I've been pondering the your first board
Eventually, I would also like to see being able to define the logic
level for a group of pins, can the pins be used differentialy? if so
which pins are paired? Can we swap pins if so which ones? What are the
power requirements (max and min) use this for drc checking. How about an
attribute that
And I would not place instructions about installation of gEDA at the
start of the manual.
Not gEDA, just pcb. And you have to install pcb before you can use it
:-)
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On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote:
One way you can do this today is to at the schematic level add a
footprint attribute to each symbol as you place them. The pain is that
if you have a thousand resisters you have to do each one individualy.
I basically do this. I
I was thinking of a pot with a knob. You could do a header in
parallel with a resistor in a resistor divider. With or without the
pot you would still get the light.
Perhaps a pot on the 555?
I really want to keep the first board simple.
___
I would probably add a pot to this one (or a header for a pot).
The trimmers all have different footprints; I figured pretty much
everyone has a generic resistor and LED.
For board 1 you could probably get some ideas from the
beginners kits that are sold in places like You-Do-It Electronics
Steve Meier wrote:
Dave,
I have been thinking that the way to do back annotation is to add a
schematic level attribute that is attached to a symbol. Something like
C 8500 9600 1 180 0 big_fpga-1.sym
{
T 8300 9100 5 10 1 1 180 0 1
refdes=U1
T -100 -100 5 10 1 1 180 0 1
Simple question... How do I get an off page connector to work sensibly
for a bus? By that I mean... a single off page symbol tied to the bus
to represent all the signals.
-dave
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Dave,
Are you asking for hierarchical buses?
Steve Meier
On Wed, 2007-12-05 at 14:45 -0800, Dave N6NZ wrote:
Simple question... How do I get an off page connector to work sensibly
for a bus? By that I mean... a single off page symbol tied to the bus
to represent all the signals.
-dave
DJ Delorie wrote:
Maybe I should do a few steps.
My personal feeling is that 3 introductory tutorials\boards is too much.
I would make one very basic, and one advanced.
And I would not place instructions about installation of gEDA at the
start of the manual. The start is a logical position, but
Ben Jackson wrote:
On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote:
One way you can do this today is to at the schematic level add a
footprint attribute to each symbol as you place them. The pain is that
if you have a thousand resisters you have to do each one individualy.
I
Steve Meier wrote:
Dave,
Are you asking for hierarchical buses?
U I don't think so. I just want to have some signals tied to a
bus on two different pages, and I want a single off-page flag on each
page. I guess as long as the signals are named, all the connectivity
will be OK
I've been thinking about this a bit, and here's my 2 cents:
gschem and pcb both really just want light symbols/footprints. It
would never really be a good idea to expect to stick one into the
other, I mean, what if you change packages or something? I guess you
could up rev the schematic
On Wed, 05 Dec 2007 11:11:35 -0800, Steve Meier wrote:
I tend to create symbols that have a predefined foot print and then only
override it at the schemtic level when I need to.
Me too. (see my combined symbol and footprint lib in gedasymbols.org)
I'd be happy to see an obvious extension of
I'd prefer one board which is expanded by advanced stuff in later
chapters.
I don't plan on making later chapters. There is a whole User's
Guide which may be able to take advantage of such a plan, though. In
the Getting Started doc I just want to give people the basics - get
them started.
On Wed, 05 Dec 2007 21:50:14 +, Stefan Salewski wrote:
My personal feeling is that 3 introductory tutorials\boards is too much.
I would make one very basic, and one advanced.
I'd prefer one board which is expanded by advanced stuff in later
chapters. Start with something very simple like
Dave N6NZ wrote:
Ben Jackson wrote:
On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote:
One way you can do this today is to at the schematic level add a
footprint attribute to each symbol as you place them. The pain is that
if you have a thousand resisters you have to do each one
On Wed, 2007-12-05 at 12:43 -0800, Ben Jackson wrote:
On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote:
One way you can do this today is to at the schematic level add a
footprint attribute to each symbol as you place them. The pain is that
if you have a thousand resisters you
Peter Clifton wrote:
I have a vague memory of seeing an auto-increment refdes thing
somewhere. If it doesn't exist (and I just made it up), would it be
useful?
I think it would simply annoy me. I have adopted the convention of
including the sheet number in the refdes, e.g.: C22 is a cap
Steve Meier wrote:
An argument for the marriage of pcb and gschem at least in the file
processing is in being able to have a simulation that includes the
layout.
And when the marriage stays at the file processing level, you can interoperate
with
other tools, OSS or store-bought.
John G
--
On Wednesday 05 December 2007 06:33:43 pm Steven Ball wrote:
I've been thinking about this a bit, and here's my 2 cents:
gschem and pcb both really just want light symbols/footprints. It
would never really be a good idea to expect to stick one into the
other, I mean, what if you change
A common danger in a divorced system is that you pick one package in
gschem and opps a different package for PCB and now your land pattern
wires are wrong for the schematic.
So unless the translator program is checking package to symbol
correctness then be prepared to dead bug. Or else re-fab.
Hi all,
On Sonntag, 2. Dezember 2007, Werner Hoch wrote:
Yes, but it's quit easy doing it in the hierarchical structur of
hdf5:
simulation_n -- plot_n -- table
or
simulation_n -- plot_n -- metadata
simulation_n -- plot_n -- vector_n
Here's a first shot of a spice2hdf5 converter script:
Bob Paddock [EMAIL PROTECTED] wrote:
The BOM should be the master document that populates everything.
[...]
Obviously people on this list are dealing with schematics and PCBs,
so we tend to think of the schematic as the master,
but in the contracting environment the BOM is what rules
On Wed, 2007-21-11 at 13:11 -0500, al davis wrote:
On Tuesday 20 November 2007, Ian Chapman wrote:
I am using Ubuntu 7.04 Feisty Fawn which is my first
serious effort into Linux. This release is only a few months
old. I guess that there is not too much change between Gutsy
and
On Wednesday 05 December 2007, Michael Sokolov wrote:
Yes, you've hit the nail right on the head! That's exactly
how I do it in uEDA, gEDA's evil twin.
In uEDA the master source code for a board is an ASCII text
file named MCL, which stands for Master Component List. It
is not a generated
al davis [EMAIL PROTECTED] wrote:
Why invent a new language? Either Verilog-AMS or VHDL-AMS, the =
structural subset, has everything you need.
I needed something I could implement by myself without any help from the
outside world and without any dependencies. It also needs to run under
UNIX
On Wed, Dec 05, 2007 at 09:21:31PM -0600, Martin Maney wrote:
(1) would the pin still be checked for minimum annular ring size, where
it could fail DRC because it's been reduced to avoid this problem with
the overlaid pads even though the copper is actually still full width?
I expect so.
On Wed, Dec 05, 2007 at 08:07:45AM +0100, Bert Timmerman wrote:
I think we should not create heavy symbols on build time but during run
time (when the part is needed).
+1
What's the difference between a light symbol and a heavy one? It's
just that the heavy symbol has more attributes that
What's the difference between a light symbol and a heavy one? It's
just that the heavy symbol has more attributes that specify it for a
particular component in various ways, no?
No. You also need to adjust pin numbers to match the symbol's pins to
the footprint's pins, one of our current
On Wed, Dec 05, 2007 at 09:56:41AM -0800, Steve Meier wrote:
I also agree that flat files really arn't a good way to capture a lot of
relevent information. I shudder thinking about a library of 10 million
resistors one for each manufacturor each package, each value etc.
This reminds a little
There would be a ten million part library for resisters if you rrestrict
yourself to a flat file format that limits the expression of the data so
that it can't capture natural regularities of that universe of components
Which was my point and why DJ got a bingo for the db reasoning. Yes
heavy
On Wed, Dec 05, 2007 at 10:22:46AM -0800, Ben Jackson wrote:
On Wed, Dec 05, 2007 at 11:35:03AM -0500, DJ Delorie wrote:
Comments? Ideas?
Don't shy away from new symbol and footprint creation. That's a very
necessary part of building any but the simplest boards.
+1
The tutorials I
It is an animated inductor, it gets very depressed when you call it a
paperclip! It wishes that it had a iron core, but alas it is air
core.
:-)
On Dec 6, 2007 9:31 AM, Dave N6NZ [EMAIL PROTECTED] wrote:
Peter Clifton wrote:
I have a vague memory of seeing an auto-increment refdes
Dave,
That left me sputtering. May I suggest an upgrade.
First that paper clip should mearly pop up, wink and say I got ya!
Then the hunt is on and you need to figure out did a refdes change? A
foot print? a value? hey any attribute is fair game.
Steve Meier
Steven Michalske wrote:
It is an
On Wednesday 05 December 2007, Michael Sokolov wrote:
al davis [EMAIL PROTECTED] wrote:
Why invent a new language? Either Verilog-AMS or VHDL-AMS,
the = structural subset, has everything you need.
I needed something I could implement by myself without any
help from the outside world and
As long as its semantics is well enough deffined that I can write a
macro to read and write its file formats then why not?
al davis wrote:
On Wednesday 05 December 2007, Michael Sokolov wrote:
al davis [EMAIL PROTECTED] wrote:
Why invent a new language? Either Verilog-AMS or
On Dec 6, 2007, at 2:46 PM, Steve Meier wrote:
As long as its semantics is well enough deffined that I can write a
macro to read and write its file formats then why not?
It might be nice, but who knows what it is, and how to reasonably map
it onto our problem? Al's always selling Verilog.
John,
The beauty of geda and its scheme capabilities is that any file format
that is reasonably well deffined can be supported.
Instead of railing at at Al start helping to nail doen the deffinitions
on the formats your prefer.
As I have said my short term goals are to provide output support
On Thursday 06 December 2007, John Doty wrote:
It might be nice, but who knows what it is, and how to
reasonably map it onto our problem? Al's always selling
Verilog. But I went and bought the book he recommended on
Verilog-AMS, and it was mostly more sales pitch.
I AM REALLY TIRED OF THE
On Dec 6, 2007, at 3:38 PM, al davis wrote:
On Thursday 06 December 2007, John Doty wrote:
It might be nice, but who knows what it is, and how to
reasonably map it onto our problem? Al's always selling
Verilog. But I went and bought the book he recommended on
Verilog-AMS, and it was
On Dec 6, 2007, at 3:13 PM, Steve Meier wrote:
John,
The beauty of geda and its scheme capabilities is that any file format
that is reasonably well deffined can be supported.
Indeed. Give me a well defined format with a clear use, I might even
help.
Instead of railing at at Al start
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