tell me what the functional
replacement is (or if it's simply unnecessary now) I can fix the plugin.
Levente: You could simply delete that line from the source and recompile.
The worst that might happen is that you have to force the screen to redraw
somehow after autocropping.
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as I can
get. I don't know if there's any connection between the DC and AC losses.
Not X7R.
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controllers included).
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dependencies.
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faster, and it can be merged into the core later.
The bulk of the solution may be in my autocrop plugin: It knows how
to move everything.
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and you have
$200, Alibre Design works the same way.
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!
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or printing problem goes away.
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?
No. Not for operations that operate on selected pads.
This was an olld bug in de-selection. It worked like an anti-selection
of a rectangle covering everything. Unfortunately it honored visibility
and if you hid a selected item it stayed selected until you made it
visible again!
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On Mon, Nov 08, 2010 at 02:32:08PM -0500, DJ Delorie wrote:
In theory, the 3AN can drive the DVI at 1024x768x24 but we'll see how
much logic I can actually cram into it.
Does the 3AN really meet the DVI spec without a cable driver?
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their docs locked up like a virgin princess.
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DMA via subdata.
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the data into the whole
32-bit float you could probably manage to use the exponent bits too.
But you can always use a 2, 3 or 4 float attribute as well.
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and requires less head turning.
It did cost $1000, though, and 20 LCDs are given away in cereal boxes
these days.
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since they're considered numbers.
You might be able to get around this with quoting. Or hey, output ODF
directly! :)
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showing
that problem on the web page!
It's OK in postscript and gui
It's BAD in gerber and png
That's an odd combo. PS, most flavors of GUI and gerber use the dicer to
draw polygons, while PNG can use erasure, which might explain something.
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pins just below C2. The rectangular
hole is the result of the dicer cutting through the middle of a pin
(could have been any of the pins at that grid point) vertically. That
slice got messed up because of the glitch by the IC.
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to find the bad poly-sub operation
and then go back and single-step through that one.
Maybe we need a debug HID. ;-)
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numbering (diode-1, diode-2). The nice thing about standards is that
there are so many to choose from.
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they happen to clone.
If the public repo is separate (typically bare) and you push to it, users
will not have this issue.
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on ANY
standard parts library. And if you're making footprints and symbols,
text files generated by scripts are FAR superior to any GUI. I'd never
get 100-1000 pins right if I had to use a GUI.
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ever seen their IPC pattern / component wizard, you wouldn't be
saying this.
Not OT. Put up a video showing it in action. Mabye geda hackers will
be inspired. I really think one thing holding back geda is that the
users and developers don't have much experience with high-end tools.
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I hadn't seen this one:
http://charliex2.wordpress.com/2010/01/08/lpkf-easycontac-test/
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any sequences
that trigger the problem. It might be possible to just modify AVRdude
to detect such sequences and modify the programming sequence to avoid
them. Sort of like bit stuffing with NRZI.
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it) and then you control both
ends.
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On Wed, Feb 17, 2010 at 02:45:22PM -0500, Bob Paddock wrote:
Anyone know of a proto-house that will do 0.031 thick boards?
I'm not there to measure it but I think the boards I got back from
Sierra Proto Express's no touch service were 0.032. Thinner than
I expected, anyway!
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polygons using the GUI.
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lines and set *them* to merge with the poly. If I want
low impedence I just make a + of wires.
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at all?
I think so. Like others I wrote my own boxsym program so I don't know
if DJ's is trying to enforce numeric pins.
Here's an example of a BGA on gedasymbols:
http://www.gedasymbols.org/user/darrell_harmon/symbols/xilinx/index.html
They have alphanumeric pin names.
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the power and IO.
The symbols are also at http://gedasymbols.org/user/ben_jackson/
I could upload an Altera EP2C8 set of symbols if that would help.
One symbol per IO bank, power, and config, iirc.
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bit to the pins 1 and 2. Of course the xy position is
the mathematical mean value of the three vectors and in this sense
correct. But this differ from the real body center imho.
Use center of the bounding box instead? The code is in src/hid/bom/bom.c
PrintBOM.
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cost about the same as Epilog's
lowest-end machine (the zing).
http://www.rabbitlaser.com/products/laserse.htm
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, though, the polygon code could do all of your Inkscape steps
internally.
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On Wed, Jan 20, 2010 at 09:20:34PM -0800, Dave N6NZ wrote:
On Jan 20, 2010, at 1:01 PM, Ben Jackson wrote:
I have been thinking about how to do improved isolation routing.
How do you differentiate between pads that must be a certain shape, like for
an SMT capacitor, and islands
segments.
Not me, that was the *other* Dave who was using inkscape, the Dave that
started this thread. I'm just thread-jacking to talk about paste stencils :)
I can only handle one Dave at a time!
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.050mm QFP (about 0.020) with and without mask between the
pads and I didn't find a big difference.
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On Sun, Jan 10, 2010 at 05:28:05PM -0800, David Griffith wrote:
This sounds like the solution. Do you have any sample code or pseudocode
on how to do it?
Something like http://en.wikipedia.org/wiki/Rotating_calipers or one of the
references from that article is probably on point.
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On Sat, Jan 09, 2010 at 05:41:05PM -0800, Ben Jackson wrote:
I meant automatic solutions which would enforce the normal DRC rules on
the slivers, eliminating any smaller than the minimum trace width.
(replying to myself)
Actually, I think I just figured out how to fix it AND do it live
how to fix this, and I can
see options for doing in in a post-processing step, but that's not really
in line with PCB's other polygon updates, which are all done live.
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will go way down...
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On Thu, Dec 03, 2009 at 03:34:02PM +, Ineiev wrote:
Try polygons.
Maybe the documentation should include a snippet of a board which is a
clickable image map. Then each region can link to a 'howto'. Now we
just need an imagemap HID to export it...
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with kapton tape so it could be soldered
flat to the board. Magnet wire is so small it didn't bunch up when taking
off busses and stuff.
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the more laborioius 1) find, 2) click drag.
Of course this is fully incompatible with gEDAs current design.
Not at all. The netlister that makes PCBs could place the components
somewhere other than 0,0. It just doesn't...
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where I could use something
like this. Too bad they want to generate a sales lead in return for
giving you a link to the datasheets. Luckily they're not bright enough
to obscure the link:
http://www.micrel.com/_PDF/Ethernet/ethernet_datasheet/
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' (detect renames) are on commands like 'log', 'show', etc.
So what you'd really want as a feature is not 'tracking' but the
ability for merge to track functions across files just like it currently
can across renames.
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just think digikey stocks the wrong part.
I've attached my footprints and symbols, which you can see in action here:
http://ad7gd.net/geda/panelusb-sm.jpg
The 'blade' shaped post is snug on my footprint because of the seating
issue I described.
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the
panels free with an ancient embedded PC driving them. Watched Monday
Night Football on it last night! :)
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from the one I picked (which include HD and VGA inputs) don't have docs
online.
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should use donated funds to fly us all to a central party^H^H^H^H^H
location.
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be a problem. I remember a design
with a big honking FPGA and a POLA that was a few inches away due to board
constraints. Someone in a meeting mentioned that the 20A 1.2V was sagging
50mV at the FPGA. Do the math and that's only 2.5mOhm drop but still
meant the *plane* was dissipating a *watt*.
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. If you want to limit the
distribution you could send it to geda-dev or just the PCB developers who
work on polygons (me, Peter, DJ)
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at different offsets).
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for square pads?
I don't know anything about the root of your problem, but the easiest
way to avoid a problem with square pads would be to edit the pads to
make them 1 wider or longer so they are no longer square (of course
they'll only be out of square by .1).
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to work around in pcb. Gah! I wish
they'd get with the program and upgrade their software already.
Is it worth adding features to gerbv to warn about known issues?
Some kind of fab DRC that would warn about known brokenness in other
tools.
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On Fri, Aug 14, 2009 at 10:47:13PM +0200, Stefan Salewski wrote:
CNC milling may be more or less related with this thread
http://archives.seul.org/geda/user/May-2009/msg00259.html
especially with the comments of Ben Jackson.
BTW this is where I think you could easily spend
footprints. So
this is probably the degenerate output of some confused m4 macro.
To the OP: Try using 'use-files' to your 'project' file and rerunning
gsch2pcb.
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. If you fix the layer grouping
(first thing in the settings menu) there's only one rat left and no
shorts.
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On Mon, Jul 27, 2009 at 02:04:13AM +0200, Stefan Salewski wrote:
Good question. For my DSO board I have placed the 0805 parts very close,
silk outline nearly touch.
For 0603 with hand assembly I place parts such that the silkscreen overlaps
adjacent parts (if I need close spacing).
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boys handle it. Obviously you can't draw wires in gschem and
then swap pins in pcb and expect the wires to be asthetically re-drawn
in gschem. So do you only do it with busrippers and netname attributes?
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with vias you could try my
jostle plugin which I wrote expressly for moving wires out of the way
to place vias.
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is muuuch faster. VNC was significantly
worse than both (at least for PCB, which is where I spend the bulk of
my time).
If you want to use VMWare, try http://www.easyvmx.com/ (free website
that will make VMs) + VMWare Player (free download).
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multiple sizes of
SMT can oscillators. And I accidentally numbered the pins clockwise. At
least the extra pad area helped me blue-wire the power...
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to speed
the drying. Where I used to work we had a can of some kind of solvent that
worked faster and dried faster but I never bought any myself.
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/Pb compatible
tips suck for lead free. They make special (hotter) tips for lead
free, which I find suck for leaded solder (can't seem to keep them
wetted).
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') is to leave the affected objects on a grid.
So a Align(X) on a single item will put it back on the X grid. So a key
binding to Align(X); Align(Y) would put one selected item back on the grid.
(Of course it would take a multi-selection and smash it all on top of
each other...)
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only mailer which prefers the text/plain
section. If we must keep mangling HTML, either remove it (if a text/plain
already exists) or properly order the sections so that the original
mailer's text/plain is preferred instead of the illegible output of the
list's filter.
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b
).
You could push it to the repo as a branch so that other people still only
had one public repo to deal with. Then after we tag and release from
master you can merge it down.
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On Sat, May 23, 2009 at 08:42:48AM +0200, Ernst van Spronsen wrote:
Ok, How do I disable the M4 libraries? At least for this project?
Thanks.
In your project file add:
use-files
skip-m4
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as formatted by the original
mailer?
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) will
create loops in the skeleton, which we want to keep. Peninsulas of
non copper will produce stubs (which do not serve to actually isolate
any region -- imagine a P shape simplified to an O). If you use a
library like CGAL these should be removed.
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) and then I just try to keep kits on hand so that I know I
have any value of resistor I want (currently in through-hole and 0805).
Connectors I'm really bad about. I tend to go through my collection of
connectors every time I need something.
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over
the output (you'd probably end up drawing some spurious traces to steer
it), but it could be done.
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it, but it
sounds interesting.
Frankly, having come to FPGAs from a long history of softare development,
the FPGA guys are working with stone age tools right now. The only reason
FPGA and ASIC projects get done at all is that their scope is vastly
simpler than a typical software project.
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, rather than having to mix it in.
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. Writing Verilog is at the abstraction level of approximately
a macro assembler. At the high end it might reach up into the level of
BASIC.
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it a committer can apply it with
almost zero effort.
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/zifssb/sband.html
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On Wed, Apr 29, 2009 at 11:45:47PM +0200, Stefan Salewski wrote:
Of course: Move mousepointer over the text and press key S.
Unfortunately line thickness is the board minwidth.
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, but you can recover with
'git reset --hard origin/before_pours'. You can even just do 'git fetch;
git reset --hard origin/before_pours' to skip all merging/rebasing.
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on a column cause the internal pullups to take several clocks to rise.
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into this? Is this a problem?
Perl uses host integer width. Those tests may not fail on a 64 bit perl.
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global sources, only embedded and local
directories. I know some people use a similar workflow already, but maybe
we should automate it to encourage people.
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'autogen.sh'. It makes configure and
Makefile.in (from Makefile.am). Yet another level of automake indirection!
configure: creating ./config.status
Maybe someone committed a configure but not a Makefile.in? It should
probably be removed from the repo if it exists.
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On Wed, Apr 08, 2009 at 02:12:10PM -0700, William Estrada wrote:
Hi group,
Does anyone have a sym file for the FT232RL?
Attached. I used this successfully in a design.
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v 20061020 1
B 300 600 1500 3800 3 0 0 0 0 0 0 -1 -1 -1 -1 -1
T
think the GNU radio guys use one of those to pump data to/from
a Cyclone FPGA).
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On Mon, Apr 06, 2009 at 10:03:36PM -0400, DJ Delorie wrote:
I tried adding serpentines but there isn't enough room to add more
Excellent news for PCB, though. If DJ has trouble laying out serpentines
or trombones, a plugin is sure to follow. ;-)
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/fail
you'd need a very fast (6G+) scope.
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, board edge is on-center)
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Ben Jackson AD7GD
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your vendor. I've used 0.025 before at a place with 8/8 rules.
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probes and other connectors (typically mictor) and
cost $1500/set.
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, which is
a big help as well.
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with an angle grinder? You have balls of
steel!
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. These happen when your pin is slightly off
grid and your line settings cause the tiny makeup angle to be at the end
of the line.
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by common cause (insufficient clearance, too-small
annular ring, etc). Plus it could have buttons like force annular ring to
min size.
I also like the idea of a DRC layer. I think you still need something like
the dialog to help you navigate it.
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http
the gerbers. That's another thing we can't
express.)
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colour schemes that seem wierd to normal people.
I agree.
Personally, I'd say that a .pcb file should describe the attributes of
the PCB itself, not how the application should display it. Things like
display colours of layers should be defined by the user's global
settings.
I agree.
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On Sun, Mar 01, 2009 at 01:46:40PM +0100, Stefan Salewski wrote:
On Sat, 2009-02-28 at 16:51 -0800, Ben Jackson wrote:
I just spent a couple hours debugging a half-broken AVR microcontroller
which was due to me putting GND and UGND (USB GND) far apart on the
symbol and forgetting to connect
.
Even when producing gerbers you will create an 'outline' layer to define
the actual PCB area for the manufacturer.
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will figure out how to use the DRC backends of gnetlist now...
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