Hi Marcus,
Option 1 is probably the most preferred route as the code is much more
likely to say in-sync and compatible if it¹s in the same repository and
tested along side gem5. The best way to proceed with that option is to
post your patches to the gem5 review board http://reviews.gem5.org. If
changeset ef2c71a5f02e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ef2c71a5f02e
description:
cpu: add support for outputing a protobuf formatted CPU trace
Doesn't support x86 due to static instruction representation.
diffstat:
src/cpu/InstPBTrace.py
changeset 61a0b02aa800 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=61a0b02aa800
description:
cpu: Remove all notion that we know when the cpu is misspeculating.
We have no way of knowing if a CPU model is on the wrong path with
our
changeset 3c42be107634 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3c42be107634
description:
arm: always set the IsFirstMicroop flag
While the IsFirstMicroop flag exists it was only occasionally used in
the ARM
instructions that gem5 microOps and
changeset aef704eaedd2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aef704eaedd2
description:
sim: Clean up InstRecord
Track memory size and flags as well as add some comments and consts.
diffstat:
src/cpu/base_dyn_inst.hh| 10 +-
changeset fae54a666162 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fae54a666162
description:
cpu: Put all CPU instruction tracers in a single file
diffstat:
src/arch/arm/ArmNativeTrace.py | 2 +-
src/arch/sparc/SparcNativeTrace.py | 2 +-
changeset c3fd4c020e49 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c3fd4c020e49
description:
cpu: remove legion tracer
If someone wants to debug with legion again they can restore the
code from the repository, but no need to have it hang around
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On Jan. 14, 2015, 6:13 p.m., Nikos
That is doable. You can created checkpoints, there is just no way to
instrument every basic-block.
Ali
On 1/13/15, 3:13 PM, mike upton via gem5-dev gem5-dev@gem5.org wrote:
Oh, Bummer.
I was hoping to be able to get simpoints out of a KvmCPU run.
It seems like that is not possible.
Is it
It should probably be /usr/bin/env python
Ali
On 1/9/15, 1:12 PM, mike upton via gem5-dev gem5-dev@gem5.org wrote:
OK, thanks.
I don't understand what is going on, but blindly following the suggestion
made it work.
I needed to do:
python /usr/bin/scons gem5 options
Oh, I see what is going
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On July 24, 2014, 7:44 p.m., Anthony
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the only file that is here is the change to the conscript... where are
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On Dec. 26, 2014, 9:32 p.m., Gabe
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seems fine to me, although I can't say I know the code well
-
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Seems fine... Anyone who deals with Ruby OK?
- Ali Saidi
On
The in-order cpu model is deprecated and will soon be removed from the tree. Id
you'd like an in order cpu model use the minor cpu model which supports ARM.
Ali
Sent from my ARM powered mobile device
On Dec 17, 2014, at 2:18 PM, Anastasiia via gem5-dev gem5-dev@gem5.org
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I think it’s fine that a device wants to do this, I’d just like it to use an
thin interface on the System object as a matter of clean interfaces in the
object hierarchy, so unrelated objects don’t have to know about each other.
Ali
On Dec 3, 2014, at 11:54 AM, Gabe Black via gem5-dev
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looks like a substantial improvement... visually seems fine
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On Dec. 3, 2014, 7:10 p.m., mike upton
Hi Gabe/Steve,
As Steve mentioned I¹ve been working on a new take on the regression
system in my spare-time.
I want to get it a bit more complete before I show it to the world, but
some of the goals I set out with align with yours.
In particular I¹m targeting the following:
(1) Success/Failure
On Dec. 4, 2014, 3:03 p.m., Nilay Vaish wrote:
src/sim/syscall_emul.hh, line 201
http://reviews.gem5.org/r/2548/diff/1/?file=42865#file42865line201
How will the compiler choose between the two versions of unlinkFunc? I
think we should either drop the default argument or drop the
daystrom is very low on ram at the moment with the various services we’re
running. We have a new machine that has substantially more ram that we’ll be
switching to in the near term which should address the issue. For the moment
I’ve restarted tomcat and it seems to be working.
Ali
On Nov 28,
There are functions that correspond to this functionality although they’re
poorly named for the purpose, but memWriteback() - beginning of KVM
simulation; memInvalidate - end of KVM simulation. Another option would be to
check for the memory time atomic_noncaching which I believe only KVM uses.
On Nov 26, 2014, at 12:11 PM, Steve Reinhardt via gem5-dev gem5-dev@gem5.org
wrote:
On Wed, Nov 26, 2014 at 4:30 AM, Gabe Black via gem5-dev gem5-dev@gem5.org
wrote:
Just to make sure we're all on the same page, I removed the spaces here
because these are default values for arguments.
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On Nov. 22, 2014, 11:39 a.m., Gabe
On Nov. 25, 2014, 10:02 p.m., Nilay Vaish wrote:
configs/common/Options.py, line 155
http://reviews.gem5.org/r/2516/diff/1/?file=42704#file42704line155
Can you explain why we need this separate option for restoring from a
checkpoint taken using the take-simpoint-checkpoints?
The
Looking at the code it looks like it would be possible for there to be 12
bytes in the socket, so the read will return less that 12 bytes (because
you got very unlucky and the bytes were split across two packets).
Looking at the code fixing that assumption will be a bit of a pain.
Ali
On
What compiler and version are you using?
Ali
On 11/17/14, 2:37 PM, Urmish Ajit Thakker via gem5-dev
gem5-dev@gem5.org wrote:
Hi,
I pulled up the latest copy of gem5 and got the following error while
building gem5.fast.
build/ARM/proto/protoio.fo (symbol from plugin): warning: memset used
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This will break compilation on non-linux platforms, so if we need
changeset d1dce0b728b6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1dce0b728b6
description:
arm: Fix timing wakeup with LLSC
diffstat:
src/cpu/simple/timing.cc | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diffs (29 lines):
diff -r
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On Nov. 10, 2014, 5:20 p.m., Andrew
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the o3 change seems fine. . someone more familiar with ruby
On Nov. 6, 2014, 7:48 p.m., Cagdas Dirik wrote:
This patch seems to be broken for X86 when restoring from checkpoints. A
sample test crashes with segmentation fault. Here are the steps:
0. Sample test program does int array manipulation and creates a checkpoint
before computation.
On Nov. 6, 2014, 7:48 p.m., Cagdas Dirik wrote:
This patch seems to be broken for X86 when restoring from checkpoints. A
sample test crashes with segmentation fault. Here are the steps:
0. Sample test program does int array manipulation and creates a checkpoint
before computation.
changeset ba51f8572571 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ba51f8572571
description:
tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
diffstat:
These should now be fixed.
Thanks,
Ali
On 11/2/14, 3:20 PM, Cron Daemon via gem5-dev gem5-dev@gem5.org wrote:
*
build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-a
tomic CHANGED!
*
build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
CHANGED!
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On Oct. 29, 2014, 3:01 p.m., Andrew
changeset aa46a8ae3487 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa46a8ae3487
description:
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
changeset aa23216161fa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa23216161fa
description:
arm: Mark some miscregs (timer counter) registers at unverifiable.
The checker can't verify timer registers, so it should just grab the
version
from the
changeset 38c7a9ea7729 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=38c7a9ea7729
description:
cpu: Add support to checker for CACHE_BLOCK_ZERO commands.
The checker didn't know how to properly validate these new commands.
diffstat:
changeset d5554f97c451 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d5554f97c451
description:
arm, mem: Fix drain bug and provide drain prints for more components.
diffstat:
src/arch/arm/table_walker.cc | 5 ++---
src/mem/cache/mshr_queue.cc | 3 +++
changeset b423e1d0735e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b423e1d0735e
description:
arm, tests: Update config files to more recent kernels and create
64-bit regressions.
This changes the default ARM system to a Versatile Express-like system
changeset 2b416ef3b400 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2b416ef3b400
description:
automated merge
diffstat:
src/arch/alpha/linux/process.cc |4 +-
src/arch/arm/linux/process.cc|4 +-
src/arch/mips/linux/process.cc |4 +-
changeset f33fab6214c4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f33fab6214c4
description:
arm: fix bare-metal memory setup.
The bare-metal configuration option still configured memory with the
old scheme
that no-longer works. This change
changeset ca4438b6e39a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ca4438b6e39a
description:
tests: Update regressions for the new kernels and various preceeding
fixes.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
changeset bd7c2aa12122 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bd7c2aa12122
description:
arm, tests: Add 64-bit ARM regression tests
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
| 2431 +++
changeset cae494887847 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cae494887847
description:
arm, tests: Forgot the system.terminal files for the new regressions.
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
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thanks for the patch. it looks good, but I'm not sure if the ruby change
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http://reviews.gem5.org/r/2468/#comment4912
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http://reviews.gem5.org/r/2468/#comment4915
Hi Everyone,
We've noticed an issue with the WriteInvalidate patch where the cpu
reads or writes the same cache line that is being write invalidated.
We're working on a fix and hope to have it out next week. If not we'll
disable the code for the time being.
Thanks,
Ali
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On Sept. 23, 2014, 7:46 p.m., Steve
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On Sept. 23, 2014, 7:47 p.m., Steve
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On Sept. 23, 2014, 7:47 p.m., Steve
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On Sept. 15, 2014, 6:29 p.m., Andrew
On Sept. 15, 2014, 8:34 p.m., Ali Saidi wrote:
Ship It!
Thanks for making the change Andrew.
Ali
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Thanks for finding this Andrew. Could you try to change the order of the
changeset 1aff1376921e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1aff1376921e
description:
arm: Assume we have a kernel that supports pci devices
Change the default kernel for AArch64 and since it supports PCI devices
remove the hack that made
changeset 1e2f39859382 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1e2f39859382
description:
dev: seperate legacy io offsets from PCI offset
The PC platform has a single IO range that is used both legacy IO and
PCI IO
while other platforms may
changeset 644b615fbe6a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=644b615fbe6a
description:
arm: Support 2GB of memory for AArch64 systems
diffstat:
configs/common/FSConfig.py | 27 +++
src/dev/arm/RealView.py| 9 +
2
changeset 198dfef33403 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=198dfef33403
description:
dev, arm: Add support for linux generic pci host driver
This change adds support for a generic pci host bus driver that
has been included in recent Linux
of this? I personally prefer keeping a buffer of about 2-3 months
between gem5-dev and gem5-stable.
--
Nilay
On Tue, 19 Aug 2014, Ali Saidi via gem5-dev wrote:
Looking through the change sets between now and 10231 there are a number
of compiler and bug fixes along with a few big changes
A patch would absolutely be welcomed. AArch32 mode still exists and gdb
should still work for 32-bit code. This was just an oversight. To be
clear gem5 will support ARMv8 going forward but we plan to support both
AArch32 and AArch64 code.
Thanks,
Ali
On 19.08.2014 18:19, Anthony Gutierrez
Looking through the change sets between now and 10231 there are a number
of compiler and bug fixes along with a few big changes. I think the big
changes are quite contained, so I'd be in favor for making changeset
10283 79fde1c67ed8 the new stable if others were ok with that.
Ali
On
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On July 22, 2014, 2:24 p.m., Ali Saidi wrote:
src/mem/cache/tags/lru.cc, line 177
http://reviews.gem5.org/r/2167/diff/5/?file=40401#file40401line177
why not unsigned?
Anthony Gutierrez wrote:
I made it unsigned because CacheBlk's set field is an int, as well as the
fact
On July 15, 2014, 2:47 p.m., Andreas Sandberg wrote:
Overall, I think this patch looks good and the refactoring is a well-needed
change to the way we implement replacement policies.
At a high level, I'd really appreciate it if you could split this patch
into two patches so the
On May 4, 2014, 11:56 p.m., Steve Reinhardt wrote:
src/python/m5/simulate.py, line 117
http://reviews.gem5.org/r/2246/diff/1/?file=39626#file39626line117
for all these 'if hasattr()' changes (here and below, and in
simulate.py): seems like it would be much cleaner to make sure
On May 4, 2014, 11:56 p.m., Steve Reinhardt wrote:
src/python/m5/SimObject.py, line 654
http://reviews.gem5.org/r/2246/diff/1/?file=39624#file39624line654
This seems kind of complicated, but I'm going to wait for a
higher-level description of what it's doing before I dig into it.
We've talked about this before, but I'd like to bring it up again. I'd l
like to switch the style to 100 character lines. I think it's far
clearer when the majority of the time all the function arguments end up
on a single line and while sometimes you can get around that with
temporaries it's
I think the assert isn’t quite strict enough, it should really be +1 of what it
is now so that forward progress can be made. Remember that all these registers
are taking up physical registers. I think you’re worried about the idea that
there are 160 register is the PRF, and really you should be
Context switches are handled by the linux kernel that is running on the
simulator. When it gets an interrupt (timer) it checks if it needs to context
switch and does.
The kernel is going to set up softIRQs for itself, if you wanted to trigger one
from the simulator you’d either need to go
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On July 3, 2014, 5:13 p.m., Steve
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On July 3, 2014, 5:12 p.m., Steve
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On June 17, 2014, 5:03 p.m.,
On June 30, 2014, 8:34 p.m., Amin Farmahini wrote:
After applying this patch, the minimum number of float regs should be 160,
even for ARMv7 ISA. If you set the number of numPhysFloatRegs to lower than
160, you get an assertion error from cpu/o3/cpu.cc:
assert(params-numPhysFloatRegs
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On June 26, 2014, 9:49 p.m., Anthony
On June 25, 2014, 2 p.m., Andreas Hansson wrote:
Perhaps I am missing something, but why would Ruby forward the packet to
the iobus in the first place if the address is not valid?
Steve Reinhardt wrote:
This is an FS thing, where you misspeculate in the kernel and generate a
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(i.e. between the two QEMU
processes I have shared memory). Hope this short description make sense.
Do you think I can apply a similar approach here?
thanks again,
Antonio
On Sun, Jun 22, 2014 at 12:06 PM, Ali Saidi via gem5-dev gem5-dev@gem5.org
wrote:
Hi Antonio,
Simulating ARM
Hi Antonio,
Simulating ARM x86 at the same time won’t work today. If you wanted to make
it work, you’d need to teach the build system how to generate compile all the
architectures into a single binary, and fix some places in the code where we
use #defines based on the architecture to
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On June 7, 2014, 10 p.m., Joel
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On June 7, 2014, 10:02 p.m., Joel
The KvmCpu is used to fast-forward the simulation using Kvm as the
execution host, not gem5 hosting a Kvm. In theory much of the support
for virtualization has been added to ARM (32-bit) support in gem5, but I
can't say it's been throughly tested. You could always try to boot a
kernel with KVM
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On June 1, 2014, 12:47 a.m., Steve
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Review request for Default.
Repository: gem5
Description
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