Pedro,
I'm not an expert on manufacturing pcbs, but I'm guessing that the
default spacing of 0.010" was picked because it is typical of the
capability of mfrs. The IC that I'm using specifies a spacing of
0.000984" which gets rounded in PCBnew to 0.001". I don't know if this
creates a problem for
wing
another type of pad "BGA" would make better sense.
Thanks and regards,
Doug
--- In kicad-users@yahoogroups.com, "Doug Deeds" <[EMAIL PROTECTED]> wrote:
>
> If I understand correctly, this only changes the mask clearance around
> vias and traces. I need to
ut
how to
> > change the solder mask opening size.
> >
> > I am laying out a 4 bump chip scale package and the default mask
opening
> > is too large. How do I change this dimension?
> >
> > Regards,
> > Doug Deeds
> > Forthright Solutions
> > 817 230 4483
> >
> >
>
Maybe I missed this in the documentation, but I can't figure out how to
change the solder mask opening size.
I am laying out a 4 bump chip scale package and the default mask opening
is too large. How do I change this dimension?
Regards,
Doug Deeds
Forthright Solutions
817 230 4483
I am confused with how Kicad handles library files under Vista.
I have been searching through my hard drive. The original library
file I am using Kicad is located at:
c:\program files\kicad\share\library
but the modified library after editing in the library editor is
located at:
c:\documents a
I create a different schematic symbol for each value of component and
size. For example, 10K_1%_0402. It's always been faster to create
more values by editing the lib file with cut/paste in a text editor.
I have run into problems under the latest version of Kicad. For
starters, the latest ver
Is there a way to change one or all of the micro vias on a board to vias?
Doug
I found it!!!
Well this is my 2nd post. Yahoo crashed when I posted the first reply.
I'll save a copy just in case this time...
None of the above suggestions had any effect. What I found was that
when I moved the Pinsheets/Wire for WEn on the root schematic there
was a small box where the Pinsh
A clue???
I dug into the .sch file for the cpu page and did not find any errant
connections between the two pins. I also looked in the netlist file
and found that both pin 40 and 59 of the micro had similar entries.
Pin 40 showed a line: ( 40 /CPU/CEn ) Pin 59 had ( 59 /CPU/CEn) I
deleted the
PDF prints of both files are in the File area.
Thanks for your help.
Doug
IC is
connected to the CEn output from the PIC. If I change the WEn Hlabel to
a Glabel or Label, ERC indicates that there is no connection for the
pin, but doesn't give the error that it is connected to the CEn pin.
Any ideas on what to look for to correct this?
Regards,
Doug Deeds
Forthright
Just out of curiousity, who is your board house?
Doug
--- In kicad-users@yahoogroups.com, "mkajdas" <[EMAIL PROTECTED]> wrote:
>
> My PCB house DRC check complains about vias having pads on inner layers.
> How to have via pads on the outside and no pads inside the board on 4
> layer board?
> The
In anyone is interested, here's my module data.
Somehow I ended up with two copies of pin 4, one extremely offset; the
other somehow at the end of the list, but in the correct place.
It looks as though the first copy has extra zeros at the end.
Regards,
Doug
$MODULE 39522-1008
Po 0 0 0 15 48090A3E
Dick,
Thanks for your latest comments. I noticed two things that allowed me
to narrow the problem down. First, I ripped up all traces, but the
gerbers and pcb still had the problem. Second, I noticed that an
8-pin connector did not seem to be anchored on pin 1 as expected.
When I went into the
Dick,
Thanks for the feedback. Auto zoom confirms that the problem is in
the board design, not caused by the gerber output. After I auto zoom,
the pcb shrink to a few pixels and a cursor shows up about a third of
the screen away from the upper right. The zoom level and coordinates
shown on the
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