ndaries in case software, or manufacturers, misrepresent smpt
> array fields.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Tudor Ambarus
I think we should consider this patch as a fix. Would you mind adding a
Fixes tag?
> ---
> drivers/mtd/spi-nor/spi-nor.c | 39 +++
ngs
Arnd Bergmann (1):
mtd: docg3: don't set conflicting BCH_CONST_PARAMS option
Boris Brezillon (4):
mtd: nand: Fix nanddev_neraseblocks()
mtd: spi-nor: Reset nor->addr_width when SFDP parsing failed
mtd: sa
On Wed, 7 Nov 2018 20:42:08 +
Hi Colin,
Colin King wrote:
> From: Colin Ian King
>
> Currently max_read_ds is being updated twice, which is incorrect.
> The second assignment should be to max_write_ds instead. Fix this.
>
> Detected by CoverityScan, CID#1475379 ("Unused value")
>
> Fixe
Nitpick: subject prefix should be "mtd: spinand" not
"mtd: nand: spi" :-).
On Thu, 8 Nov 2018 08:32:11 +
Schrempf Frieder wrote:
> Add minimal support for the Toshiba TC58CVG2S0H SPI NAND chip.
>
> Signed-off-by: Frieder Schrempf
> ---
> drivers/mtd/nand/spi/Makefile | 2 +-
> drivers/
Hi Mark,
On Wed, 7 Nov 2018 15:18:36 +
Mark Brown wrote:
> On Wed, Nov 07, 2018 at 03:03:27PM +, Mark Brown wrote:
> > The patch
> >
> >spi: Add QuadSPI driver for Atmel SAMA5D2
> >
> > has been applied to the spi tree at
> >
> >https://git.kernel.org/pub/scm/linux/kernel/git/
On Wed, 7 Nov 2018 15:43:20 +0100
Frieder Schrempf wrote:
> From: Frieder Schrempf
>
> Adjust the documentation of the new SPI memory interface based
> driver to reflect the new drivers settings.
>
> The "old" driver was using the "fsl,qspi-has-second-chip" property to
> select one of two dua
On Wed, 7 Nov 2018 15:43:19 +0100
Frieder Schrempf wrote:
> From: Frieder Schrempf
>
> Move the documentation of the old SPI NOR driver to the place of the new
> SPI memory interface based driver.
>
> Signed-off-by: Frieder Schrempf
> ---
> .../devicetree/bindings/mtd/fsl-quadspi.txt |
On Wed, 7 Nov 2018 16:36:13 +
Schrempf Frieder wrote:
> Hi Olof,
>
> On 07.11.18 17:20, Olof Johansson wrote:
> > On Wed, Nov 7, 2018 at 6:44 AM Frieder Schrempf
> > wrote:
> >>
> >> From: Frieder Schrempf
> >>
> >> The new driver at spi/spi-fsl-qspi.c replaces the old SPI NOR driver
> >
On Wed, 7 Nov 2018 12:08:58 +0100
Christophe Kerello wrote:
> >> +
> >> +write_8bit:
> >> + for (i = 0; i < len; i++)
> >> + writeb_relaxed(p[i], io_addr_w);
> >
> > Is 8bit access really enforced by the byte accessor? In this case, how
> > can you be sure 32-bit accesses are doing t
Hello Michael,
On Thu, 01 Nov 2018 21:18:28 +1100
Michael Ellerman wrote:
> Mark Brown writes:
>
> > On Fri, Oct 26, 2018 at 12:36:14PM -0500, Rob Herring wrote:
> >> On Thu, Oct 25, 2018 at 9:14 AM Linus Torvalds
> >> wrote:
> >
> >> > Are there other situations where you might want to
On Tue, 6 Nov 2018 23:19:14 +0100
Geert Uytterhoeven wrote:
> Hi Boris,
>
> On Tue, Nov 6, 2018 at 10:58 PM Boris Brezillon
> wrote:
> > On Tue, 6 Nov 2018 22:44:16 +0100
> > Geert Uytterhoeven wrote:
> > > On Toshiba RBTX4927, where map_probe is supposed
On Tue, 6 Nov 2018 22:44:16 +0100
Geert Uytterhoeven wrote:
> On Toshiba RBTX4927, where map_probe is supposed to fail:
>
> Creating 2 MTD partitions on "physmap-flash.0":
> 0x00c0-0x0100 : "boot"
> 0x-0x00c0 : "user"
> physmap-flash physmap-f
On Tue, 6 Nov 2018 19:08:27 +0800
Liang Yang wrote:
> On 2018/11/6 18:22, Boris Brezillon wrote:
> > On Tue, 6 Nov 2018 18:00:37 +0800
> > Liang Yang wrote:
> >
> >> On 2018/11/6 17:28, Boris Brezillon wrote:
> >>> On Tue, 6 Nov 2
On Mon, 5 Nov 2018 08:58:35 +0100
Boris Brezillon wrote:
> Enabling -Wvla found another variable-length array with randconfig
> testing:
>
> drivers/mtd/maps/sa1100-flash.c: In function 'sa1100_setup_mtd':
> drivers/mtd/maps/sa1100-flash.c:224:10: error: ISO C90 f
On Tue, 6 Nov 2018 18:00:37 +0800
Liang Yang wrote:
> On 2018/11/6 17:28, Boris Brezillon wrote:
> > On Tue, 6 Nov 2018 17:08:00 +0800
> > Liang Yang wrote:
> >
> >> On 2018/11/5 23:53, Boris Brezillon wrote:
> >>> On Fri, 2 Nov 20
On Tue, 6 Nov 2018 17:08:00 +0800
Liang Yang wrote:
> On 2018/11/5 23:53, Boris Brezillon wrote:
> > On Fri, 2 Nov 2018 00:42:21 +0800
> > Jianxin Pan wrote:
> >
> >> +#define NFC_REG_CMD 0x00
> >> +#define NFC_CMD_DRD
On Tue, 16 Oct 2018 09:13:46 +0200
Christophe JAILLET wrote:
> We return 0 unconditionally in 'cqspi_direct_read_execute()'.
> However, 'ret' is set to some error codes in several error handling paths.
>
> Return 'ret' instead to propagate the error code.
>
> Fixes: ffa639e069fb ("mtd: spi-nor:
'mtd' description in 'panic_nand_wait'
>
> Fixes: f1d46942e823 ("mtd: rawnand: Pass a nand_chip object to
> chip->waitfunc()")
>
> Signed-off-by: Randy Dunlap
> Cc: Boris Brezillon
> Cc: Miquel Raynal
> Cc: Richard Weinberger
Queued to the fixe
On Thu, 11 Oct 2018 13:06:16 +0200
Arnd Bergmann wrote:
> I noticed during the creation of another bugfix that the BCH_CONST_PARAMS
> option that is set by DOCG3 breaks setting variable parameters for any
> other users of the BCH library code.
>
> The only other user we have today is the MTD_NAN
Hi Christophe,
On Fri, 5 Oct 2018 11:41:59 +0200
wrote:
A few more comments.
> +/* Sequencer read/write configuration */
> +static void stm32_fmc2_rw_page_init(struct nand_chip *chip, int page,
> + int raw, bool write_data)
> +{
> + struct stm32_fmc2 *fmc2 =
On Fri, 2 Nov 2018 00:42:21 +0800
Jianxin Pan wrote:
> +#define NFC_REG_CMD 0x00
> +#define NFC_CMD_DRD (0x8 << 14)
> +#define NFC_CMD_IDLE (0xc << 14)
> +#define NFC_CMD_DWR (0x4 << 14)
> +#define NFC_CMD_CLE (0x5 << 14)
> +#define NFC_CMD_ALE
finite waiting
>
> Piotr Bugalski (6):
> mtd: spi-nor: atmel-quaspi: Typo fix
> mtd: spi-nor: atmel-quadspi: Add spi-mem support to atmel-quadspi
> mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi
> driver
> mtd: spi-nor: atmel-quadspi: Remove unus
On Mon, 5 Nov 2018 08:58:35 +0100
Boris Brezillon wrote:
> Enabling -Wvla found another variable-length array with randconfig
> testing:
>
> drivers/mtd/maps/sa1100-flash.c: In function 'sa1100_setup_mtd':
> drivers/mtd/maps/sa1100-flash.c:224:10: error: ISO C90 f
cdev array passed to mtd_concat_create()
instead of using a VLA.
Reported-by: Arnd Bergmann
Signed-off-by: Boris Brezillon
Cc: Kees Cook
Cc: Olof Johansson
---
Changes in v2:
- Allocate cdev dynamically instead of having a fixed-size array
Hello,
I'm planning to queue this patch to the
Hi Abhishek,
On Fri, 20 Jul 2018 15:03:48 +0200
Boris Brezillon wrote:
> On Fri, 20 Jul 2018 17:46:38 +0530
> Abhishek Sahu wrote:
>
> > Hi Boris,
> >
> > On 2018-07-19 03:13, Boris Brezillon wrote:
> > > On Wed, 18 Jul 2018 23:23
Hello Linus,
On Thu, 1 Nov 2018 09:27:20 -0700
Linus Torvalds wrote:
> On Wed, Oct 31, 2018 at 10:35 PM Boris Brezillon
> wrote:
> >
> > Greg, I didn't get your feedback on v10 of the i3c patchset [1] where I
> > was asking if you'd agree to have this framew
Hello Greg,
On Thu, 1 Nov 2018 12:33:30 +0100
Greg Kroah-Hartman wrote:
> On Thu, Nov 01, 2018 at 06:35:23AM +0100, Boris Brezillon wrote:
> > Hello Greg, Linus,
> >
> > Greg, I didn't get your feedback on v10 of the i3c patchset [1] where I
> > was asking if yo
1ccdc61d1:
dt-bindings: i3c: Document Cadence I3C master bindings (2018-11-01 06:12:05
+0100)
Add the I3C framework + an I3C controller driver for Cadence IP
--------
Boris Brez
Hi Huijin,
On Thu, 23 Aug 2018 04:43:39 -0400
Huijin Park wrote:
> From: "huijin.park"
>
> assign of a signed value which has type 'int' to a variable of
> a bigger unsigned integer type 'uint64_t'.
Why are you mentioning u64? AFAICT, the len passed to erase_write() is
always an unsigned int.
Hi Huijin,
Subject prefix should be "mtd: spi-nor: ...", and please replace
"unexpected error" by "unsigned int overflows".
On Thu, 23 Aug 2018 03:28:02 -0400
Huijin Park wrote:
> From: "huijin.park"
>
> the params->size is defined as "u64"
> and, "info->sector_size" and "info->n_sectors" is
Hi Piotr, Tudor,
On Wed, 27 Jun 2018 15:16:03 +0200
Piotr Bugalski wrote:
> Hello,
>
> Atmel SAMA5D2 is equipped with two QSPI interfaces. These interfaces can
> work as in SPI-compatible mode or use two / four lines to improve
> communication speed. At the moment there is QSPI driver strongly
On Wed, 31 Oct 2018 03:18:28 +
"Grandbois, Brett" wrote:
> On 30/10/18 6:26 pm, Boris Brezillon wrote:
> > On Mon, 29 Oct 2018 23:15:42 +
> > "Grandbois, Brett" wrote:
> >
> >> On 28/10/18 1:39 am, Boris Brezillon wrote:
> >>
On Mon, 29 Oct 2018 23:15:42 +
"Grandbois, Brett" wrote:
> On 28/10/18 1:39 am, Boris Brezillon wrote:
> > Hi Brett,
> >
> > On Tue, 16 Oct 2018 00:57:41 +
> > "Grandbois, Brett" wrote:
> >
> >> Add support to expose th
Hi Kees,
On Sun, 28 Oct 2018 19:13:26 -0700
Kees Cook wrote:
> On Fri, Oct 12, 2018 at 2:22 AM, Boris Brezillon
> wrote:
> > On Fri, 12 Oct 2018 11:19:52 +0200
> > Arnd Bergmann wrote:
> >
> >> On Fri, Oct 12, 2018 at 11:16 AM Boris Brezillon
>
Hi Brett,
On Tue, 16 Oct 2018 00:57:41 +
"Grandbois, Brett" wrote:
> Add support to expose the SPI boot flash on AMD Family 16h CPUs as a
> standard mtd device to give userspace BIOS updaters greater feature
> support. The BIOS and Kernel Developer's Guide refers to this as the
> 'SPI ROM'
On Thu, 25 Oct 2018 09:16:53 +0200
Boris Brezillon wrote:
> Hi Mason,
>
> On Thu, 25 Oct 2018 14:44:30 +0800
> masonccy...@mxic.com.tw wrote:
>
> > From: Mason Yang
> >
> > Hi Boris,
> > I patched this for Macronix all 1.8V AC chips.
> > Thanks f
Hi Mason,
On Thu, 25 Oct 2018 14:44:30 +0800
masonccy...@mxic.com.tw wrote:
> From: Mason Yang
>
> Hi Boris,
> I patched this for Macronix all 1.8V AC chips.
> Thanks for your review.
No need to add a cover letter when you only have patch.
> best regards,
> Mason
>
> Mason Yang (1):
> mtd
On Tue, 23 Oct 2018 13:28:09 -0500
Rob Herring wrote:
> On Mon, Aug 27, 2018 at 4:44 AM Johan Hovold wrote:
> >
> > On Mon, Aug 27, 2018 at 10:48:42AM +0200, Boris Brezillon wrote:
> > > On Mon, 27 Aug 2018 10:44:14 +0200
> > > Johan Hovold wrote:
> >
Hi Yogesh,
On Tue, 23 Oct 2018 09:39:25 +
Yogesh Narayan Gaur wrote:
> Hi,
>
> Did we have have any comments or remarks about this patch-series, if not
> please apply.
Sorry, but it was already too late for this release, and the merge
window just started, so it will have to wait at least
On Tue, 23 Oct 2018 09:37:13 +
Yogesh Narayan Gaur wrote:
> Add support for octo mode I/O data transfer in spi-mem framework.
>
> Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
> ---
> Changes for v3:
> - Modified string 'octal' with 'octo'
receive with 8 wires
>
> Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
> ---
> Changes for v3:
> - Modified string 'octal' with 'octo'.
> - Add octo mode support in spi_setup().
> Changes for v2:
> - Incorporated review comments of Boris.
Hi Linus,
On Tue, 23 Oct 2018 09:41:32 +0100
Linus Torvalds wrote:
> So I'm mainly pinging people I've already pulled to see how much
> people actually _care_. Yes, the ack is nice, but do people care
> enough that I should try to make that workflow change? Traditionally,
> you can see that I'v
On Tue, 23 Oct 2018 09:05:23 +
Yogesh Narayan Gaur wrote:
> Hi,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Tuesday, October 23, 2018 2:31 PM
> > To: Yogesh Narayan Gaur
> > Cc: cristian
On Tue, 23 Oct 2018 08:59:22 +
Yogesh Narayan Gaur wrote:
> Hi,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Tuesday, October 23, 2018 2:18 PM
> > To: Yogesh Narayan Gaur
> > Cc: cristian
On Tue, 23 Oct 2018 08:56:46 +
Yogesh Narayan Gaur wrote:
> +struct nxp_fspi {
> + void __iomem *iobase;
> + void __iomem *ahb_addr;
> + u32 memmap_phy;
> + u32 memmap_phy_size;
> + struct clk *clk, *clk_en;
> + struct device *dev;
> + struct completion c;
> +
On Tue, 23 Oct 2018 10:48:27 +0200
Boris Brezillon wrote:
> On Tue, 23 Oct 2018 08:18:35 +
> Yogesh Narayan Gaur wrote:
>
> >
> > I have added the prints in m25p80_read() and in flexspi controller
> > prepare_lut and read_rxfifo() func.
> > In these have
On Tue, 23 Oct 2018 08:18:35 +
Yogesh Narayan Gaur wrote:
>
> I have added the prints in m25p80_read() and in flexspi controller
> prepare_lut and read_rxfifo() func.
> In these have added prints for data variable of struct op and data which
> being read by the controller from the flash.
>
On Tue, 23 Oct 2018 04:47:33 +
Yogesh Narayan Gaur wrote:
> Hi,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, October 22, 2018 5:22 PM
> > To: Yogesh Narayan Gaur
> > Cc: cristian
Create an entry for the I3C subsystem and mark it as maintained by me.
There's no official git repository, patchwork instance, mailing list or
website yet, but this will be added after the subsystem has been
accepted.
Signed-off-by: Boris Brezillon
---
Changes in v9:
- None
Changes
Add a driver for Cadence I3C GPIO expander.
Signed-off-by: Boris Brezillon
Acked-by: Linus Walleij
---
Changes in v9:
- None
Changes in v8:
- None
Changes in v7:
- None
Changes in v6:
- Use kmalloc_array() instead of kmalloc(N * sizeof(X))
- Add Linus' ack
Changes in v5:
- Us
Document sysfs files/directories/symlinks exposed by the I3C subsystem.
Signed-off-by: Boris Brezillon
Reviewed-by: Arnd Bergmann
---
Changes in v9:
- Add Arnd's R-b
Changes in v8:
- None
Changes in v7:
- Bump KernelVersion to 4.20
- Add new entries under i3c- now that the master contr
+Mark
Hi Yogesh,
On Mon, 15 Oct 2018 12:13:57 +
Yogesh Narayan Gaur wrote:
> Add support for octal mode IO data transfer.
> Micron flash, mt35xu512aba, supports octal mode data transfer and
> NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
>
> Patch series
> * Add s
On Mon, 22 Oct 2018 11:46:55 +
Yogesh Narayan Gaur wrote:
> Hi,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, October 22, 2018 5:13 PM
> > To: Yogesh Narayan Gaur
> > Cc: cristian
On Mon, 22 Oct 2018 11:43:40 +
Yogesh Narayan Gaur wrote:
> + Mark Brown
>
> Complete patch series[1]
> [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70210
Please resend the patch series with a "PATCH RESEND v4" prefix and
explain why you resend it in the cover letter.
>
On Mon, 22 Oct 2018 11:03:09 +
Yogesh Narayan Gaur wrote:
> Hi,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, October 22, 2018 4:23 PM
> > To: Yogesh Narayan Gaur ;
> > cristian.bir...
On Mon, 22 Oct 2018 12:46:27 +0200
Boris Brezillon wrote:
> On Mon, 22 Oct 2018 10:39:48 +
> Yogesh Narayan Gaur wrote:
>
> >
> > [1.632190] Start [addr_width:, read_dumy:08,
> > read_opcode:]
On Mon, 22 Oct 2018 10:39:48 +
Yogesh Narayan Gaur wrote:
>
> [1.632190] Start [addr_width:, read_dumy:08,
> read_opcode:]
> [1.639148] spi_nor_get_map_in_use:2882 smpt[0]=08ff65fc
>
On Mon, 22 Oct 2018 10:03:55 +
Yogesh Narayan Gaur wrote:
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2863,26 +2863,36 @@ static u8 spi_nor_smpt_read_dummy(const struct
> spi_nor *nor, const u32 settings)
> * @nor: pointer to a 'struct spi_nor'
>
On Mon, 22 Oct 2018 10:17:58 +
Yogesh Narayan Gaur wrote:
> It works,
Not really.
> [1.628162] m25p80 spi0.0: found s25fl512s, expected m25p80
>
> [1.633854] Start [addr_width:, read_dumy:08,
> read_opcode:
On Mon, 22 Oct 2018 10:03:55 +
Yogesh Narayan Gaur wrote:
> [1.624684] m25p80 spi0.0: found s25fl512s, expected m25p80
> [1.630377] Start [addr_width:, read_dumy:08, read_opcode:]
> [1.637335] spi_nor_get_map_in_use:2882 smpt[0]=08ff65fc
> [1.642641] spi_nor_ge
On Mon, 22 Oct 2018 10:03:55 +
Yogesh Narayan Gaur wrote:
> Hi,
>
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, October 22, 2018 2:46 PM
> > To: Yogesh Narayan Gaur
> > Cc: Tudor A
On Mon, 22 Oct 2018 06:04:13 +
Yogesh Narayan Gaur wrote:
> - /* Find the matching configuration map */
> - while (SMPT_MAP_ID(smpt[i]) != map_id) {
> - if (smpt[i] & SMPT_DESC_END)
> - goto out;
> + if (map_id_is_valid)
> +
On Mon, 22 Oct 2018 08:32:21 +
Yogesh Narayan Gaur wrote:
> HI,
>
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, October 22, 2018 1:32 PM
> > To: Yogesh Narayan Gaur
> > Cc: Cyrille
On Mon, 22 Oct 2018 06:04:13 +
Yogesh Narayan Gaur wrote:
> -static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32
> *smpt)
> +static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32
> *smpt, u32 smpt_len)
> {
> const u32 *ret = NULL;
> - u32
On Mon, 22 Oct 2018 06:04:13 +
Yogesh Narayan Gaur wrote:
> Hi Boris, Tudor,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Wednesday, October 17, 2018 3:23 PM
> > To: Yogesh Narayan Gaur
> >
On Fri, 19 Oct 2018 16:29:40 +0800
Liang Yang wrote:
> On 2018/10/19 4:50, Boris Brezillon wrote:
> > On Thu, 18 Oct 2018 13:09:05 +0800
> > Jianxin Pan wrote:
> >
> >> +static int meson_nfc_buffer_init(struct mtd_info *mtd)
> >> +{
> >
On Fri, 19 Oct 2018 15:29:05 +0800
Liang Yang wrote:
> > How about defining that the HW returns an array of __le64 instead and then
> > define the following macros which you can use after converting in the
> > CPU endianness
> >
> > #define ECC_GET_PROTECTED_OOB_BYTE(x, y)(((x) >> (8 * (1 +
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
> +static int meson_nfc_buffer_init(struct mtd_info *mtd)
> +{
> + struct nand_chip *nand = mtd_to_nand(mtd);
> + struct meson_nfc *nfc = nand_get_controller_data(nand);
> + static int max_page_bytes, max_info_bytes;
> + int pa
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
> +static int meson_nfc_calc_set_timing(struct meson_nfc *nfc,
> + const struct nand_sdr_timings *timings)
> +{
> + struct nand_timing *timing = &nfc->timing;
> + int div, bt_min, bt_max, bus_timing;
>
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
> +static int meson_nand_bch_mode(struct nand_chip *nand)
> +{
> + struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
> + struct meson_nand_ecc meson_ecc[] = {
> + MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8),
> +
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
> From: Liang Yang
>
> Add initial support for the Amlogic NAND flash controller which found
> in the Meson-GXBB/GXL/AXG SoCs.
>
> Signed-off-by: Liang Yang
> Signed-off-by: Yixun Lan
> Signed-off-by: Jianxin Pan
> ---
> drivers/mtd/nan
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
> +static int meson_nfc_exec_op(struct nand_chip *chip,
> + const struct nand_operation *op, bool check_only)
> +{
> + struct mtd_info *mtd = nand_to_mtd(chip);
> + struct meson_nfc *nfc = nand_get_controller_d
On Wed, 17 Oct 2018 07:46:30 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Wednesday, October 17, 2018 1:00 PM
> > To: Yogesh Narayan Gaur
> >
On Wed, 17 Oct 2018 08:20:19 +
Yogesh Narayan Gaur wrote:
> Hi Tudor,
>
> > -Original Message-
> > From: Tudor Ambarus [mailto:tudor.amba...@microchip.com]
> > Sent: Wednesday, October 17, 2018 1:31 PM
> > To: Yogesh Narayan Gaur ; Boris Brezillo
On Wed, 17 Oct 2018 09:10:45 +0200
Boris Brezillon wrote:
> On Wed, 17 Oct 2018 09:07:24 +0200
> Boris Brezillon wrote:
>
> > On Wed, 17 Oct 2018 02:07:43 +
> > Yogesh Narayan Gaur wrote:
> >
> > > >
> > > Actually there is
On Wed, 17 Oct 2018 09:10:45 +0200
Boris Brezillon wrote:
> On Wed, 17 Oct 2018 09:07:24 +0200
> Boris Brezillon wrote:
>
> > On Wed, 17 Oct 2018 02:07:43 +
> > Yogesh Narayan Gaur wrote:
> >
> > > >
> > > Actually there is
On Wed, 17 Oct 2018 09:07:24 +0200
Boris Brezillon wrote:
> On Wed, 17 Oct 2018 02:07:43 +
> Yogesh Narayan Gaur wrote:
>
> > >
> > Actually there is no entry of s25fs512s in current spi-nor.c file.
> > For my connected flash part, jedec ID read points
On Wed, 17 Oct 2018 02:07:43 +
Yogesh Narayan Gaur wrote:
> >
> Actually there is no entry of s25fs512s in current spi-nor.c file.
> For my connected flash part, jedec ID read points to s25fl512s. I
> have asked my board team to confirm the name of exact connected flash
> part. When I chec
On Wed, 17 Oct 2018 10:08:11 +0800
masonccy...@mxic.com.tw wrote:
> From: Mason Yang
>
> Add a driver for Macronix SPI controller IP.
>
> Signed-off-by: Mason Yang
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/Kconfig| 6 +
> drivers/spi/Makefile |
reg-names: should contain "regs" and "dirmap"
> +- interrupts: interrupt line connected to the SPI controller
> +- clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk"
The _clk suffix is unnecessary in my opinion. How about:
- c
On Tue, 16 Oct 2018 14:04:11 +0200
Boris Brezillon wrote:
> On Tue, 16 Oct 2018 09:51:47 +
> Yogesh Narayan Gaur wrote:
>
> > Hi Tudor,
> >
> > This patch is breaking the 1-4-4 Read protocol for the spansion flash
> > "s25fl512s".
> >
>
On Tue, 16 Oct 2018 09:51:47 +
Yogesh Narayan Gaur wrote:
> Hi Tudor,
>
> This patch is breaking the 1-4-4 Read protocol for the spansion flash
> "s25fl512s".
>
> Without this patch read request command for Quad mode, 4-byte enable, is
> coming as 0xEC i.e. SPINOR_OP_READ_1_4_4_4B.
> But
time macros.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
> ---
>
> drivers/mtd/nand/raw/denali.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h
> index 57a549
On Tue, 16 Oct 2018 18:26:34 +0800
Hou Tao wrote:
> On 2018/10/16 14:41, Richard Weinberger wrote:
> > On Tue, Oct 16, 2018 at 7:53 AM Hou Tao wrote:
> >>
> >> ping ?
> >>
> >> On 2018/10/6 17:09, Hou Tao wrote:
> >>> When an invalid mount option is passed to jffs2, jffs2_parse_options()
> >
Hi Yogesh,
On Mon, 15 Oct 2018 11:47:55 +
Yogesh Narayan Gaur wrote:
> Add support for octal mode IO data transfer.
> Micron flash, mt35xu512aba, supports octal mode data transfer and
> NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
>
> Patch series
> * Add support
Hi Mason,
On Mon, 15 Oct 2018 16:26:15 +0800
masonccy...@mxic.com.tw wrote:
> +
> +static int mxic_spi_setup(struct spi_device *spi)
> +{
> + return 0;
> +}
Drop this empty function and leave ->setup to NULL.
> +
> +static int mxic_spi_probe(struct platform_device *pdev)
> +{
> + struc
culations based on
^ with
> priv->io_base.
Can we do that in 2 steps?
1/ Stop using .IO_ADDR_R/W
2/ Convert the driver to ->exec_op()
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Janusz Krzysztofik
> ---
[...]
> -static int ams_delta_nand_r
Hi Janusz,
On Fri, 12 Oct 2018 22:41:00 +0200
Janusz Krzysztofik wrote:
> Each controller driver with access to NAND R/B pin over GPIO would have
> to reimplement the polling loop otherwise.
>
> Signed-off-by: Janusz Krzysztofik
> ---
> Changelog:
> v2:
> New patch - v1 consisted of only one
On Tue, 28 Aug 2018 22:32:57 +0800
Liu Xiang wrote:
> If the size of spi-nor flash is larger than 16MB, the read_opcode
> is set to SPINOR_OP_READ_1_1_4_4B, and fsl_qspi_get_seqid() will
> return -EINVAL when cmd is SPINOR_OP_READ_1_1_4_4B. This can
> cause read operation fail.
>
> Fixes: e46ecd
On Fri, 12 Oct 2018 11:19:52 +0200
Arnd Bergmann wrote:
> On Fri, Oct 12, 2018 at 11:16 AM Boris Brezillon
> wrote:
> >
> > Hi Arnd,
> >
> > On Wed, 10 Oct 2018 20:44:50 +0200
> > Arnd Bergmann wrote:
> >
> > > Enabling -Wvla found another
Hi Arnd,
On Wed, 10 Oct 2018 20:44:50 +0200
Arnd Bergmann wrote:
> Enabling -Wvla found another variable-length array with randconfig
> testing:
>
> drivers/mtd/maps/sa1100-flash.c: In function 'sa1100_setup_mtd':
> drivers/mtd/maps/sa1100-flash.c:224:10: error: ISO C90 forbids variable
> leng
Hi Vignesh,
On Mon, 8 Oct 2018 21:06:02 +0530
Vignesh R wrote:
> Hi Boris,
>
> Sorry I missed this mail.
>
> On Thursday 04 October 2018 04:47 PM, Boris Brezillon wrote:
> > On Thu, 4 Oct 2018 16:05:36 +0530
> > Vignesh R wrote:
> >
> >>>
Arnd Bergmann (1):
lib/bch: fix possible stack overrun
lib/Makefile | 1 -
lib/bch.c| 17 +
2 files changed, 13 insertions(+), 5 deletions(-)
--
Boris Brezillon, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Fri, 12 Oct 2018 02:23:08 +
Yogesh Narayan Gaur wrote:
> Some MICRON related macros in spi-nor domain were ST.
> Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
>
> Added entry of MFR Id for Micron flashes, 0x002C.
>
> Signed-off-by: Yogesh Gaur
> Reviewed-by: Tudo
On Fri, 28 Sep 2018 16:21:25 -0700
Eric Anholt wrote:
> Since this is UAPI, it's good to document what exactly the guarantees
> we're providing are.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Boris Brezillon
> ---
> include/uapi/drm/v3d_drm.h | 10
ock, not that the driver was slow.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Boris Brezillon
> ---
> drivers/gpu/drm/v3d/v3d_debugfs.c | 35 +++
> drivers/gpu/drm/v3d/v3d_regs.h| 30 ++
> 2 files changed, 65 insertions(+
On Tue, 9 Oct 2018 09:52:23 +
Chuanhua Han wrote:
> 1. In the dspi driver (spi controller), bits_per_word
> (dspi->bits_per_word = transfer->bits_per_word) passed from the upper
> layer (spi-mem.c) is used. In this way, I can only assign the
> appropriate value of transfer->bits_per_word befo
On Mon, 8 Oct 2018 16:41:39 +0530
Yogesh Gaur wrote:
> +/* Registers used by the driver */
> +#define FSPI_MCR00x00
> +#define FSPI_MCR0_AHB_TIMEOUT_MASK GENMASK(31, 24)
> +#define FSPI_MCR0_IP_TIMEOUT_MASKGENMASK(23, 16)
You never mask the IP_TIMEOUT val, so you don't
On Mon, 8 Oct 2018 11:21:13 +
Yogesh Narayan Gaur wrote:
> > > +static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct
> > > +spi_mem_op *op) {
> > > + u32 len = op->data.nbytes;
> > > +
> > > + /* Read out the data directly from the AHB buffer. */
> > > + memcpy_fromio(op->data.buf.i
On Mon, 8 Oct 2018 09:40:09 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 9:32 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 20:12:43 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > >
> > > I think
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