On Thu, 5 Jul 2018 13:14:58 +0200
Frieder Schrempf wrote:
> By calling spi_mem_get_name(), the driver of the (Q)SPI controller can
> set a custom name for the memory device if necessary.
> This is useful to keep mtdparts compatible when controller drivers are
> ported from the MTD to the SPI lay
On Sat, 30 Jun 2018 16:24:21 +0530
Vignesh R wrote:
> Sometimes when writing large size files to flash in direct/memory mapped
> mode, it is seen that flash write enable command times out with error:
> [ 503.146293] cadence-qspi 4704.ospi: Flash command execution timed out.
>
> This is beca
On Fri, 06 Jul 2018 16:44:44 +0200
Richard Weinberger wrote:
> Am Freitag, 6. Juli 2018, 15:05:25 CEST schrieb Benjamin Gaignard:
> > The format specifier "%p" can leak kernel addresses.
> > Use "%pK" instead.
>
> Does %pK really make sense for dev_dbg()?
> When the driver is being debugged "l
On Mon, 25 Jun 2018 10:44:47 +1200
Chris Packham wrote:
> Micron MT29F1G08ABAFAWP-ITE:F supports an on-die ECC with 8 bits
> per 512 bytes. Add support for this combination.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Boris Brezillon
> ---
> Changes in v2:
&g
On Mon, 25 Jun 2018 10:44:42 +1200
Chris Packham wrote:
> Hi,
>
> I'm looking at adding support for the Micron MT29F1G08ABAFAWP-ITE:F chip
Hm, it's even worse than I thought. The model name does not include the
-ITE suffix (E means ECC can't be disabled), which means we have no way
to detect th
On Fri, 6 Jul 2018 21:27:20 +0200
Boris Brezillon wrote:
> On Mon, 25 Jun 2018 10:44:42 +1200
> Chris Packham wrote:
>
> > Hi,
> >
> > I'm looking at adding support for the Micron MT29F1G08ABAFAWP-ITE:F chip
>
> Hm, it's even worse than I thought.
On Tue, 12 Jun 2018 06:42:42 +
Yogesh Narayan Gaur wrote:
> I have tried JFFS2 mounting with smaller partition size but still getting
> failure.
> For partition size equal or less than 1MB, getting errors as
> [ 25.044930] jffs2: Too few erase blocks (4)
> Thus, need to have size more
Hi Neil,
On Tue, 12 Jun 2018 08:05:13 +1000
NeilBrown wrote:
> On Mon, Jun 11 2018, Boris Brezillon wrote:
> >
> > Also, I'd prefer to have this patch split in 2:
> > 1/ one patch removing the check in spi_nor_write()
> > 2/ and the second patch removing
On Tue, 12 Jun 2018 10:02:12 +0200
Stefan Agner wrote:
> >> +static int tegra_nand_read_page_hwecc(struct mtd_info *mtd,
> >> +struct nand_chip *chip,
> >> +uint8_t *buf, int oob_required, int page)
> >> +{
> >> + struct tegra_nand_
On Tue, 12 Jun 2018 10:06:42 +0200
Stefan Agner wrote:
> On 12.06.2018 02:03, Dmitry Osipenko wrote:
> > On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> >> Add support for the NAND flash controller found on NVIDIA
> >> Tegra 2 SoCs. This implementation does not make use of the
> >> c
On Tue, 12 Jun 2018 11:17:09 +0200
Stefan Agner wrote:
> [also added Jens Axboe]
>
> On 12.06.2018 10:27, Boris Brezillon wrote:
> > On Tue, 12 Jun 2018 10:06:42 +0200
> > Stefan Agner wrote:
> >
> >> On 12.06.2018 02:03, Dmitry Osipenko wrote:
> &g
On Tue, 12 Jun 2018 19:36:06 +0900
Masahiro Yamada wrote:
> Maybe, the commit title should be:
>
> mtd: rawnand: denali: add more clocks and improve setup_data_interface
Or you split that in 2 commits, one retrieving the new clks, and the
other one fixing/improving ->setup_data_interface().
>
On Tue, 12 Jun 2018 22:20:58 +0200
Stefan Agner wrote:
> On 12.06.2018 17:24, Jens Axboe wrote:
> > On 6/12/18 3:17 AM, Stefan Agner wrote:
> >> [also added Jens Axboe]
> >>
> >> On 12.06.2018 10:27, Boris Brezillon wrote:
> >>> On Tue, 12 J
On Tue, 12 Jun 2018 15:24:41 -0600
Jens Axboe wrote:
> On 6/12/18 2:20 PM, Stefan Agner wrote:
> > On 12.06.2018 17:24, Jens Axboe wrote:
> >> On 6/12/18 3:17 AM, Stefan Agner wrote:
> >>> [also added Jens Axboe]
> >>>
> >>> On 12.06.2018
On Wed, 13 Jun 2018 08:24:26 +1000
NeilBrown wrote:
> On Tue, Jun 12 2018, Boris Brezillon wrote:
>
> >
> > Just because you managed to solve the problem in one driver does not
> > mean the problem does not exist for others. I read this datasheet [1]
> > several ti
On Thu, 14 Jun 2018 16:29:59 +0900
Masahiro Yamada wrote:
> Hi Richard,
>
> 2018-06-14 16:25 GMT+09:00 Richard Weinberger :
> > Masahiro,
> >
> > Am Donnerstag, 14. Juni 2018, 07:11:04 CEST schrieb Masahiro Yamada:
> >>
> >> The ->setup_data_interface() hook needs to know the clock frequency.
On Thu, 14 Jun 2018 10:02:12 +0200
Richard Weinberger wrote:
> Am Donnerstag, 14. Juni 2018, 09:38:35 CEST schrieb Boris Brezillon:
> > On Thu, 14 Jun 2018 16:29:59 +0900
> > Masahiro Yamada wrote:
> >
> > > Hi Richard,
> > >
> > &g
On Thu, 14 Jun 2018 09:29:42 +0200
Richard Weinberger wrote:
> Quentin,
>
> Am Montag, 11. Juni 2018, 12:20:37 CEST schrieb Quentin Schulz:
> > If we go for a per-image flag, adding nocheck to the ioctl makes sense,
> > otherwise we have to find a way to select only one or more volumes for
> > w
On Thu, 14 Jun 2018 20:31:59 +0900
Masahiro Yamada wrote:
> Hi Boris,
>
> 2018-06-14 16:38 GMT+09:00 Boris Brezillon :
> > On Thu, 14 Jun 2018 16:29:59 +0900
> > Masahiro Yamada wrote:
> >
> >> Hi Richard,
> >>
> >> 2018-06-14
On Tue, 12 Jun 2018 08:51:25 +
Yogesh Narayan Gaur wrote:
>
> I am working on lsxxx platform. With further debugging, I found that my erase
> operation for second flash device is not working properly.
> Need to have debugging for this in Frieder Patch.
Did you find the problem? Could it be
On Fri, 15 Jun 2018 13:42:12 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> I am still debugging the issue.
> With some analysis, able to check that proper values are not being written
> for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register.
>
> In current code, value of map_addr are b
On Fri, 15 Jun 2018 15:55:41 +0200
Boris Brezillon wrote:
> On Fri, 15 Jun 2018 13:42:12 +
> Yogesh Narayan Gaur wrote:
>
> > Hi Boris,
> >
> > I am still debugging the issue.
> > With some analysis, able to check that proper values are not bein
On Thu, 17 May 2018 15:35:04 +0800
Xiangsheng Hou wrote:
> On Thu, 2018-05-17 at 09:13 +0200, Boris Brezillon wrote:
> > On Thu, 17 May 2018 14:58:24 +0800
> > Xiangsheng Hou wrote:
> >
> > > Hi Boris,
> > >
> > > On Wed, 2018-05-16 at 14:4
On Fri, 18 May 2018 13:50:00 +0800
Xiangsheng Hou wrote:
> Hi Boris,
>
> On Thu, 2018-05-17 at 09:42 +0200, Boris Brezillon wrote:
> > On Thu, 17 May 2018 15:35:04 +0800
> > Xiangsheng Hou wrote:
> >
> > > On Thu, 2018-05-17 at 09:13 +0200, Boris Brezi
Hi Andy,
Sorry for the late reply.
On Thu, 8 Feb 2018 20:18:47 +0800
Andy Yan wrote:
> From: Shawn Lin
Commit message please.
>
> Add Rockchip SFC(serial flash controller) driver.
>
> Signed-off-by: Shawn Lin
> Signed-off-by: Andy Yan
> Acked-by: Marek Vasut
>
> ---
>
> Changes in v8
esterberg
Queued to spi-nor/next.
Thanks,
Boris
>
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Boris Brezillon, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
> control behavior. Convert all drivers requesting exclusive resets to the
> explicit API call so the temporary transition helpers can be removed.
>
> No functional changes.
>
> Cc: Cyrille Pitchen
> Cc: Marek Vasut
> Cc: David Woodhouse
> Cc: Brian Norris
> Cc
Hi Chuanhua,
On Wed, 15 Aug 2018 14:33:43 +0800
Chuanhua Han wrote:
> Consider a message size limit when calculating the maximum amount
> of data that can be read.
>
> Signed-off-by: Chuanhua Han
> ---
> drivers/mtd/devices/m25p80.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-
On Tue, 14 Aug 2018 00:34:46 +0200
Janusz Krzysztofik wrote:
> In its current shape, the driver sets data port direction before each
> byte read/write operation, even during multi-byte transfers. Improve
> performance of the driver by setting the port direction only when
> needed.
>
> This opti
On Tue, 14 Aug 2018 00:34:48 +0200
Janusz Krzysztofik wrote:
> Don't readw()/writew() data directly from/to GPIO port which is under
> control of gpio-omap driver, use GPIO API instead.
>
> Degrade of performance on Amstrad Delta is significant, can be
> recognized as a regression, that's why I'
Hi Yixun,
I know I said I would finish reviewing the driver, but I didn't have
time to do it, so feel free to send a new version addressing the
comments I already made.
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
> +static void meson_nfc_select_chip(struct mtd_info *mtd, int chip)
> +{
On Fri, 17 Aug 2018 10:47:34 +0200
Arnd Bergmann wrote:
> On Fri, Aug 17, 2018 at 1:27 AM Luck, Tony wrote:
> >
> > On Thu, Aug 16, 2018 at 11:10:33PM +0200, Arnd Bergmann wrote:
> > > Another way would be to add
> > >
> > > #include
> > > +#undef PCI_IOBASE
> > >
> > > in your asm/io.h. Thi
On Fri, 17 Aug 2018 18:07:05 +0800
Chuanhua Han wrote:
> The length of the transmitted data needs to be adjusted due to the maximum
> length limit for espi transmission messages
>
> Signed-off-by: Chuanhua Han
> ---
> drivers/spi/spi-fsl-espi.c | 25 +
> 1 file changed
On Fri, 17 Aug 2018 21:03:59 +0800
Liang Yang wrote:
> Hi Boris,
> On 2018/8/2 5:50, Boris Brezillon wrote:
>
> > Hi Yixun,
> >
> > On Thu, 19 Jul 2018 17:46:12 +0800
> > Yixun Lan wrote:
> >
> > I haven't finished reviewing the driver ye
On Fri, 17 Aug 2018 15:56:23 +
"Luck, Tony" wrote:
> >> - Some targets don't have any support for I/O space on their PCI bus and
> >> just
> >>want to get things to compile by setting PCI_IOBASE to zero, this still
> >> opens
> >> up some of the same problems as above, but doesn't r
Hi Naga,
On Fri, 17 Aug 2018 18:49:24 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_exec_op_cmd(struct nand_chip *chip,
> +const struct nand_subop *subop)
> +{
> + const struct nand_op_instr *instr;
> + struct anfc_op nfc_op = {};
> + struct a
On Sat, 18 Aug 2018 05:49:32 +
Naga Sureshkumar Relli wrote:
> Hi Boris,
>
> Thanks for the review.
>
> > -Original Message-----
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Friday, August 17, 2018 11:29 PM
> > To: Naga S
Hi Chuanhua,
On Mon, 20 Aug 2018 17:43:26 +0800
Chuanhua Han wrote:
Subject prefix should be "spi: spi-mem: " not "mtd: m25p80: ", and you
need a commit message explaining what this patch does and why it's
needed.
> Signed-off-by: Chuanhua Han
Fixes: c36ff266dc82 ("spi: Extend the core to eas
On Mon, 20 Aug 2018 10:49:38 +
Naga Sureshkumar Relli wrote:
>
> Thanks for your suggestion and are you saying something like Marvell parser
> patterns for nfcv1 as below?
>
> static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER(
> /* Naked commands not support
On Mon, 20 Aug 2018 12:21:12 +
Naga Sureshkumar Relli wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, August 20, 2018 5:40 PM
> > To: Naga Sureshkumar Relli
> > Cc: r
On Fri, 17 Aug 2018 18:49:23 +0530
Naga Sureshkumar Relli wrote:
> This patch adds the dts binding document for arasan nand flash
> controller.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
> Changes in v10:
> - None
> Changes in v9:
> - None
> Changes in v8:
> - Updated compatible and clock-
On Mon, 20 Aug 2018 13:01:13 +
David Laight wrote:
> From: Chuanhua Han
> > Sent: 20 August 2018 13:44
> >
Still no message here, and the subject prefix is still wrong.
Fixes and Cc-stable tags should be placed here...
> > Signed-off-by: Chuanhua Han
> > ---
> > Changes in v3:
> > R
Hi Naga,
On Fri, 17 Aug 2018 18:49:24 +0530
Naga Sureshkumar Relli wrote:
>
> +config MTD_NAND_ARASAN
> + tristate "Support for Arasan Nand Flash controller"
> + depends on HAS_IOMEM
> + depends on HAS_DMA
Just nitpicking, but you can place them on the same line:
depends
s: fix I2C transfers in Cadence I3C master driver (2018-12-12
17:08:32 +0100)
Add initial support for I3C along with 2 I3C master controller drivers.
--------
Boris Brezillon (7):
mtd: spi-nor: Add support for mx25u12835f
Boris Brezillon (61):
mtd: maps: physmap: Add SPDX header
mtd: maps: physmap: Rename ->map and ->mtd into ->maps and ->mtds
mtd: maps: physmap: Use platform_get_resource() to retrieve iomem
resources
mtd: maps:
On Mon, 2018-12-03 at 10:23:15 UTC, Boris Brezillon wrote:
> Use my korg address instead of the bootlin one.
>
> Signed-off-by: Boris Brezillon
Applied to http://git.infradead.org/linux-mtd.git mtd/next.
Boris
Hi Yogesh,
On Mon, 10 Dec 2018 04:13:28 +
Yogesh Narayan Gaur wrote:
> Hi Mark,
>
> Patch has been resend [1], this patch is depends on the series of patch[2]
> and this series has been applied by Boris already.
You're still not asking the right person. Every patches touching
things in dr
On Wed, 3 Oct 2018 22:26:03 +0530
Vignesh R wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Octal DDR mode. Therefore, extend current dr
On Sun, 9 Dec 2018 14:17:18 +0530
Vignesh R wrote:
> Hi Boris,
>
> On 03/10/18 10:26 PM, Vignesh R wrote:
> > This series adds support for octal mode of mt35x flash. Also, adds
> > support for OSPI version of Cadence QSPI controller.
> >
> > Based on top of patches adding basic support for mt35
On Mon, 10 Dec 2018 08:39:20 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> Sorry for confusion.
>
> My intention was just to point to the correct patch number only. Earlier you
> have asked Mark to pick the patch [1] but that patch number was not correct.
Look at the context in [1] (we hav
On Mon, 10 Dec 2018 09:41:51 +
Yogesh Narayan Gaur wrote:
> > > +/* Instead of busy looping invoke readl_poll_timeout functionality.
> > > +*/ static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem
> > > *base,
> > > + u32 mask, u32 delay_us,
> > > +
On Mon, 10 Dec 2018 10:31:57 +
Schrempf Frieder wrote:
> >> Yes, I need to validate op->addr.nbytes else LUT would going to be
> >> programmed for 0 addrlen.
> >> I have checked this on the target.
> >
> > Also agree there. Some operations have 0 address bytes. We could also
> > test addr
On Mon, 10 Dec 2018 10:35:35 +
Schrempf Frieder wrote:
> >>> +
> >>> +static int nxp_fspi_exec_op(struct spi_mem *mem, const struct
> >>> +spi_mem_op *op) {
> >>> + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
> >>> + int err = 0;
> >>> +
> >>> + mutex_lock(&f->lock);
>
On Mon, 10 Dec 2018 10:43:56 +
Yogesh Narayan Gaur wrote:
> > > Thus, in LUT preparation we have assigned only the base address.
> > > Now if I have assigned ahb_buf_size to FSPI_FLSHXXCR0 register then for
> > read/write data beyond limit of ahb_buf_size offset I get data corruption.
> >
On Mon, 3 Dec 2018 08:39:18 +
Yogesh Narayan Gaur wrote:
> - Add opcodes for octal I/O commands
> * Read : 1-1-8 and 1-8-8 protocol
> * Write : 1-1-8 and 1-8-8 protocol
> * opcodes for 4-byte address mode command
>
> - Entry of macros in _convert_3to4_xxx function
>
> - Add flag spec
On Mon, 10 Dec 2018 10:59:54 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, December 10, 2018 4:20 PM
> > To: Yogesh Narayan Gaur
> >
On Mon, 10 Dec 2018 10:59:54 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, December 10, 2018 4:20 PM
> > To: Yogesh Narayan Gaur
> >
On Mon, 10 Dec 2018 11:17:20 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, December 10, 2018 4:27 PM
> > To: Yogesh Narayan Gaur
> > Cc:
On Mon, 10 Dec 2018 16:49:29 +0530
Vignesh R wrote:
> On 10/12/18 2:15 PM, Boris Brezillon wrote:
> > On Wed, 3 Oct 2018 22:26:03 +0530
> > Vignesh R wrote:
> >
> >> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> >> It also has an int
On Mon, 10 Dec 2018 19:23:46 +0800
Liang Yang wrote:
> >> + mtd->ecc_stats.failed++;
> >> + continue;
> >> + }
> >> + mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
> >> + bitflips = max_t(u32, bitflips, ECC_ERR_CNT(*info));
> >> + }
On Mon, 10 Dec 2018 11:25:55 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, December 10, 2018 4:39 PM
> > To: Yogesh Narayan Gaur
> >
river for Atmel QSPI
> controller")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Arnd Bergmann
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/sp
On Tue, 11 Dec 2018 09:56:25 +0800
Liang Yang wrote:
> Hi Miquel,
>
> On 2018/12/10 22:50, Miquel Raynal wrote:
> > Hi Liang,
> >
> > Liang Yang wrote on Mon, 10 Dec 2018 20:12:39
> > +0800:
> >
> >> On 2018/12/10 19:38, Boris Brezillon w
On Fri, 7 Dec 2018 14:47:57 +0100
Paul Kocialkowski wrote:
> diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
> index f3fd34faa812..e80b1ad5c938 100644
> --- a/drivers/gpu/drm/vc4/vc4_kms.c
> +++ b/drivers/gpu/drm/vc4/vc4_kms.c
> @@ -479,6 +479,7 @@ static const struct
On Mon, 10 Dec 2018 17:15:29 +
wrote:
> From: Cyrille Pitchen
>
> This patch configures the QSPI0 controller pin muxing and declares
> a jedec,spi-nor memory.
>
> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> memory which advertises a maximum frequency of 80MHz for Qu
On Thu, 20 Dec 2018 08:23:07 +
Yogesh Narayan Gaur wrote:
> Octal mode support patch series has dependency over these patches.
> Should I send these two patches again or specifies them as dependency patches
> in the cover letter.
No, you should either base your work on the master branch of
act8945a-regulator: Implement PM
> functionalities")
> Signed-off-by: Wei Yongjun
Reviewed-by: Boris Brezillon
> ---
> drivers/regulator/act8945a-regulator.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/regulator/act8945a-regulator.c
On Fri, 14 Dec 2018 10:58:06 +0100
Christophe Kerello wrote:
> This patch adds the documentation of the device tree bindings for the STM32
> FMC2 NAND controller.
>
> Signed-off-by: Christophe Kerello
Reviewed-by: Boris Brezillon
> ---
> .../devicetree/bindings/mtd/s
2> (Extended ECC
>based on Hamming)
>
> This patch has been tested on Micron MT29F8G08ABACAH4 and
> MT29F8G16ABACAH4
>
> Signed-off-by: Christophe Kerello
Reviewed-by: Boris Brezillon
On Fri, 14 Dec 2018 10:58:08 +0100
Christophe Kerello wrote:
> This patch adds the polling mode, a basic mode that do not need
> any DMA channels. This mode is also useful for debug purpose.
>
> Signed-off-by: Christophe Kerello
Reviewed-by: Boris Brezillon
On Mon, 17 Dec 2018 15:49:07 +
Schrempf Frieder wrote:
> From: Frieder Schrempf
>
> Currently supported bad block marker positions within the block are:
> * in first page only
> * in last page only
> * in first or second page
>
> Some ESMT NANDs are known to have been shipped by the manufa
On Thu, 20 Dec 2018 14:59:54 +0100
Boris Brezillon wrote:
> >
> > /**
> > + * nand_bbm_page_offset - Get the page offsets for bad block markers
> > + * @chip: NAND chip object
> > + * @index: Index for the page offset
>
> Hm, the meaning of index is far
Hi Frieder,
On Thu, 20 Dec 2018 14:35:05 +
Schrempf Frieder wrote:
> On 20.12.18 14:59, Boris Brezillon wrote:
> > On Mon, 17 Dec 2018 15:49:07 +
> > Schrempf Frieder wrote:
> >
> >> From: Frieder Schrempf
> >>
> >> Currently suppo
Hi Gustavo,
On Fri, 4 Jan 2019 11:26:37 -0600
"Gustavo A. R. Silva" wrote:
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elements for that array. For example:
>
>
Hello Linus,
On Wed, 2 Jan 2019 11:53:34 -0800
Linus Torvalds wrote:
> Hmm..
>
> Adding a few more mtd people to the cc.
Sorry for the late reply, I don't have access to my @bootlin.com
address anymore and it took me some time to realize you had replied to
this bug report.
>
> On Tue, Jan 1,
hrempf
> Acked-by: Han Xu
> Reviewed-by: Yogesh Gaur
> Tested-by: Yogesh Gaur
> Tested-by: Han Xu
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/spi-nor/Kconfig | 9 -
> drivers/mtd/spi-nor/Makefile | 1 -
> drivers/spi/Kconfig | 11 +
>
driver.
>
> The new driver is already in use and this code is not compiled anymore,
> so let's remove it.
>
> Signed-off-by: Frieder Schrempf
> Acked-by: Han Xu
> Tested-by: Han Xu
Acked-by: Boris Brezillon
On Mon, 8 Oct 2018 16:41:39 +0530
Yogesh Gaur wrote:
> +/* Registers used by the driver */
> +#define FSPI_MCR00x00
> +#define FSPI_MCR0_AHB_TIMEOUT_MASK GENMASK(31, 24)
> +#define FSPI_MCR0_IP_TIMEOUT_MASKGENMASK(23, 16)
You never mask the IP_TIMEOUT val, so you don't
On Tue, 9 Oct 2018 09:52:23 +
Chuanhua Han wrote:
> 1. In the dspi driver (spi controller), bits_per_word
> (dspi->bits_per_word = transfer->bits_per_word) passed from the upper
> layer (spi-mem.c) is used. In this way, I can only assign the
> appropriate value of transfer->bits_per_word befo
ock, not that the driver was slow.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Boris Brezillon
> ---
> drivers/gpu/drm/v3d/v3d_debugfs.c | 35 +++
> drivers/gpu/drm/v3d/v3d_regs.h| 30 ++
> 2 files changed, 65 insertions(+
On Fri, 28 Sep 2018 16:21:25 -0700
Eric Anholt wrote:
> Since this is UAPI, it's good to document what exactly the guarantees
> we're providing are.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Boris Brezillon
> ---
> include/uapi/drm/v3d_drm.h | 10
Hi Kees,
On Sun, 28 Oct 2018 19:13:26 -0700
Kees Cook wrote:
> On Fri, Oct 12, 2018 at 2:22 AM, Boris Brezillon
> wrote:
> > On Fri, 12 Oct 2018 11:19:52 +0200
> > Arnd Bergmann wrote:
> >
> >> On Fri, Oct 12, 2018 at 11:16 AM Boris Brezillon
>
On Mon, 29 Oct 2018 23:15:42 +
"Grandbois, Brett" wrote:
> On 28/10/18 1:39 am, Boris Brezillon wrote:
> > Hi Brett,
> >
> > On Tue, 16 Oct 2018 00:57:41 +
> > "Grandbois, Brett" wrote:
> >
> >> Add support to expose th
On Wed, 31 Oct 2018 03:18:28 +
"Grandbois, Brett" wrote:
> On 30/10/18 6:26 pm, Boris Brezillon wrote:
> > On Mon, 29 Oct 2018 23:15:42 +
> > "Grandbois, Brett" wrote:
> >
> >> On 28/10/18 1:39 am, Boris Brezillon wrote:
> >>
Hi Piotr, Tudor,
On Wed, 27 Jun 2018 15:16:03 +0200
Piotr Bugalski wrote:
> Hello,
>
> Atmel SAMA5D2 is equipped with two QSPI interfaces. These interfaces can
> work as in SPI-compatible mode or use two / four lines to improve
> communication speed. At the moment there is QSPI driver strongly
Hi Huijin,
Subject prefix should be "mtd: spi-nor: ...", and please replace
"unexpected error" by "unsigned int overflows".
On Thu, 23 Aug 2018 03:28:02 -0400
Huijin Park wrote:
> From: "huijin.park"
>
> the params->size is defined as "u64"
> and, "info->sector_size" and "info->n_sectors" is
Hi Huijin,
On Thu, 23 Aug 2018 04:43:39 -0400
Huijin Park wrote:
> From: "huijin.park"
>
> assign of a signed value which has type 'int' to a variable of
> a bigger unsigned integer type 'uint64_t'.
Why are you mentioning u64? AFAICT, the len passed to erase_write() is
always an unsigned int.
1ccdc61d1:
dt-bindings: i3c: Document Cadence I3C master bindings (2018-11-01 06:12:05
+0100)
Add the I3C framework + an I3C controller driver for Cadence IP
--------
Boris Brez
On Tue, 16 Oct 2018 18:26:34 +0800
Hou Tao wrote:
> On 2018/10/16 14:41, Richard Weinberger wrote:
> > On Tue, Oct 16, 2018 at 7:53 AM Hou Tao wrote:
> >>
> >> ping ?
> >>
> >> On 2018/10/6 17:09, Hou Tao wrote:
> >>> When an invalid mount option is passed to jffs2, jffs2_parse_options()
> >
time macros.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
> ---
>
> drivers/mtd/nand/raw/denali.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/denali.h b/drivers/mtd/nand/raw/denali.h
> index 57a549
On Tue, 16 Oct 2018 09:51:47 +
Yogesh Narayan Gaur wrote:
> Hi Tudor,
>
> This patch is breaking the 1-4-4 Read protocol for the spansion flash
> "s25fl512s".
>
> Without this patch read request command for Quad mode, 4-byte enable, is
> coming as 0xEC i.e. SPINOR_OP_READ_1_4_4_4B.
> But
On Tue, 16 Oct 2018 14:04:11 +0200
Boris Brezillon wrote:
> On Tue, 16 Oct 2018 09:51:47 +
> Yogesh Narayan Gaur wrote:
>
> > Hi Tudor,
> >
> > This patch is breaking the 1-4-4 Read protocol for the spansion flash
> > "s25fl512s".
> >
>
On Wed, 17 Oct 2018 10:08:11 +0800
masonccy...@mxic.com.tw wrote:
> From: Mason Yang
>
> Add a driver for Macronix SPI controller IP.
>
> Signed-off-by: Mason Yang
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/Kconfig| 6 +
> drivers/spi/Makefile |
reg-names: should contain "regs" and "dirmap"
> +- interrupts: interrupt line connected to the SPI controller
> +- clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk"
The _clk suffix is unnecessary in my opinion. How about:
- c
On Wed, 17 Oct 2018 02:07:43 +
Yogesh Narayan Gaur wrote:
> >
> Actually there is no entry of s25fs512s in current spi-nor.c file.
> For my connected flash part, jedec ID read points to s25fl512s. I
> have asked my board team to confirm the name of exact connected flash
> part. When I chec
On Wed, 17 Oct 2018 09:07:24 +0200
Boris Brezillon wrote:
> On Wed, 17 Oct 2018 02:07:43 +
> Yogesh Narayan Gaur wrote:
>
> > >
> > Actually there is no entry of s25fs512s in current spi-nor.c file.
> > For my connected flash part, jedec ID read points
On Wed, 17 Oct 2018 09:10:45 +0200
Boris Brezillon wrote:
> On Wed, 17 Oct 2018 09:07:24 +0200
> Boris Brezillon wrote:
>
> > On Wed, 17 Oct 2018 02:07:43 +
> > Yogesh Narayan Gaur wrote:
> >
> > > >
> > > Actually there is
On Wed, 17 Oct 2018 09:10:45 +0200
Boris Brezillon wrote:
> On Wed, 17 Oct 2018 09:07:24 +0200
> Boris Brezillon wrote:
>
> > On Wed, 17 Oct 2018 02:07:43 +
> > Yogesh Narayan Gaur wrote:
> >
> > > >
> > > Actually there is
On Wed, 17 Oct 2018 08:20:19 +
Yogesh Narayan Gaur wrote:
> Hi Tudor,
>
> > -Original Message-
> > From: Tudor Ambarus [mailto:tudor.amba...@microchip.com]
> > Sent: Wednesday, October 17, 2018 1:31 PM
> > To: Yogesh Narayan Gaur ; Boris Brezillo
On Wed, 17 Oct 2018 07:46:30 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Wednesday, October 17, 2018 1:00 PM
> > To: Yogesh Narayan Gaur
> >
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