Re: [Mesa-dev] [PATCH 08/10] glsl/linker: Modify array_sizing_visitor to handle named interface blocks.

On Fri, Sep 27, 2013 at 12:05 PM, Paul Berry wrote: > Unsized arrays appearing inside named interface blocks now get a > proper size assigned by the array_sizing_visitor. > > Fixes piglit tests: > - spec/glsl-1.50/execution/unsized-in-named-interface-block > - spec/glsl-1.50/execution/unsized-in-n

[Mesa-dev] [PATCH 6/6] st/vdpau: really block until surface is idle

pipe_screen::fence_finish with zero timeout returns quickly and doesn't wait at all. Fix that, and also delete the fence afterwards, so that QuerySurfaceStatus returns the right state later. Addresses: https://trac.videolan.org/vlc/ticket/9281 https://bugs.freedesktop.org/show_bug.cgi?id=68792 ---

[Mesa-dev] [PATCH 5/6] st/vdpau: add new formats to OutputSurface rendering

OutputSurfaces have simple YCbCr rendering functionality built in, but so far only 4:2:0 subsampling worked correctly. This fixes 4:2:2 and 4:4:4 formats. --- src/gallium/state_trackers/vdpau/output.c| 2 +- src/gallium/state_trackers/vdpau/vdpau_private.h | 23 +++ 2

[Mesa-dev] [PATCH 4/6] st/vdpau: fix GenerateCSCMatrix with NULL procamp

As per API specification, it is legal to supply a NULL procamp. In this case, a CSC matrix according to the colorspace should be generated, but no further adjustments are made. Addresses: https://trac.videolan.org/vlc/ticket/9281 https://bugs.freedesktop.org/show_bug.cgi?id=68792 --- src/gallium/

[Mesa-dev] [PATCH 2/6] radeon/uvd: try to fix VC-1 decoding

The DPB size calculations seem to be off; there is various random corruption happening, even with advanced profile. Always assuming a minimum number of references appears to fix it, similarly to H.264. This might overallocate the DPB. Also clean up the SPS/PPS field setup so that it matches VC-1 s

[Mesa-dev] [PATCH 3/6] radeon/uvd: disable VC-1 simple/main profile

It doesn't work (decodes to garbage) with most videos on UVD 3.0. Worse yet, it often results in random memory corruption or GPU hangs. Rumor has it only the newest UVD hardware could do it anyway. --- src/gallium/drivers/radeon/radeon_uvd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

[Mesa-dev] [PATCH 1/6] radeon/uvd: fix video format reporting

UVD can only support NV12 in the case of hardware decoding, but we can still use all other formats for software decoding. Use the UNKNOWN profile to signal that we're not interesting in hardware decoding. v2: use profile instead of entrypoint --- src/gallium/drivers/radeon/radeon_uvd.c | 7 +-

Re: [Mesa-dev] [PATCH 1/3] i965: Don't forget the cube map padding on gen5+.

Kenneth Graunke writes: > On 10/08/2013 10:36 AM, Eric Anholt wrote: >> We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd >> experimentally found to be necessary!), but while the spec still requires >> it on gen5, we'd been missing it in the array-layout cubemaps. > > Ah, I see it n

Re: [Mesa-dev] [PATCH 3/3] configure.ac: report an error if LLVM shared libs are disabled and CL is enabled

Just had a failure because of this - should the default for shared libs not be yes now? On 7 October 2013 13:27, Tom Stellard wrote: > On Mon, Oct 07, 2013 at 01:05:15PM +0200, Marek Olšák wrote: > > From: Marek Olšák > > > > Reviewed-by: Tom Stellard > > > --- > > configure.ac | 5 +++-- > >

[Mesa-dev] [PATCH 2/2] i965: Use IVB specific formula for depthbuffer

After the last patch, we can replace the region allocated in the miptree creation with a more straightforward (and hopefully smaller resulting) buffer based on the bspec's allocation formula. Since I am relatively new to this part of the bspec, I would very much appreciate scrutiny during review o

[Mesa-dev] [PATCH 1/2] i965: Extract region use from hiz depth buffer

The HiZ buffer's allocation requirements were relaxed on Ivybridge. Following a "simple" formula in the bspec was all you needed to satisfy the requirement. To prepare the code for this, extract all places where the miptree was used, when we really only needed the region. This allows an upcoming p

Re: [Mesa-dev] thunderbird / firefox segfault with recent

On 10/08/2013 12:51 AM, Knut Petersen wrote: Hi everybody! I see lines like [ 362.708791] thunderbird-bin[1888]: segfault at 8 ip b0f3f3aa sp bf93fd54 error 4 in i915_dri.so[b0a02000+fc] [ 846.063129] firefox[2008]: segfault at 8 ip b0af63aa sp bff96c74 error 4 in i915_dri.so[b05b9000+f

Re: [Mesa-dev] [PATCH 1/3] i965: Don't forget the cube map padding on gen5+.

On 10/08/2013 10:36 AM, Eric Anholt wrote: We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd experimentally found to be necessary!), but while the spec still requires it on gen5, we'd been missing it in the array-layout cubemaps. Cc: "9.1 9.2" --- src/mesa/drivers/dri/i965/brw_t

Re: [Mesa-dev] [PATCH 3/3] i965: Fix 3D texture layout by more literally copying from the spec.

On 10/08/2013 10:36 AM, Eric Anholt wrote: Fixes 3 texelFetch tests in piglit all.tests. Cc: "9.1 9.2" --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 72 +++--- 1 file changed, 17 insertions(+), 55 deletions(-) Patch 3/3 is Reviewed-by: Chad Versace http://lists.f

Re: [Mesa-dev] [PATCH 04/19] glsl: Construct gl_PerVertex interfaces for GS and VS outputs.

1-4 Reviewed-by: Jordan Justen On Wed, Oct 2, 2013 at 5:45 PM, Paul Berry wrote: > Although these interfaces can't be accessed directly by GLSL (since > they don't have an instance name), they will be necessary in order to > allow redeclarations of gl_PerVertex. > --- > src/glsl/builtin_variabl

Re: [Mesa-dev] [PATCH 2/2] r600g, radeonsi: use fences provided by the winsys

Sorry, I didn't realize this. You are right. My bad. Regardless of my comment, I still wonder what people's opinion on this patch is. Marek On Tue, Oct 8, 2013 at 11:28 PM, Fredrik Höglund wrote: > On Tuesday 08 October 2013, Marek Olšák wrote: >> From: Marek Olšák >> >> This was horribly, horr

Re: [Mesa-dev] RFC: Haswell resource streamer/hw-generated binding tables (v2)

On Wednesday, October 09, 2013 12:41:37 AM Abdiel Janulgue wrote: > Prerequisites: > > - Kernel patches: [1] > (do 'make headers_install' and update libdrm headers after compiling > the kernel) > - Mesa patch: [2] > Series lives on http://cgit.freedesktop.org/~abj/mesa/ mesa_rs branc

Re: [Mesa-dev] [PATCH 1/3] i965: Don't forget the cube map padding on gen5+.

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 10/08/2013 01:28 PM, Eric Anholt wrote: > Ian Romanick writes: > >> On 10/08/2013 10:36 AM, Eric Anholt wrote: >>> We had a fixup for gen4's 3d-layout cubemaps (which, iirc, >>> we'd experimentally found to be necessary!), but while the spec >>> s

[Mesa-dev] [PATCH 16/16] i965/gen7.5: Flush on-chip binding table to pool

Normally, the CS will will just consume the binding table pointer commands as pipelined state. When the RS is enabled however, the RS flushes whatever edited surface state entries of our on-chip binding table to the binding table pool before passing the command on to the CS. Note that the the bind

[Mesa-dev] [PATCH 15/16] i965/blorp: Update surface state entries in blorp.

When hw-generated binding tables are enabled edit the binding table state for new SURFACE_STATE entries that are generated in the blorp path. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff

[Mesa-dev] [PATCH 14/16] i965/gen7.5: Update surface state entry for WM pull constants

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c |4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 08c5720..215ff76 100644 --- a/src/mesa/drivers/

[Mesa-dev] [PATCH 13/16] i965/gen7.5: Update surface state entries for WM UBO surface states

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c |6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index d82a7cf..08c5720 100644 --- a/src/mesa/driver

[Mesa-dev] [PATCH 12/16] i965/gen7.5: Update surface state entries for renderbuffer surfaces

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 564ac76..2dfa05c

[Mesa-dev] [PATCH 11/16] i965/gen7.5: Update surface entries for pull constants and VS UBO surfaces.

When surface_state pointing to pull constant surfaces are changed, update on-chip binding table. Same with VS ubo surface states. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_vs_surface_state.c |9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/d

[Mesa-dev] [PATCH 09/16] i965/gen7.5: Implement opcodes for the hw-generated binding table EDIT commands

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 36 src/mesa/drivers/dri/i965/brw_defines.h|5 src/mesa/drivers/dri/i965/brw_state.h | 15 +- 3 files changed, 55 insertions(+), 1 deletion(-) diff -

[Mesa-dev] [PATCH 08/16] i965/gen7.5: Skip manual binding table upload

When hardware-generated binding tables are taken into use, skip uploading of binding tables generated manually by the driver. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/

[Mesa-dev] [PATCH 10/16] i965/gen7.5: Update surface state entries in update_texture_surfaces

Update the on-chip binding table for every generated texture surface_state entries. Instead of generating binding tables manually, we update individual slots of surface state entries using the new EDIT commands for gen7.5 Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_wm_surfac

[Mesa-dev] [PATCH 06/16] i965/gen7.5: Enable hardware-generated binding tables on render path.

This patch implements the binding table enable command which is also used to allocate a binding table pool where where hardware-generated binding table entries are flushed into. Each binding table offset in the binding table pool is unique per each shader stage that are enabled within a batch. In

[Mesa-dev] [PATCH 07/16] i965/gen7.5: Enable hardware-generated binding tables in blorp path

--- src/mesa/drivers/dri/i965/gen7_blorp.cpp |3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 4d1a65e..031e21e 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/g

[Mesa-dev] [PATCH 05/16] i965/gen7.5: Implement MI_RS_STORE_DATA_IMM workaround for 3DPRIMITIVE commands

Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_draw.c | 14 ++ src/mesa/drivers/dri/i965/gen7_blorp.cpp | 14 ++ 2 files changed, 28 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 549

[Mesa-dev] [PATCH 04/16] i965/gen7.5: Temporarily disable resource streamer when updating state base address.

Bspec: "Prior to changing the Surface State Base Address, the resouce streamer must be disabled within a batch buffer where the RS is enabled. RS is re-enabled again once the SBA is updated." The resource streamer can be toggled within a batch using MI_RS_CONTROL. Signed-off-by: Abdiel Janulgue

[Mesa-dev] [PATCH 03/16] i965/gen7.5: Pass resource streamer enable flags on batchbuffer start

This is passed on the kernel to enable the resource streamer enable bit on MI_BATCHBUFFER_START Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/intel_batchbuffer.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b

[Mesa-dev] [PATCH 02/16] i965/gen7.5: Introduce INTEL_RESOURCE_STREAMER to toggle resource streamer

export INTEL_RESOURCE_STREAMER={0,1} To switch on/off resource streamer. Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_context.h |1 + src/mesa/drivers/dri/i965/intel_context.c | 24 2 files changed, 25 insertions(+) diff --git a/src/mesa/driv

[Mesa-dev] [PATCH 01/16] i965/gen7.5: Implement resource streamer control opcodes

Used to toggle the resource streamer within a batchbuffer Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/intel_reg.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h index d732038..92075a6 10064

[Mesa-dev] RFC: Haswell resource streamer/hw-generated binding tables (v2)

Prerequisites: - Kernel patches: [1] (do 'make headers_install' and update libdrm headers after compiling the kernel) - Mesa patch: [2] This is an update from my previous RFC patches [3]. Most notable change is that the resource streamer is an experimental feature disabled by defaul

Re: [Mesa-dev] [PATCH 12/19] glsl: Generalize processing of variable redeclarations.

On 5 October 2013 12:25, Kenneth Graunke wrote: > On 10/02/2013 05:45 PM, Paul Berry wrote: > > This patch modifies the get_variable_being_redeclared() function so > > that it no longer relies on the ast_declaration for the variable being > > redeclared. In future patches, this will allow > > ge

Re: [Mesa-dev] [PATCH 2/2] r600g, radeonsi: use fences provided by the winsys

On Tuesday 08 October 2013, Marek Olšák wrote: > From: Marek Olšák > > This was horribly, horribly broken. The limit was 1024 fences created > from the start of the application and as you probably know, pipe fences are > not reusable. If you wanted to use one fence per frame, you could only do >

Re: [Mesa-dev] [PATCH 06/19] glsl: Refactor code to check that identifier names are valid.

On 5 October 2013 12:12, Kenneth Graunke wrote: > On 10/02/2013 05:45 PM, Paul Berry wrote: > > GLSL reserves identifiers beginning with "gl_" or containing "__", but > > we haven't been consistent about enforcing this rule. This patch > > makes a new function to check whether identifier names a

Re: [Mesa-dev] [PATCH] glsl: Rename the fourth argument to get_interface_instance.

On 10/08/2013 02:17 PM, Paul Berry wrote: > Interface declarations have two names associated with them: the block > name and the instance name. It's the block name that needs to be > passed to get_interface_instance(). This patch renames the argument > so that there's no confusion. > --- > src/g

[Mesa-dev] [PATCH] glsl: Rename the fourth argument to get_interface_instance.

Interface declarations have two names associated with them: the block name and the instance name. It's the block name that needs to be passed to get_interface_instance(). This patch renames the argument so that there's no confusion. --- src/glsl/glsl_types.cpp | 8 src/glsl/glsl_types.h

Re: [Mesa-dev] [PATCH 02/19] glsl: Fix block name of built-in gl_PerVertex interface block.

On 5 October 2013 12:10, Kenneth Graunke wrote: > On 10/02/2013 05:45 PM, Paul Berry wrote: > > Previously, we erroneously used the name "gl_in" for both the block > > name and the instance name. > > --- > > src/glsl/builtin_variables.cpp | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-)

Re: [Mesa-dev] [PATCH 1/9] i965: Fix a compiler warning about conservative depth enums.

Sorry, that was a bit sloppy on my part.. Reviewed-by: Chris Forbes On Wed, Oct 9, 2013 at 10:00 AM, Eric Anholt wrote: > --- > src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c > b/src/mesa/drivers/d

[Mesa-dev] [PATCH 8/9] i965: Try to avoid stalls on the GPU when doing glBufferSubData().

On DOTA2, framerate on dota2-de1.dem in windowed mode on my laptop improves by 7.69854% +/- 0.909163% (n=3). In a microbenchmark hitting this code path (wall time of piglit vbo-subdata-many), runtime decreases from 0.8 to 0.05 seconds. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 24 ++

[Mesa-dev] [PATCH 7/9] i965: Be sure to reset brw->vb.buffers[] when trying to redo vertex setup.

The brw_prepare_vertices that sets up buffers[] depends on these parameters, so don't let brw_prepare_vertices() skip it. --- src/mesa/drivers/dri/i965/brw_draw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c inde

[Mesa-dev] [PATCH 9/9] i965: Add perf debug hint when the app makes us do index buffer scanning.

--- src/mesa/drivers/dri/i965/brw_draw.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index b6cfd53..0acd089 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH 6/9] i965: Add support for GL_ARB_texture_buffer_range.

Supporting this extension turns out to simplify our code a bit over not supporting this extension, once the glBufferSubData() synchronization code lands. --- docs/GL3.txt | 2 +- src/mesa/drivers/dri/i965/brw_context.c | 1 + src/mesa/drivers/dri/i9

[Mesa-dev] [PATCH 5/9] i965: Relax the alignment requirements on uniform buffer objects.

I noticed this while looking for a cite for the similar requirement I was going to put on texture buffer objects. We don't actually have a test for this, but the GL_ARB_texture_buffer_range alignment test we have makes me reasonably confident that this works, too. This causes a regression to be r

[Mesa-dev] [PATCH 4/9] i965: Add a note about the late-allocation in intel_bufferobj_buffer().

This was mostly for the i915 system-memory VBO code, which we don't have any more, but since that existed we've ended up producing dependencies on it being there. --- src/mesa/drivers/dri/i965/intel_buffer_objects.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH 1/9] i965: Fix a compiler warning about conservative depth enums.

--- src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 7ddeb6e..a2046c3 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/g

[Mesa-dev] [PATCH 3/9] i965: Drop intel_bufferobj_source().

Since src_offset was always 0, it wasn't doing anything for us beyond intel_bufferobj_buffer(). --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 14 -- src/mesa/drivers/dri/i965/intel_buffer_objects.c | 15 ++- src/mesa/drivers/dri/i965/intel_buffer_objects.h | 5 ---

[Mesa-dev] [PATCH 2/9] i965: Fix texture buffer rendering after a whole buffer replacement.

If glBufferData(), glBufferSubData(0, obj->Size), or similar happens, we get a new drm_intel_bo for the buffer object, and thus need to re-upload texture buffer state so we point at the new data. Fixes the new piglit GL_ARB_texture_buffer_object/data-sync Cc: "9.2" --- src/mesa/drivers/dri/i965

[Mesa-dev] glBufferSubData() GPU stall reduction (DOTA2 optimization).

Since it sounds like valve won't be able to fix dota2's rendering to use ARB_mbr soon, here's a series to add just a little bit of tracking that works around most of the overhead of not using ARB_mbr with their rendering pattern. 7.69854% +/- 0.909163% (n=3) fps improvement with default settings.

[Mesa-dev] [PATCH] llvmpipe: abstract the code to set number of subpixel bits

As we're moving towards expanding the number of subpixel bits and the width of the variables used in the computations we need to make this code a bit more centralized. Signed-off-by: Zack Rusin --- src/gallium/drivers/llvmpipe/lp_rast.h | 9 + src/gallium/drivers/llvmpipe/lp_setup.

Re: [Mesa-dev] [PATCH 7/7] i965/blorp: Allow format conversions.

On 10/08/2013 01:42 PM, Eric Anholt wrote: > Kenneth Graunke writes: > >> BLORP performs blits by drawing a rectangle with a shader that samples >> from the source texture, and writes color data to the destination. >> >> The sampler always returns 32-bit RGBA float data, regardless of the >> sour

Re: [Mesa-dev] [PATCH 3/3] llvmpipe: implement 64 bit mul opcodes in llvmpipe

Am 08.10.2013 22:00, schrieb Matt Turner: > Do the ARB_gpu_shader5 tests in piglit (fs-imulExtended, > fs-umulExtended) tests pass? Since the patch makes no attempt to translate it from glsl, I can't see how it would. Might be a nice addition though, but it would require glsl version and extension

Re: [Mesa-dev] [PATCH 7/7] i965/blorp: Allow format conversions.

On 10/07/2013 04:31 PM, Kenneth Graunke wrote: BLORP performs blits by drawing a rectangle with a shader that samples from the source texture, and writes color data to the destination. The sampler always returns 32-bit RGBA float data, regardless of the source format's component ordering or data

Re: [Mesa-dev] [PATCH 7/7] i965/blorp: Allow format conversions.

Kenneth Graunke writes: > BLORP performs blits by drawing a rectangle with a shader that samples > from the source texture, and writes color data to the destination. > > The sampler always returns 32-bit RGBA float data, regardless of the > source format's component ordering or data type. Likewi

Re: [Mesa-dev] [PATCH 1/3] i965: Don't forget the cube map padding on gen5+.

On 10/08/2013 10:36 AM, Eric Anholt wrote: > We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd > experimentally found to be necessary!), but while the spec still requires > it on gen5, we'd been missing it in the array-layout cubemaps. Ah, I see it now: >From the Sandybridge PRM, Vo

Re: [Mesa-dev] [PATCH 1/3] i965: Don't forget the cube map padding on gen5+.

On 10/08/2013 11:22 AM, Ian Romanick wrote: > On 10/08/2013 10:36 AM, Eric Anholt wrote: >> We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd >> experimentally found to be necessary!), but while the spec still requires >> it on gen5, we'd been missing it in the array-layout cubemaps.

Re: [Mesa-dev] [PATCH 1/3] i965: Don't forget the cube map padding on gen5+.

Ian Romanick writes: > On 10/08/2013 10:36 AM, Eric Anholt wrote: >> We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd >> experimentally found to be necessary!), but while the spec still requires >> it on gen5, we'd been missing it in the array-layout cubemaps. > > I think we didn't

Re: [Mesa-dev] [v3 1/4] glsl: add ir_cache class for IR serialization (WIP)

Tapani Pälli writes: > Patch introduces ir_cache class that can serialize a gl_shader > to memory with help of memory_writer class and also unserialize > it back with help of memory_map class. > > This can be used by the shader compiler to cache individual shaders > and skip lexing, parsing, type

Re: [Mesa-dev] [PATCH 3/3] llvmpipe: implement 64 bit mul opcodes in llvmpipe

Do the ARB_gpu_shader5 tests in piglit (fs-imulExtended, fs-umulExtended) tests pass? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] r600g, radeonsi: use fences provided by the winsys

From: Marek Olšák This was horribly, horribly broken. The limit was 1024 fences created from the start of the application and as you probably know, pipe fences are not reusable. If you wanted to use one fence per frame, you could only do that for 1024 frames, whish was pretty bad. The error messa

[Mesa-dev] [PATCH 1/2] winsys/radeon: add the implementation of fences from r300g

From: Marek Olšák --- src/gallium/drivers/r300/r300_flush.c | 13 ++- src/gallium/drivers/r300/r300_screen.c| 28 +++--- src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 56 +++ src/gallium/winsys/radeon/drm/radeon_winsys.h | 23 +++ 4 f

Re: [Mesa-dev] [PATCH 3/3] llvmpipe: implement 64 bit mul opcodes in llvmpipe

Am 08.10.2013 21:22, schrieb Zack Rusin: > Both the imul_hi and umul_hi are working with this patch. > > Signed-off-by: Zack Rusin > --- > src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 60 > ++ > 1 file changed, 60 insertions(+) > > diff --git a/src/gallium/auxiliary

Re: [Mesa-dev] [PATCH RFC 3/6] i965: add FS_OPCODE_OVERWRITE_DST

Chia-I Wu writes: > From: Chia-I Wu > > FS_OPCODE_OVERWRITE_DST is used to indicate that the destination register is > (completely) overwritten. No code is emitted, but the liveness analysis can > use it as a hint to add the destination register to DEF bitset. This is > needed because it is ha

Re: [Mesa-dev] [PATCH 0/7] ARB_gpu_shader5 textureGather*, Part 2

On 10/08/2013 02:34 AM, Chris Forbes wrote: > This series adds support for the following textureGather* enhancements > that are part of ARB_gpu_shader5: > > - new textureGatherOffset variants > - nonconstant offset for all textureGatherOffset variants, when GLSL 4.00 or >ARB_gpu_shader5 is in

Re: [Mesa-dev] [PATCH 5/7] i965: relax brw_texture_offset assert

On 10/08/2013 02:34 AM, Chris Forbes wrote: > Some texturing ops are about to have nonconstant offset support; the > offset in the header in these cases should be zero. > > Signed-off-by: Chris Forbes > --- > src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +- > 1 file changed, 1 insertion(+), 1 de

[Mesa-dev] [PATCH 3/3] llvmpipe: implement 64 bit mul opcodes in llvmpipe

Both the imul_hi and umul_hi are working with this patch. Signed-off-by: Zack Rusin --- src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c | 60 ++ 1 file changed, 60 insertions(+) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c b/src/gallium/auxiliary/galli

[Mesa-dev] [PATCH 2/3] gallium: Add support for 32x32 muls with 64 bit results

The code introduces two new 32bit integer multiplication opcodes which can be used to produce correct 64 bit results. GLSL, OpenCL and D3D10+ require them. We use two seperate opcodes, because they match the behavior of GLSL and OpenCL, are a lot easier to add than a single opcode with multiple des

[Mesa-dev] [PATCH 1/3] gallivm: support printing of 64 bit integers

only 8 and 32 bit integers were supported before. Signed-off-by: Zack Rusin --- src/gallium/auxiliary/gallivm/lp_bld_printf.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_printf.c b/src/gallium/auxiliary/gallivm/lp_bld_printf.c in

Re: [Mesa-dev] [PATCH] st/vdpau: set correct timeout for fence_finish

Ok. I didn't know Grigori had been working on it. Marek On Tue, Oct 8, 2013 at 8:40 PM, Christian König wrote: > Am 08.10.2013 19:13, schrieb Marek Olšák: > >> From: Marek Olšák >> >> The timeout of 0 is equivalent to calling fence_signalled, which is not >> very >> useful here. > > > Grigori a

Re: [Mesa-dev] [PATCH 2/3] mesa: Fix compiler warnings when ALIGN's alignment is "1 << value".

Brian Paul writes: > On 10/08/2013 11:36 AM, Eric Anholt wrote: >> We hadn't run into order of operation warnings before, apparently, since >> addition is so low on the order. >> >> Cc: "9.1 9.2" >> --- >> src/mesa/main/macros.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> d

Re: [Mesa-dev] [PATCH] st/vdpau: set correct timeout for fence_finish

Am 08.10.2013 19:13, schrieb Marek Olšák: From: Marek Olšák The timeout of 0 is equivalent to calling fence_signalled, which is not very useful here. Grigori already attached the same fix to the bug https://bugs.freedesktop.org/show_bug.cgi?id=68792. He's probably already working on the re

Re: [Mesa-dev] [PATCH 0/7] i965: BLORP with format conversions

On 10/07/2013 04:31 PM, Kenneth Graunke wrote: > This series introduces support for blitting and CopyTexSubImage with > format conversions via the BLORP engine. Previously, we fell back to > the meta paths, which fell back to unpack/pack code, which was pretty > dire for performance. > > In parti

Re: [Mesa-dev] [PATCH 7/7] i965/blorp: Allow format conversions.

On 10/07/2013 04:31 PM, Kenneth Graunke wrote: > BLORP performs blits by drawing a rectangle with a shader that samples > from the source texture, and writes color data to the destination. > > The sampler always returns 32-bit RGBA float data, regardless of the > source format's component ordering

Re: [Mesa-dev] [PATCH 6/7] i965/blorp: Rework sRGB override behavior.

On 10/07/2013 04:31 PM, Kenneth Graunke wrote: > The previous code for sRGB overrides assumes that the source and > destination formats are equal, other than the color space. This won't > be feasible when we add support for format conversions. > > Here are a few cases, and how the old code handle

Re: [Mesa-dev] [PATCH 3/4] glsl/gs: handle gl_ClipDistance geometry input in lower_clip_distance.

On 09/28/2013 02:59 PM, Paul Berry wrote: > On 27 September 2013 14:32, Ian Romanick > wrote: > > There are some bits of this patch I'm trying to understand. I think > they can be cleared up by one question below... > > On 09/14/2013 01:00 PM, Paul Berry

Re: [Mesa-dev] [PATCH 2/3] mesa: Fix compiler warnings when ALIGN's alignment is "1 << value".

On 10/08/2013 10:36 AM, Eric Anholt wrote: > We hadn't run into order of operation warnings before, apparently, since > addition is so low on the order. > Reviewed-by: Ian Romanick > Cc: "9.1 9.2" > --- > src/mesa/main/macros.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff

Re: [Mesa-dev] [PATCH 1/3] i965: Don't forget the cube map padding on gen5+.

On 10/08/2013 10:36 AM, Eric Anholt wrote: > We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd > experimentally found to be necessary!), but while the spec still requires > it on gen5, we'd been missing it in the array-layout cubemaps. I think we didn't bother with that patch because

Re: [Mesa-dev] [PATCH 1/4] glsl: Keep track of location for interface block fields.

Series Reviewed-by: Jordan Justen On Sat, Sep 14, 2013 at 1:00 PM, Paul Berry wrote: > This patch adds a "location" element to struct glsl_struct_field, so > that we can keep track of the gl_varying_slot associated with each > built-in geometry shader input. > > In lower_named_interface_blocks,

Re: [Mesa-dev] [PATCH] gallium: new, unified pipe_context::set_sampler_views() function

Am 08.10.2013 02:23, schrieb Brian Paul: > The new function replaces four old functions: set_fragment/vertex/ > geometry/compute_sampler_views(). > > Note: at this time, it's expected that the 'start' parameter will > always be zero. > > --- > > This change touches quite a few files. I've proba

Re: [Mesa-dev] [PATCH 2/3] mesa: Fix compiler warnings when ALIGN's alignment is "1 << value".

On 10/08/2013 11:36 AM, Eric Anholt wrote: We hadn't run into order of operation warnings before, apparently, since addition is so low on the order. Cc: "9.1 9.2" --- src/mesa/main/macros.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/macros.h b/src/mesa/

[Mesa-dev] [PATCH 1/3] i965: Don't forget the cube map padding on gen5+.

We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd experimentally found to be necessary!), but while the spec still requires it on gen5, we'd been missing it in the array-layout cubemaps. Cc: "9.1 9.2" --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 22 +++--- 1 fil

[Mesa-dev] [PATCH 3/3] i965: Fix 3D texture layout by more literally copying from the spec.

Fixes 3 texelFetch tests in piglit all.tests. Cc: "9.1 9.2" --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 72 +++--- 1 file changed, 17 insertions(+), 55 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c

[Mesa-dev] [PATCH 2/3] mesa: Fix compiler warnings when ALIGN's alignment is "1 << value".

We hadn't run into order of operation warnings before, apparently, since addition is so low on the order. Cc: "9.1 9.2" --- src/mesa/main/macros.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h index 1052f75..05aad4e 100644 ---

[Mesa-dev] [PATCH] st/vdpau: set correct timeout for fence_finish

From: Marek Olšák The timeout of 0 is equivalent to calling fence_signalled, which is not very useful here. --- src/gallium/state_trackers/vdpau/presentation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/vdpau/presentation.c b/src/gallium/state

Re: [Mesa-dev] [PATCH 1/2] radeonsi: draw register fixes for CIK

The series is Reviewed-by: Michel Dänzer -- Earthling Michel Dänzer| http://www.amd.com Libre software enthusiast |Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org h

Re: [Mesa-dev] PATCH: R600/SI: Enable the verifier on most lit tests

3rd patch is reviewed-by:Vincent Lejeune The first one >Subject: [PATCH 1/4] R600/SI: Mark the EXEC register as reserved > >This prevents the machine verifier from complaining about uses of >an undefined physical register. >--- > lib/Target/R600/SIRegisterInfo.cpp | 3 ++- > 1 file changed, 2 in

[Mesa-dev] [PATCH 1/2] radeonsi: draw register fixes for CIK

From: Marek Olšák This doesn't fix any known issue. I'm just following the docs. --- src/gallium/drivers/radeonsi/si_state.c | 10 ++ src/gallium/drivers/radeonsi/si_state_draw.c | 26 +- 2 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/gal

[Mesa-dev] [PATCH 2/2] radeonsi: fix occlusion queries for CIK

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_state_draw.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 626ba95..d20658e 100644 --- a/src/gallium/dri

[Mesa-dev] [Bug 70123] Freeze caused by 'winsys/radeon: remove cs_queue_empty' commit

https://bugs.freedesktop.org/show_bug.cgi?id=70123 --- Comment #4 from Christian König --- (In reply to comment #3) > Unfortunately this doesn't fix the issue. When I get a spare moment I'll try > the patch on the desktop pc (which has a different card). Please try to attach a gdb to the deadloc

Re: [Mesa-dev] [PATCH 6/7] i965/blorp: Rework sRGB override behavior.

On Mon, Oct 07, 2013 at 04:31:22PM -0700, Kenneth Graunke wrote: > The previous code for sRGB overrides assumes that the source and > destination formats are equal, other than the color space. This won't > be feasible when we add support for format conversions. > > Here are a few cases, and how t

Re: [Mesa-dev] [PATCH 4/7] i965/blorp: Use R16_UNORM for Z32F surfaces.

On Mon, Oct 07, 2013 at 04:31:20PM -0700, Kenneth Graunke wrote: > Currently, all that matters is that we copy the correct number of bits, > so any format that has 32-bits of data will work fine. > > Once BLORP begins handling format conversions, the sampler will need to > correctly interpret the

[Mesa-dev] [Bug 70123] Freeze caused by 'winsys/radeon: remove cs_queue_empty' commit

https://bugs.freedesktop.org/show_bug.cgi?id=70123 --- Comment #3 from Jeff Blake --- Unfortunately this doesn't fix the issue. When I get a spare moment I'll try the patch on the desktop pc (which has a different card). -- You are receiving this mail because: You are the assignee for the bug.

Re: [Mesa-dev] [PATCH 2/7] glsl: relax const offset requirement for textureGatherOffset

The commit message is wrong -- there is no requirement for the offset to be dynamically uniform, either in the spec or in the i965 implementation in later patches. On Tue, Oct 8, 2013 at 10:34 PM, Chris Forbes wrote: > Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required to be > a constant

[Mesa-dev] [PATCH 5/7] i965: relax brw_texture_offset assert

Some texturing ops are about to have nonconstant offset support; the offset in the header in these cases should be zero. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_shad

[Mesa-dev] [PATCH 4/7] i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets.

The generator code ends up clearer this way than if we had to sniff via mlen. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [PATCH 3/7] i965: add missing tg4 case in brw_instruction_name

Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 61c4bf5..19500d1 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/sr

[Mesa-dev] [PATCH 2/7] glsl: relax const offset requirement for textureGatherOffset

Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required to be a constant expression. With that extension, it is relaxed to be any dynamically uniform expression. If the value is not dynamically uniform, the results are undefined. Signed-off-by: Chris Forbes --- src/glsl/builtin_functions.cp

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