You wrote on 11.05.2004 02:53:44:
how does protel 99SE handle drilled slots?
not at all, unfortunately
Gisbert
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Ray,
try to draw a closed track on the bottom layer surrounding the area you
don't want routes, and give the track the attribute keepout. With this,
no route on bottom layer may cross this area. It may happen, that the
router places short traces which stay only within this area. Anyway, you
can
Hi,
I would be grateful if someone had the pcb of a 21-slot 6U backplane to
share (e.g.VME would be fine). I don't need any components or routing,
just the mechanical (and maybe keepout) layers with the outline and
mounting hole definitions.
Thank you.
Mit freundlichem Gruß
Kind regards
Yes
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Michael Biggs
Brian,
we went completely away from gold, nothing but problems in the soldering
process. Silver showed much better results for us. The price is about the
same. Maybe it depends on the assembly house and the processes they are
using.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
Hi Abd and Ian,
unfortunately that does not work. I tried to do just what you suggested,
but it selects nothing. What I do now is to place the PCB outline not in
the center of the workspace, as it defaults to, but near the down-left
corner of the workspace. That leaves enough room for all
Hi,
did anyone notice the following bug in 99SE? I'm referring to SP6.
When you draw a PCB outline from the scratch and then call the update PCB
function in the corresponding schematic, in order to import your parts and
nets into the PCB file, the synchronizer places the parts on the right side
Leo,
check again that there really is no overlap whatever small between the
split sections.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
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Hi,
SPECCTRA V7 works fine with Protel99SE. Just the usual small problem with
via hole size, when read back to Protel. All via holes are set to 28mil,
need to be gloablly changed after. This issue has been between SPECCTRA and
Protel ever since, and still exists in DXP.
Mit freundlichem Gruß
Gisbert,
OK, I'm lost, call me dumb, what's a STRG key ?
JaMi
JaMi,
Strg is written on the key on my (german) keyboard. Maybe on a us keyboard
it is named differently, Control, may be.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
* * * * * * * * * * * * *
Rene,
while starting up 99SE hold the STRG key pressed in order to prevent 99SE
to load any project. Then load the manually one after the other to see
where the problem is located.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Hi Julian,
this also happens when you update a schematic part from library.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Julian
www.nateurope.com
ga@nateurope.
com An: Protel EDA Forum
[EMAIL PROTECTED]
Kopie:
03.12.2002 Thema: [PEDA] Rules and PCB
library definitions
10
ga@nateurope.
com An: Protel EDA Forum
[EMAIL PROTECTED]
Kopie
just
received
my copy of DXP, but have to start the learning curve first, which will
take
some time. So I cannot check myself now.
Thank you.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
ga@nateurope.
com
Hello group,
does anyone know how to overcome the following effect:
When I define e.g. a BGA component in PCB library editor and include
fanouts and preroutes for the pads, once I have that part placed on the
PCB, the specified rules for clearance, power connection, etc. do not apply
for the
Hi group,
I have a design done some months ago. I want to do a redesign now. As in
the meantime a number of PCB decals have been changed, and I want these
changes to be taken into the redesign layout. Is there a possibility of
doing an update parts from library function, which updates all used
Robert, Ian,
this answers my question also. Thank you.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Robert M.
Hi Dave,
if you ever renamed layers in the layer stack manager you get these strange
results. It is a bug I reported some months ago.
If you remember how to rename them to their original names, that might
help. If not, no chance (to my knowledge). Maybe a copy of layer by layer
to a clean
Waldemar,
I remember a similar situation. You could try two approaches:
1. save the DDB in spite of the error messages, close it. and do a repair
on this DDB. This helped me in one case.
2. Create a new DDB, and copy all documents from the DDB with the error
message into the new one, and then
Miker,
you are of course correct, but I don't think that this meaning of fanout
was questioned.
Fanout also means routing a short trace to escape from a SMD pad, and then
placing a via to connect to an inner layer or a plane.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
Baseball bats are also sometimes used as weapons, if you don't have a gun
handy (yes, in the U.S. you can still
own guns, thank God!).
Ivan, I am sure the people especially in the Washington area are very
pleased about this fact at the moment.
Regards,
Gisbert
* * * * * * * * * * * * * * *
Ivan,
I can back this. I opened 3 Yahoo member accounts with different email
addresses for different purposes, and did not receive any spam so far. Of
course, when opening the account, you must uncheck all the pre-checked
options for information they want to supply you with. If you do that, no
Hi,
I cannot confirm this behaviour. The given procedure works absolutely fine
here, just toggles the 3 layers.
W2K SP3, 99SE SP6, but not all the other processes you mentioned, just
Lotus.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Hi group,
since this SP7 stuff is being discussed, I typically have 100+ emails from
the forum every day, instead of 10-30 before. Yes, I also would like to
have SP7, but I suggest going back to normal. If someone wants to add
JaMi's Ceterum censeo ... to every mail as a reminder for Altium,
Hello JaMi,
the effect you describe
This time, however, rather than wait for Protel to load, I hit the
minimize button while it still has its little Protel Logo Box in the
center of the screen, and is starting to load files, and it dissappears
into
the taskbar, so I can launch PowerDesk (or
JaMi,
I support your views on another service pack. There are several long-known
bugs, which should be fixed as far as possible. M$ still delivers service
packs for Win2K, although Win XP is the product sold today. Altium should
do the same.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
Hello,
just a short question, as I did not have the time to evaluate the DXP trial
so far:
In the documentation/tutorials Altium placed on their website concerning
DXP I did not find a single word about a Specctra interface. Does DXP have
such an interface like 99SE or not, and did anyone test
Hi Matt,
another point I forgot to mention:
If you have launched Protel without loading the DDB (by pressing the STRG
key while Protel is loading), you can then try the repair function on the
DDB that crashes your system (Down Arrow/Design Utilities/Repair). You can
only repair DDBs which are
Keep this fight off the forum! Mail it directly to the person(s) you want
to address, if you think it appropriate.
Did they not teach you manners when you were young? Obviously not.
Most probably you will start shouting at me now. Send your insults to my
given eMail address, not to the forum.
-
ga@nateurope.
com An: Protel EDA Forum
[EMAIL PROTECTED]
Kopie
Hi Ian,
thank you for the quick response. Here are the details:
snip
What would be really really helpful would be you laying out the info in
the
following form so I can copy and paste.
Date: 2002/01/28 sort of format (/mm/dd)
Summary: PCB: Gerber gerneration of renamed layers is (wrong?)
You make your point very clear, Ian. I am with you.
Concerning the bug list you manage:
Did you add the bug in gerber generation of renamed layers and the bug in
translating layer information to Specctra to the list, which I described
some weeks ago? I never received any comment to these mails.
JaMi,
aren't you mixing up some things in this discussion?
See my comments below.
I also eventually found this forum, which has been of some help. The
problem
here is that in general everybody refuses to realize or acknowledge that
this (as with many other things) is a bug, notwithstanding the
Tony,
you wrote on 23.07.2002 04:47:57:
Speaking about the ability of any other Windows Application: I really
HATE
IT when I'm working on a document in MS Word and I decide to change my
print
driver for HP Laserjet to Acrobat and all my FRICKIN' PAGE FORMATTING
CHANGES!! You what that to be
Hi,
I don't recall if this was brought up before, but there is a very
irritating bug in the influence of Rules/Routing layers and the SPECCTRA
export function. It is easy to reproduce. Do the following:
Take a multilayer PCB (no matter how many layers, but at least one inner
routing layer) and
I have been following this thread (and others on the same topic before)
with some astonishment. I placed a .TIF file with our company logo on the
schematic templates long time ago, which is stored in only one location,
far away from any protel files, and it just works fine with any project I
Hi,
when I try to generate a BOM from SCH in spreadsheet format, I receive an
error message: CLIENT99SE: License information for TF1Book is invalid.
What's that? Generation of BOM in Protel format works okay. Protel99SE SP6.
Win2K.
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Abd-ulRahman Lomax wrote:
What does the Stack Manager show? What shows in the Design/Split Planes
dialog?
Stack Manager shows:
TopLayer
MidLayer1
MidLayer2
InternalPlane1 (+3.3V)
InternalPlane2 (GND)
MidLayer3
MidLayer4
MidLayer5
MidLayer6
InternalPlane3 (+2.5V)
InternalPlane4 (VCC)
MidLayer7
Hi,
I'd like to report a bug (?) in the layer stack management of power planes.
I set up a board with 5 power planes; lateron I found out that by
efficiently using split planes I could reduce them to 4. The obsolete power
plane was named Internal Plane 4. So I deleted this plane and renamed
A workaround to those issues is:
Print to Acrobat Writer, and then send to printer from Acrobat. Works fine
with \ negation.
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
David,
I cannot support your experience. I am just doing a board containing routes
using arcs on different layers, and the print preview works just fine.
Protel 99 SE SP6, Win2K SP2.
Gisbert Auge
What the heck do the flies do in the archive?
;-)
Gisbert
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Steve and Heiko,
thank you for the advice. Maybe I should have provided more details. Before
posting the question, I had checked the menu properties, and they seem to
be ok (including the ampersand at the correct position of the string). I
have W2K pro SP2 installed, and Protel SP6. Perhaps
Rene,
The update design has spurious errors. It may happen that changing
a string ( 10k to 100k) in the schematic, leads to a hole bunch
of actions during update design. Quite often remove a connection
and redo the same connection. This appears to be some propagated
errors. The probability is
Kiernan,
I'm still on my first PCB under P99SE. I need to add quite a few extra
routes,
but the PCB is really dense. Can I route these on the InternalPlane
layers?
As the following text shows that you are talking about plane layers, I
would strongly discourage you to do so, though it
I don't know of any fix, but this also is a known, old bug. Is it on the
bug list already, Ian and Abdul?
Regards,
Gisbert
rimas
JaMi,
I spend about 20 - 30 minutes a day with this list; maybe more, if I decide
to write detailed posts, which seldom happens. It is really worth the time.
The members of this group are giving professional support to all kinds of
problems related to this EDA product I earn my salary with.
Probably the solution to your proble, is to uncheck the unrouted net
constraint button in Tools/Design Rule Check menu, as long as the board
has not been routed. Unrouted nets are always flagged the way you describe.
This is very helpful when checking for remaining (partially) unrouted nets,
or,
I don't think there is. This would be on my wishlist, though.
Regards,
Gisbert
Sean James
If this is supposed to be joke, it is not funny.
How did the attachment slip through the Techserv filter?
Gisbert
Ken Henrich
Hi Jeff,
I know this might be of little help, but you should seriously think about
changing PLD development tools. You got the Altera tools, so why don't you
use them? There sure is a reason for most of us Protel users, as far as I
know, not to use the PLD tools from Protel. MAX Plus is
According to Altium Germany the additional license fee is EUR 3875, which
is significantly cheaper than 3995 US$, if you take into account the
exchange rate, and it includes ATS and update to Phoenix. Sounds
interesting to me.
Regards,
Gisbert Auge
N.A.T. GmbH
Why don't you generate 2 sets of Gerber files, one with and one without
tenting, and select the top soldermask with tented vias from one set, and
the bottom soldermask with not tented vias from the other set?
Gisbert Auge
Hi Gene,
just keep in mind that the dongle drivers for V7 do not run under WIN2K
(and probably not under XP either). There is no known workaround for that.
No problems under W95 and W98.
Regards,
Gisbert Auge
N.A.T. GmbH
Hi all,
I agree with Remco, you always want to change something after the
autorouter has finished. The DWIT command (do what I'm thinking) still
has not been implemented :-)
But I want to speak in favour of Swiss cheese, not only because of its
excellent taste.
It is true that an
You wrote on 17.01.2002 14:43:05:
Georg,
I had a similar problem, if I understand your question correctly. We have
a
product that used to use ispLSI2064 devices, and then we could only get
the
2064A variant. Our programming software wouldn't work with it, as it
detected the wrong signature. We
Hi all,
I did a design with blind and buried vias (7 signal layers, 3 power
layers), which I had routed by SPECCTRA. All looks fine in SPECCTRA, but it
won't read back to Protel (actually it will, but thousands of errors show
up). I know I have to correct the drill size of vias manually, as
Hi,
I can only warn you to use standard footprints without thorough check.
Many of them are just useless without modification and should only be taken
as examples. E.g. almost all QFP footprints have much too wide pads, and
all DSUB and RJ connectors look nice, but do most probably not match
Hello Mark,
we use Lattice and Altera for programmable logic. ispDESIGN Expert
(Lattice) is freeware. They call it starter, but it covers the M4 family
up to M4-512, the complete ispLSI1K, 2K, 5K families, and 8K up to 8840.
That is more than 90% of all the devices they do. For Altera we use
You are invited to have a look at them under www.nateurope.com.
By the way, do you have a name, intellasys?
Gisbert
intellasys
It sure does, Brian. :-)
Gisbert
Brian
Guralnick
Hallo Waldemar,
if it still is possible to go back one step to the PCB with the components
to be deleted, I would suggest that you do so. Then, in PCB editor, select
Tools/Unroute/Components and unroute the components you want to be deleted.
Then do the update PCB from Schematic. There should
You wrote on 12.12.2001 10:15:02:
Bastards... Do they want to sell ICs or software? It always makes me
mad.
Rant off... goodnight..
Tony
Both, Tony, ICs and SW. Therefore, whereever possible, I implement only
devices into my designs which supply development software for free.
Gisbert
* *
Not to my knowledge, but why would you want to do that?
Gisbert Auge
N.A.T. GmbH
Sean James
You wrote on 06.12.2001 06:36:49:
Altium tech support is nearly irrelevant
right now, since this forum is extremely helpful. The last time I used
Protel support was in 1996, when I first started using the program. I
haven't needed it since. I am quite sure that I would still need it if
Hi,
there is a small program called CTSPD
(ftp://ftp.heise.de/pub/ct/ctsi/ctspd092.zip) that does conformity and
plausibility checks on the EEPROM contents of SDRAM modules. If a module
fails this check, it does not necessarily mean that it is not working
properly, but that the EEPROM data
Hi Mike,
I have no problem with posting the reply I received from Altium to the
group. I don't know why this is being made personal, anyway, it's helpful.
Maybe Abd's comment gives the reason for it. But, as I learnt from this
mail, there are some articles in the knowledge base I did not check
I can back that statement, Abd ul-Rahman. Last week I received a mail
directed only to me from Protel support concerning the setup of the router.
I had not turned to them directly; they had been reading my postings on
this thread.
Regards,
Gisbert Auge
N.A.T. GmbH
Steve,
same here. Even medium designs won't route and end up with an unable to
initialise. Does anyone know a reason and workaround for this effect?
Regards,
Gisbert Auge
N.A.T. GmbH
Hi,
my use of Protel is
- Schematic yes
- PCB yes
- Powerprint no
- CAM Manager yes
- Simulator no
- Autorouter seldom
- 3D Viewer no
- PLD no
- Arrange Components no
- Autoplacer no, much worse than AR
- PCB Miter
Hi Tim,
we route large designs with SPECCTRA.
Gisbert Auge
N.A.T. GmbH
Tim Fifield
Ivan,
what buttons do you push, i.e. what rules did you find significant playing
around with? Just being curious ...
Regards,
Gisbert Auge
N.A.T. GmbH
Wow, thank you, Colin, I did not know about this feature, and it's smart.
Regards,
Gisbert Auge
N.A.T. GmbH
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works also fine in Protel.
G. Auge
Sean James
Don Ingram wrote:
I don't accept that the solution to this is to move to another product. We
have spent a hell of a lot of blood, sweat tears over the years while
trying to turn out a living with this product.
That is exactly it !!
Perhaps we should all buy some Altium shares and show up at
Hi Yuri,
it cannot be done. What you can do is define a bus like SIGNAL[1..10] and
place text strings on the wires showing the names originally wanted
(DATA1-8, CLK,GND). Be careful with adding power signals to a bus! This may
be a cause for serious trouble.
Regards,
Gisbert Auge
N.A.T. GmbH
***
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Engineering/Technical Placement Specialists
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***
Hello,
just another 2c: Try Mentor's Integra Work Station package, if
***
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Hi Brian,
this will not be of much help for you, but consider like
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Gordon,
there is (was?) a special offer in connection with an OrCAD
Hello aj,
in a recent post to PEDA you wrote
You simply add the discalimer that by sending ANY further email to your
address they have legally agreed to the terms in your following statement
(I'm not posting it unless someone really wants it as a template, in which
case send a private
Hi aj,
thank you for the text. I tried to answer you directly, but it bounced
again. Your server is refusing to accept mail to your address.
... while talking to mailhost.columbus.oh.ameritech.net.:
RCPT To:target address
550 you are not allowed to send mail to target address
550 target
Hi,
there seems to be a coincidence in receiving spam (with PEDA as subject !!)
and posting to this group. After I sent some posts during the last
fortnight, I received about half a dozen of spam mails, half of them from
.au servers, the rest from elsewhere. Someone seems to collect addresses
Hello Ivan.
tent the vias. You will most probably risk short under the BGA if you
don't. By the way, I never understood why many PCB designs come with open
vias, unless you want to use them as testpoints.
Regards,
Gisbert Auge
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To
Hi all,
is it possible to make global changes to the properties of a layer set in
Print/Preview? It is somewhat annoying to have to make changes to layer
settings 25 times for one set of layer definitions.
Regards,
Gisbert Auge
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*
I do the parts just as you describe, and it works fine. In detail:
- Place the 1st part (the one you completed already) on the screen
- Mark it by selecting the complete area and do Edit/Copy
- Click on a reference point
- Place the 2nd part on the screen ( button). This screen should still be
Hi Gordon,
could you possibly share your knowledge with the forum members? There are
more participants interested in this thread (like me :-) ).
TIA,
Gisbert Auge
N.A.T. GmbH
Jon Elson wrote:
Right, the CE requirement is that all electrical components must bear the
CE mark at the full accepted size (I think it is around 5 cm?). This
includes
EVERY component, including 0402 resistors! There are no exceptions
permitted, and any unit bearing even one such unlabeled or
Your description is more precise than mine. Thank you.
Gisbert
Heiko Vachek [EMAIL PROTECTED] on 09.08.2001 15:45:19
Please respond to Protel EDA Forum [EMAIL PROTECTED]
To: 'Protel EDA Forum' [EMAIL PROTECTED]
cc:
Subject: Re: [PEDA] Logo's for FCC, UL and CE ?
Not quite correct,
Thank you, Konrad, that's a nice work-around.
Gisbert Auge
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Hi,
I also think it works like Andrew describes, for instance as for my
experience. I came across this behaviour already in version 2.8, when I was
merging libraries from different developers. But, for normal working
situations why not organise libraries in a way, that there are no different
Hi,
I just noticed a bug which was new to me so far.
If you open Protel and click on the little minimize window button in the
upper right window corner while the files are loading, and then renew the
normal window size some time later, the entrance picture Design Explorer
99 SE does not close,
Hi all,
in the definition of the rule for Matched Net Length there is an item
called gap. Does anyone know what this is supposed to be and how to alter
it? In the respective properties window there is no such item.
Regards,
Gisbert
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Just another question in the same context.
Is it possible in SCH to do a global rename of net labels with all
different names, in order to add a letter to them?
Example: I want to rename signals ABC, DEF, GHI, ... to Z_ABC, Z_DEF,
Z_GHI, ..., without having to change every signal name manually.
We disregard it.
Gisbert
Coleman, Tim [EMAIL PROTECTED] on 09.03.2001 09:51:03
Please respond to Protel EDA Forum [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
cc:
Subject: Re: [PEDA] [PROTEL EDA USERS]: Database Linking...a suggested
improveme nt
Hi,
To answer your question:
Confirmed. I made the same experience when translating back from Specctra.
Gisbert
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I would suggest to drop
this feature completely. It is a relic from the times when a chip had a
power supply of 5V, and that was it.
Abd ul-Rahman wrote:
The feature remains almost as useful as it ever was. Further, it should be
considered that there is a huge base of legacy designs which
Hi Terry,
sorry, but I do not at all agree with you.
As for showing no connect pins - it is about as useful as adding a few
ficticious components to the schematic and marking them as not fitted and
nothing to do with the design?
These pins are not fictitious and have everything to do with the
Cadence runs a SPECCTRA forum under [EMAIL PROTECTED]
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Hello Ian,
stupid me. I get your point. Of course you are right. Sorry for not
thinking twice.
Regards,
Gisbert Auge
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