On Thursday 25 October 2018 15:45:37 Kenneth Lerman wrote: > I believe that issue Gene thinks needs addressing is the following: > Consider component A (say Jon's board) reads the hardware and produces > a signal Sa. > Component B reads Sa and produces Sb > Component C reads Sb and produces Sc > Component A (Jon's board again) reads Sc and writes to the hardware. > This can all take place in one servo cycle. > > However, what happens if the components are added (addf) in the order: > Component C, component B, Component A. > > In that case: > (cycle 1): Component C reads Sb (no value stored there yet) and > produces Sc-1. > Component B reads Sa (no value stored there yet) and > produces Sb-1. > Component A reads hardware and produces Sa-1. It reads > Sc-1 and writes the hardware. > (cycle 2): Component C reads Sb-1 and produces Sc-2 > Component B reads Sa-1 and produces Sb-2 > Component A reads hardware and produces Sa-2. It read > Sc-1 and writes the hardware. > (cycle 3): Component C reads Sb-2 and produces Sc-3 > Component B reads Sa-2 and produces Sb-3 > Component A reads hardware and produces Sa-3. It reads > Sc-2 and writes the hardware. > > Look at where the value written to the hardware came from. Sc-2 was > generated in cycle 2 from Sb-1. > Sb-1 was generated in cycle 1 from no value store there, but call it > cycle 0. > > So the value that is output in cycle 3 is essentially three cycles > old. > > If instead, the components were addf'd in the order A, B, C, the delay > would be > determined strictly by the processing time. > > I first saw this problem in the 1960s in the context of generating a > PERT chart. I later found out that solving it requires doing a > topological sort. There's a slight complication in that topological > sorts are done in DAGs (directed acyclic graphs) and our graph has > cycles where a single component can be both an input and an output. A > straightforward solution might be to arbitrarily break those > components into two parts. > > At any rate, Gene brings up a real problem should be solvable with a > simple tool. > > Ken >
I'm not so sure I'd call it simple, Ken, but we definitely do need such a tool. I don't think it would be fast, at least not on a hal file with 100 lines of addf's or more, and 2, maybe 3 threads. My Sheldon, running from a pi, has two threads, servo and jog, with jog running at only 200 hertz. I need to move all the slow threads to the bottom of the list, then re-sort each list to firmly achieve the correct, it all falls thru in one thread cycle order, and if it was carefully analyzed, theres likely a few items/modules that could be moved to the slower thread. The G0704 is all running on the 1KHz servo thread, but thats a much faster Intel dual core cpu, which isn't showing its overworked, yet... Its about to get independent homing switches which will add a few lines to the hal file as soon as I get good eyesight back. 2, maybe 3 weeks yet to new glasses. Now getting into the killing frost time of the year, snow by the foot or so, so some of this will slow down. The garage is very well insulated, heats all winter with a 1500 watt heater. but the shop only has a layer of T-111 between the weather and occupants like me. Been thinking of tearing it down and making a bigger one that can be insulated as its built, now that a damaged back in 2010 50 foot pine has been taken down at the other end of the yard. All I have to do is last long enough to do it. ;-) Thanks Ken. -- Cheers, Gene Heskett -- "There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order." -Ed Howdershelt (Author) Genes Web page <http://geneslinuxbox.net:6309/gene> _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
