I am issuing a branch entry form of  a macro, in the SRB 

So for the SRB control block 241,

For the SRB code 227

 Thank you for all your help



-----Original Message-----
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Chris Craddock
Sent: Monday, October 17, 2011 6:27 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA

On Mon, Oct 17, 2011 at 5:31 PM, Shmuel Metz (Seymour J.) <
shmuel+ibm-m...@patriot.net> wrote:

> In
> <cakxahqwwofk2cmeed1akporkeytzvz-_iq5pk1kmi3bb8fx...@mail.gmail.com>,
> on 10/17/2011
>    at 11:27 AM, Chris Craddock <crashlu...@gmail.com> said:
>
> >On the other hand; If you are trying to schedule an SRB into
> >-any-other- address space, then (somehow) you have to make sure
> >the code will be addressable when the SRB is dispatched. In
> >general that means loading it into common storage (technically it
> >should be in SQA rather than CSA, but that's a minor nit)
>
> Why? As long as the address is accessible and the code will be
> addressable, why can't it be private and pagable? MVS can handle a
> page fault in an SRB routine.
>
> Now, if you're going to schedule SRB's into multiple address spaces
> for the same routine, then you would want the code in common so that
> you only need a single copy.



If you can arrange ahead of time for the code to be loaded in the foreign
address space then of course it can be in private. I said as much. It is
also true that SRB's can take page faults, so the SRB code *can* be in
pageable storage... However, it is very desirable for the SRB to be able to
run through its processing without taking any unnecessary page faults. An
ordinary SRB dispatch is an extremely efficient mechanism, but if the SRB
subsequently interrupted and has to be suspended (e.g. for a page fault) the
system has quite a lot of work to do to save its state (SSRB, FRR stack,
linkage stack etc). It is still fast, but why take the hit? Kind of like the
old joke about Ferraris. She's a made a to go, not a to stop.



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