The e6500 core manual defines IVOR42 as the LRAT error interrupt offset register. U-Boot programs it during interrupt setup, but currently the QEMU e6500 IVOR mask currently excludes bit 42.
Include IVOR42 in the mask so the existing BookE SPR registration exposes its offset. This permits the register accesses without implementing LRAT translation or LRAT exception delivery. Reference: E6500RM (Rev.0), section 2.9.5 and 4.9.22 https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Signed-off-by: Bin Meng <[email protected]> --- target/ppc/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 4d12152659..5077f3300e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2824,7 +2824,7 @@ static void init_proc_e500(CPUPPCState *env, int version) ivor_mask = 0x000003FE0000FFFFULL; break; case fsl_e6500: - ivor_mask = 0x000003FF0000FFFFULL; + ivor_mask = 0x000007FF0000FFFFULL; break; } register_BookE_sprs(env, ivor_mask); -- 2.53.0
