The e500mc and e5500 manuals specify pseudo-LRU replacement, cache locking and parity detection for both L1 caches. The reset values describe the block size, associativity and capacity, but leave CREPL/ICREPL, CLA/ICLA and CPA/ICPA clear.
Set those fields to their documented values so both L1CFG0 and L1CFG1 reset to 0x00B83820, including the shared eight-way, 32 KiB cache geometry. Reference: - E500MCRM (Rev.3), section 2.14.4 and 2.14.5 https://www.nxp.com/docs/en/reference-manual/E500MCRM.pdf - E5500RM (Rev.4), section 2.14.4 and 2.14.5 https://www.nxp.com/webapp/Download?colCode=E5500RM Signed-off-by: Bin Meng <[email protected]> --- target/ppc/cpu_init.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 29f28be7e0..fec672a8a6 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2886,8 +2886,9 @@ static void init_proc_e500(CPUPPCState *env, int version) case fsl_e5500: env->dcache_line_size = 64; env->icache_line_size = 64; - l1cfg0 |= 0x00800000; /* 64 byte cache block size */ - l1cfg1 |= 0x00800000; /* 64 byte cache block size */ + /* 64 byte blocks, pseudo-LRU replacement, cache locking and parity */ + l1cfg0 |= 0x00B80000; + l1cfg1 |= 0x00B80000; break; case fsl_e6500: env->dcache_line_size = 64; -- 2.53.0
