The e500mc, e5500 and e6500 core manuals define MAS5 and MAS8 as SPRs 339 (0x153) and 341 (0x155). MAS5 supplies GS and LPID values for TLB searches and invalidations, while MAS8 holds guest-space and LPID context for TLB entries.
Register both alongside the other BookE MMU assist registers using the existing 32-bit SPR storage. Exclude e500v1 and e500v2, which do not implement MAS5 or MAS8. Reference: - E500MCRM (Rev.3), section 2.16.6.6 and 2.16.6.9 https://www.nxp.com/docs/en/reference-manual/E500MCRM.pdf - E5500RM (Rev.4), section 2.16.6.6 and 2.16.6.9 https://www.nxp.com/webapp/Download?colCode=E5500RM - E6500RM (Rev.0), section 2.13.10.6 and 2.13.10.9 https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Signed-off-by: Bin Meng <[email protected]> --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 498b505a96..9d3d27be91 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1931,6 +1931,7 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_BOOKE_MAS5 (0x153) #define SPR_BOOKE_TCR (0x154) #define SPR_PPE42_TCR (0x154) +#define SPR_BOOKE_MAS8 (0x155) #define SPR_BOOKE_TLB0PS (0x158) #define SPR_BOOKE_TLB1PS (0x159) #define SPR_BOOKE_TLB2PS (0x15A) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 21c6012fa1..032b8b606e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2901,6 +2901,14 @@ static void init_proc_e500(CPUPPCState *env, int version) env->spr[SPR_PVR]); } register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); + if (version != fsl_e500v1 && version != fsl_e500v2) { + spr_register(env, SPR_BOOKE_MAS5, "MAS5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic32, 0); + spr_register(env, SPR_BOOKE_MAS8, "MAS8", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic32, 0); + } register_usprgh_sprs(env); if (version != fsl_e500v1) { -- 2.53.0
