From: Philippe Mathieu-Daudé <[email protected]> Convert LI[16] and LI[48]. LI[16] decodes its 3-bit register with gpr3() and its immediate with s_eu() (0x7f encodes -1). LI[48] takes a 32-bit immediate and is not available in NMS cores; handle it in trans_LI_nnms(), which checks NMS before calling trans_LI(). Expose check_nms() for that purpose.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- Since v3: - Fix LI[16] register decoding, using the gpr3() mapping - Fix LI[16] immediate, extracted unsigned - Fix LI[48] immediate halfword order - Replace the not_in_nms argument by trans_LI_nnms() - Reuse check_nms() from translate.c --- target/mips/tcg/translate.h | 1 + target/mips/tcg/nanomips16.decode | 9 ++++++++ target/mips/tcg/nanomips48.decode | 8 ++++++++ target/mips/tcg/nanomips_translate.c | 26 ++++++++++++++++++++++++ target/mips/tcg/translate.c | 2 +- target/mips/tcg/nanomips_translate.c.inc | 17 ---------------- 6 files changed, 45 insertions(+), 18 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 71370f336dc1..0af9f2fb3603 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -152,6 +152,7 @@ void check_cp1_enabled(DisasContext *ctx); void check_cp1_64bitmode(DisasContext *ctx); void check_cp1_registers(DisasContext *ctx, int regs); void check_cop1x(DisasContext *ctx); +void check_nms(DisasContext *ctx); void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); void gen_base_index_addr(DisasContext *ctx, TCGv addr, int base, int index); diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode index f68fb57022a5..70db007e820b 100644 --- a/target/mips/tcg/nanomips16.decode +++ b/target/mips/tcg/nanomips16.decode @@ -6,3 +6,12 @@ # # Reference: nanoMIPS32 Instruction Set Technical Reference Manual # (Document Number: MD01247) + +&rd_imm rd imm + +%rt3 7:3 !function=gpr3 +%s_eu 0:7 !function=s_eu + +@rt3_s ...... ... ....... &rd_imm rd=%rt3 imm=%s_eu + +LI 110100 ... ....... @rt3_s # LI[16] diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode index 0ab33ce5a952..4c9fe695a869 100644 --- a/target/mips/tcg/nanomips48.decode +++ b/target/mips/tcg/nanomips48.decode @@ -6,3 +6,11 @@ # # Reference: nanoMIPS32 Instruction Set Technical Reference Manual # (Document Number: MD01247) + +&rd_imm rd imm !extern + +%imm 0:s16 16:16 + +@rd_imm ...... rd:5 ..... ................ ................ &rd_imm imm=%imm + +LI_nnms 011000 ..... 00000 ................ ................ @rd_imm diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c index 6b8aaedb5477..c9ef142fe73f 100644 --- a/target/mips/tcg/nanomips_translate.c +++ b/target/mips/tcg/nanomips_translate.c @@ -9,6 +9,18 @@ #include "qemu/osdep.h" #include "translate.h" +static int gpr3(DisasContext *ctx, int x) +{ + static const int map[8] = { 16, 17, 18, 19, 4, 5, 6, 7 }; + + return map[x]; +} + +static int s_eu(DisasContext *ctx, int x) +{ + return x == 0x7f ? -1 : x; +} + /* Include the auto-generated decoders. */ #include "decode-nanomips16.c.inc" #include "decode-nanomips32.c.inc" @@ -18,3 +30,17 @@ static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } + +static bool trans_LI(DisasContext *ctx, arg_rd_imm *a) +{ + gen_li(ctx, a->rd, a->imm); + + return true; +} + +static bool trans_LI_nnms(DisasContext *ctx, arg_rd_imm *a) +{ + check_nms(ctx); + + return trans_LI(ctx, a); +} diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 74c571c1c125..10811db827c9 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1712,7 +1712,7 @@ static inline void check_cp0_mt(DisasContext *ctx) * This code generates a "reserved instruction" exception if the * Config5 NMS bit is set. */ -static inline void check_nms(DisasContext *ctx) +void check_nms(DisasContext *ctx) { if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { gen_reserved_instruction(ctx); diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 028ef49ea053..c883b5514f1c 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -57,7 +57,6 @@ enum { NM_POOL32S = 0x30, NM_P_BRI = 0x32, - NM_LI16 = 0x34, NM_SWGP16 = 0x35, NM_P16_BR = 0x36, @@ -86,7 +85,6 @@ enum { /* P48I instruction pool */ enum { - NM_LI48 = 0x00, NM_ADDIU48 = 0x01, NM_ADDIUGP48 = 0x02, NM_ADDIUPC48 = 0x03, @@ -3665,12 +3663,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) mo_endian(ctx)); target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16; switch (extract32(ctx->opcode, 16, 5)) { - case NM_LI48: - check_nms(ctx); - if (rt != 0) { - tcg_gen_movi_tl(cpu_gpr[rt], addr_off); - } - break; case NM_ADDIU48: check_nms(ctx); if (rt != 0) { @@ -4628,15 +4620,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) break; } break; - case NM_LI16: - { - imm = extract32(ctx->opcode, 0, 7); - imm = (imm == 0x7f ? -1 : imm); - if (rt != 0) { - tcg_gen_movi_tl(cpu_gpr[rt], imm); - } - } - break; case NM_ANDI16: { uint32_t u = extract32(ctx->opcode, 0, 4); -- 2.55.0
