From: Philippe Mathieu-Daudé <[email protected]> Introduce the MIPS16e decodetree configs for the 16-bit and 32-bit instructions.
EXTEND-prefixed and JAL/JALX instructions are 32-bit, all others are 16-bit. Call the matching decoder, loading the second halfword only for 32-bit instructions. Unmatched opcodes fall back to the legacy decoder. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- Since v3: - Only call the 32-bit decoder for EXTEND-prefixed opcodes, loading the second halfword only then (rth) - Treat JAL/JALX as 32-bit instructions --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/mips16e_16.decode | 9 +++++++++ target/mips/tcg/mips16e_32.decode | 9 +++++++++ target/mips/tcg/mips16e_translate.c | 14 ++++++++++++++ target/mips/tcg/mips16e_translate.c.inc | 17 ++++++++++++++++- target/mips/tcg/meson.build | 3 +++ 6 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 target/mips/tcg/mips16e_16.decode create mode 100644 target/mips/tcg/mips16e_32.decode create mode 100644 target/mips/tcg/mips16e_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index ab2e21736741..98848d2fb90b 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -227,6 +227,8 @@ bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); +bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); +bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); bool decode_ext_loongson(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/mips16e_16.decode b/target/mips/tcg/mips16e_16.decode new file mode 100644 index 000000000000..2f3926052b9e --- /dev/null +++ b/target/mips/tcg/mips16e_16.decode @@ -0,0 +1,9 @@ +# MIPS16e 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: MIPS Architecture for Programmers, Volume IV-a +# The MIPS16e Application Specific Extension +# (Document Number: MD00076) diff --git a/target/mips/tcg/mips16e_32.decode b/target/mips/tcg/mips16e_32.decode new file mode 100644 index 000000000000..1dccb554fb56 --- /dev/null +++ b/target/mips/tcg/mips16e_32.decode @@ -0,0 +1,9 @@ +# MIPS16e 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: MIPS Architecture for Programmers, Volume IV-a +# The MIPS16e Application Specific Extension +# (Document Number: MD00076) diff --git a/target/mips/tcg/mips16e_translate.c b/target/mips/tcg/mips16e_translate.c new file mode 100644 index 000000000000..136468c65c71 --- /dev/null +++ b/target/mips/tcg/mips16e_translate.c @@ -0,0 +1,14 @@ +/* + * MIPS emulation for QEMU - MIPS16e translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-mips16e_16.c.inc" +#include "decode-mips16e_32.c.inc" diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index eb77326acf6b..dfb4312f1835 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -658,7 +658,22 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, mo_endian(ctx)); - op = (ctx->opcode >> 11) & 0x1f; + + op = extract32(ctx->opcode, 11, 5); + /* EXTEND-prefixed and JAL/JALX instructions are 32-bit */ + if (op == M16_OPC_EXTEND || op == M16_OPC_JAL) { + uint32_t opcode; + + opcode = ctx->opcode << 16; + opcode |= translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, + mo_endian(ctx)); + if (decode_ase_mips16e_32(ctx, opcode)) { + return 4; + } + } else if (decode_ase_mips16e_16(ctx, ctx->opcode)) { + return 2; + } + sa = (ctx->opcode >> 2) & 0x7; sa = sa == 0 ? 8 : sa; rx = xlat((ctx->opcode >> 8) & 0x7); diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 4ee359874aca..7715b029f90d 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,4 +1,6 @@ gen = [ + decodetree.process('mips16e_16.decode', extra_args: ['--decode=decode_ase_mips16e_16', '--insnwidth=16']), + decodetree.process('mips16e_32.decode', extra_args: ['--decode=decode_ase_mips16e_32']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), @@ -16,6 +18,7 @@ mips_ss.add(files( 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', + 'mips16e_translate.c', 'msa_helper.c', 'msa_translate.c', 'octeon_crypto.c', -- 2.55.0
