From: Philippe Mathieu-Daudé <[email protected]> Add empty decodetree files for the microMIPS 16-bit and 32-bit instructions, and micromips32_r6.decode for the 32-bit encodings only valid on Release 6.
Select the 16-bit or 32-bit decoder from the instruction size, loading the second halfword only for 32-bit instructions. The R6 decoder is only called on R6 CPUs, like decode_isa_rel6() in decode_opc(), so its patterns need no check_insn(ISA_MIPS_R6). Unmatched opcodes fall back to the legacy decoder. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- Since v3: - Select the decoder from the instruction size, instead of calling it from the delay slot check (rth) - Only load the second halfword for 32-bit instructions - Add micromips32_r6.decode, only called on R6 CPUs --- target/mips/tcg/translate.h | 3 +++ target/mips/tcg/micromips16.decode | 11 +++++++++++ target/mips/tcg/micromips32.decode | 11 +++++++++++ target/mips/tcg/micromips32_r6.decode | 11 +++++++++++ target/mips/tcg/micromips_translate.c | 15 +++++++++++++++ target/mips/tcg/micromips_translate.c.inc | 17 +++++++++++++++++ target/mips/tcg/meson.build | 4 ++++ 7 files changed, 72 insertions(+) create mode 100644 target/mips/tcg/micromips16.decode create mode 100644 target/mips/tcg/micromips32.decode create mode 100644 target/mips/tcg/micromips32_r6.decode create mode 100644 target/mips/tcg/micromips_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 98848d2fb90b..eea7e555153f 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -226,6 +226,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); bool decode_64bit_enabled(DisasContext *ctx); /* decodetree generated */ +bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); +bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn); +bool decode_isa_micromips32_r6(DisasContext *ctx, uint32_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/micromips16.decode b/target/mips/tcg/micromips16.decode new file mode 100644 index 000000000000..4b1f04299132 --- /dev/null +++ b/target/mips/tcg/micromips16.decode @@ -0,0 +1,11 @@ +# microMIPS32 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: MIPS Architecture for Programmers, Volume II-B +# microMIPS32 Instruction Set +# (Document Number: MD00582) +# microMIPS64 Instruction Set +# (Document Number: MD00594) diff --git a/target/mips/tcg/micromips32.decode b/target/mips/tcg/micromips32.decode new file mode 100644 index 000000000000..d7668181a100 --- /dev/null +++ b/target/mips/tcg/micromips32.decode @@ -0,0 +1,11 @@ +# microMIPS32 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: MIPS Architecture for Programmers, Volume II-B +# microMIPS32 Instruction Set +# (Document Number: MD00582) +# microMIPS64 Instruction Set +# (Document Number: MD00594) diff --git a/target/mips/tcg/micromips32_r6.decode b/target/mips/tcg/micromips32_r6.decode new file mode 100644 index 000000000000..5786947c7c96 --- /dev/null +++ b/target/mips/tcg/micromips32_r6.decode @@ -0,0 +1,11 @@ +# microMIPS32 Release 6 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: MIPS Architecture for Programmers, Volume II-B +# microMIPS32 Instruction Set +# (Document Number: MD00582) +# microMIPS64 Instruction Set +# (Document Number: MD00594) diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c new file mode 100644 index 000000000000..b30c0119996c --- /dev/null +++ b/target/mips/tcg/micromips_translate.c @@ -0,0 +1,15 @@ +/* + * MIPS emulation for QEMU - microMIPS translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-micromips16.c.inc" +#include "decode-micromips32.c.inc" +#include "decode-micromips32_r6.c.inc" diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 40ffb1a71d30..7528591b1ab4 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -3026,6 +3026,23 @@ static int decode_isa_micromips(CPUMIPSState *env, DisasContext *ctx) return 2; } + if (is_16bit) { + if (decode_isa_micromips16(ctx, opcode)) { + return 2; + } + } else { + opcode <<= 16; + opcode |= translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, + mo_endian(ctx)); + if (cpu_supports_isa(env, ISA_MIPS_R6) + && decode_isa_micromips32_r6(ctx, opcode)) { + return 4; + } + if (decode_isa_micromips32(ctx, opcode)) { + return 4; + } + } + switch (op) { case POOL16A: { diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index 7715b029f90d..d7ae95b70f56 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,6 +1,9 @@ gen = [ decodetree.process('mips16e_16.decode', extra_args: ['--decode=decode_ase_mips16e_16', '--insnwidth=16']), decodetree.process('mips16e_32.decode', extra_args: ['--decode=decode_ase_mips16e_32']), + decodetree.process('micromips16.decode', extra_args: ['--decode=decode_isa_micromips16', '--insnwidth=16']), + decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']), + decodetree.process('micromips32_r6.decode', extra_args: ['--decode=decode_isa_micromips32_r6']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), @@ -18,6 +21,7 @@ mips_ss.add(files( 'fpu_helper.c', 'ldst_helper.c', 'lmmi_helper.c', + 'micromips_translate.c', 'mips16e_translate.c', 'msa_helper.c', 'msa_translate.c', -- 2.55.0
