From: Philippe Mathieu-Daudé <[email protected]> Call the generic gen_lsa(), using plus_1() to add 1 to the shift amount. LSA is a Release 6 instruction: add it to micromips32_r6.decode, which is only called on R6 CPUs.
The legacy decoder only matched bits [5:0]; the pattern also requires bits [8:6] to be zero, as specified. Other encodings now raise a Reserved Instruction exception. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- Since v3: - Move LSA to micromips32_r6.decode; v2 accepted it on pre-R6 microMIPS CPUs - plus_1() no longer declared inline --- target/mips/tcg/micromips32_r6.decode | 8 ++++++++ target/mips/tcg/micromips_translate.c | 10 ++++++++++ target/mips/tcg/micromips_translate.c.inc | 5 ----- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/micromips32_r6.decode b/target/mips/tcg/micromips32_r6.decode index 5786947c7c96..35f7afe53bd2 100644 --- a/target/mips/tcg/micromips32_r6.decode +++ b/target/mips/tcg/micromips32_r6.decode @@ -9,3 +9,11 @@ # (Document Number: MD00582) # microMIPS64 Instruction Set # (Document Number: MD00594) + +&r rs rt rd sa + +%lsa_sa 9:2 !function=plus_1 + +@lsa ...... rt:5 rs:5 rd:5 .. ... ...... &r sa=%lsa_sa + +LSA 000000 ..... ..... ..... .. 000 001111 @lsa diff --git a/target/mips/tcg/micromips_translate.c b/target/mips/tcg/micromips_translate.c index b30c0119996c..2a2b5aaa4530 100644 --- a/target/mips/tcg/micromips_translate.c +++ b/target/mips/tcg/micromips_translate.c @@ -9,7 +9,17 @@ #include "qemu/osdep.h" #include "translate.h" +static int plus_1(DisasContext *ctx, int x) +{ + return x + 1; +} + /* Include the auto-generated decoders. */ #include "decode-micromips16.c.inc" #include "decode-micromips32.c.inc" #include "decode-micromips32_r6.c.inc" + +static bool trans_LSA(DisasContext *ctx, arg_r *a) +{ + return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); +} diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index 7528591b1ab4..6eb8e79ec57b 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -191,7 +191,6 @@ enum { /* The following can be distinguished by their lower 6 bits. */ BREAK32 = 0x07, INS = 0x0c, - LSA = 0x0f, ALIGN = 0x1f, EXT = 0x2c, POOL32AXF = 0x3c, @@ -1799,10 +1798,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) case INS: gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); return; - case LSA: - check_insn(ctx, ISA_MIPS_R6); - gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) + 1); - break; case ALIGN: check_insn(ctx, ISA_MIPS_R6); gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); -- 2.55.0
