From: Philippe Mathieu-Daudé <[email protected]> Add empty decodetree files for the nanoMIPS 16-bit, 32-bit and 48-bit instructions.
The instruction size is known from the first halfword: 16-bit major opcodes have bit 12 set, and the P48I major opcode is the only 48-bit one. Call the matching decoder, reading only the halfwords needed. Unmatched opcodes fall back to the legacy decoder. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Aleksandar Rikalo <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- Since v3: - Select the decoder from the instruction size, reading only the halfwords needed (rth) --- target/mips/tcg/translate.h | 3 +++ target/mips/tcg/nanomips16.decode | 8 ++++++++ target/mips/tcg/nanomips32.decode | 8 ++++++++ target/mips/tcg/nanomips48.decode | 8 ++++++++ target/mips/tcg/nanomips_translate.c | 15 +++++++++++++++ target/mips/tcg/nanomips_translate.c.inc | 22 ++++++++++++++++++++++ target/mips/tcg/meson.build | 4 ++++ 7 files changed, 68 insertions(+) create mode 100644 target/mips/tcg/nanomips16.decode create mode 100644 target/mips/tcg/nanomips32.decode create mode 100644 target/mips/tcg/nanomips48.decode create mode 100644 target/mips/tcg/nanomips_translate.c diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index eea7e555153f..d11b2f32f009 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -229,6 +229,9 @@ bool decode_64bit_enabled(DisasContext *ctx); bool decode_isa_micromips16(DisasContext *ctx, uint16_t insn); bool decode_isa_micromips32(DisasContext *ctx, uint32_t insn); bool decode_isa_micromips32_r6(DisasContext *ctx, uint32_t insn); +bool decode_isa_nanomips16(DisasContext *ctx, uint16_t insn); +bool decode_isa_nanomips32(DisasContext *ctx, uint32_t insn); +bool decode_isa_nanomips48(DisasContext *ctx, uint64_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_mips16e_16(DisasContext *ctx, uint16_t insn); bool decode_ase_mips16e_32(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/tcg/nanomips16.decode b/target/mips/tcg/nanomips16.decode new file mode 100644 index 000000000000..f68fb57022a5 --- /dev/null +++ b/target/mips/tcg/nanomips16.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 16-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips32.decode b/target/mips/tcg/nanomips32.decode new file mode 100644 index 000000000000..2127c57444e6 --- /dev/null +++ b/target/mips/tcg/nanomips32.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 32-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips48.decode b/target/mips/tcg/nanomips48.decode new file mode 100644 index 000000000000..0ab33ce5a952 --- /dev/null +++ b/target/mips/tcg/nanomips48.decode @@ -0,0 +1,8 @@ +# nanoMIPS32 48-bit instruction set extensions +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Reference: nanoMIPS32 Instruction Set Technical Reference Manual +# (Document Number: MD01247) diff --git a/target/mips/tcg/nanomips_translate.c b/target/mips/tcg/nanomips_translate.c new file mode 100644 index 000000000000..9393257612aa --- /dev/null +++ b/target/mips/tcg/nanomips_translate.c @@ -0,0 +1,15 @@ +/* + * MIPS emulation for QEMU - nanoMIPS translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +/* Include the auto-generated decoders. */ +#include "decode-nanomips16.c.inc" +#include "decode-nanomips32.c.inc" +#include "decode-nanomips48.c.inc" diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index 421f26a192cb..6f6b5f190c9a 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -4482,6 +4482,28 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next, mo_endian(ctx)); ctx->opcode = opcode; + if (extract32(opcode, 12, 1)) { + /* Major opcodes with bit 2 set are 16-bit */ + if (decode_isa_nanomips16(ctx, opcode)) { + return 2; + } + } else { + opcode <<= 16; + opcode |= translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, + mo_endian(ctx)); + if (extract32(opcode, 26, 6) == NM_P48I) { + opcode <<= 16; + opcode |= translator_lduw_end(env, &ctx->base, + ctx->base.pc_next + 4, + mo_endian(ctx)); + if (decode_isa_nanomips48(ctx, opcode)) { + return 6; + } + } else if (decode_isa_nanomips32(ctx, opcode)) { + return 4; + } + } + rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode)); rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode)); rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode)); diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index d7ae95b70f56..644ca85f6390 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -5,6 +5,9 @@ gen = [ decodetree.process('micromips32.decode', extra_args: ['--decode=decode_isa_micromips32']), decodetree.process('micromips32_r6.decode', extra_args: ['--decode=decode_isa_micromips32_r6']), decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']), + decodetree.process('nanomips16.decode', extra_args: ['--decode=decode_isa_nanomips16', '--insnwidth=16']), + decodetree.process('nanomips32.decode', extra_args: ['--decode=decode_isa_nanomips32']), + decodetree.process('nanomips48.decode', extra_args: ['--decode=decode_isa_nanomips48', '--insnwidth=48']), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), @@ -25,6 +28,7 @@ mips_ss.add(files( 'mips16e_translate.c', 'msa_helper.c', 'msa_translate.c', + 'nanomips_translate.c', 'octeon_crypto.c', 'op_helper.c', 'rel6_translate.c', -- 2.55.0
