gEDA-user: EDIF: Found some ancient books. Any use to you?
I discovered a box of books that never got unpacked after the last rearrangement of my home office. Among these, I found several EDIF-related books. Since I long ago stopped giving a rat's rear end about EDIF, I offer them to the group. I'm guessing I could stuff them into a USPS flat-rate mailer and get them about anywhere in the USA for about US$8.00 -- not sure about cheap international shipping options. You can have them for the cost of shipping. These books are about 20 years old, so to the extent EDIF has evolved since 2.0.0, YMMV. I don't follow EDIF any more, in fact I will run quickly in the other direction at it's mere mention, so I can't comment on their actual utility today. Contact me off-list if you want to save these from the fireplace. EIA-584: Electronic Design Interchange Format Version 2 0 0 EIA EDIF/AG-1: Applications Guide: Using EDIF 2 0 0 For Schematic Transfer EDIF Question and Answers Volumes I,II,III, and IV, Prepared for the Design Automation Conference 1991 EIA/EDIF-1 Introduction to EDIF, Vol 1 EIA/EDIF-2 Introduction to EDIF, Vol 2 -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Oct 11, 2010, at 1:43 PM, Stefan Salewski wrote: -- may long default to 64 bit on 64 bit systems A well, that depends on the programming model that the system developers chose. 64 bit systems have been done two ways: LP64 or ILP64, that is longs and pointers are 64, ints are 32 or ints, longs, and pointers are 64. On a 64 bit systems, pointers are going to be 64 bits -- after all, that is why you are going to 64 bits. The C spec says longs shall be big enough to hold a pointer so that you can cast pointers and longs, and can union pointers and longs. The debate of what to do about ints can go on for years (... trust me I've been there) If you make ints default to 64 bits, all of a sudden recompiled programs get much larger, and the cache pressure is much higher, all for no good reason. If you make ints default to 32 bits, beelyuns of badly coded programs that expect to cast pointers to ints or do other sloppy things that work in an ILP32 world break right and left. So... w.r.t. the debate about pcb going to 64 bits instead of 32 bits is going to make the memory footprint much bigger (not a big deal) and the cache footprint much bigger (could be a big deal). TL;DR: It varies. Check for your system and compilers. -dave -- may it be better to use long long on 32 bit machines to enforce there 64 bit (emulation) when 64 bit is desired? Sorry, I should better be quiet. http://en.wikipedia.org/wiki/Long_integer ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GNUduino - Arduino made with gEDA
Good on you. It really gripes me when open hardware projects use something like Eagle for the schematic/pcb flow. The current object of my derision for doing that is the RepRap foundation. Today there are at least two reasonable choices for open source schematic and pcb design -- why do open hardware projects go with closed-source tool flows? I boggle. -dave On Oct 8, 2010, at 9:56 PM, jeffrey antony wrote: Hello all, I have designed a board named GNUduino ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GNUduino - Arduino made with gEDA
On Oct 9, 2010, at 10:28 AM, Kevin Vermeer wrote: What can we do to gEDA to make it more accessible to these folks? IMHO, the OP is on the right track. It will take less energy and time to simply fork the designs and push them out to a public repo than to lobby with the originators. I suspect the old issue of libraries is a barrier to the project originators, but by having us (who ever *we are) do the fork and gEDA conversion, we at least must solve the library issues for that one design. After a while, either the open-CAD version will become popular and the project originators will be dragged to open-CAD by their customers, or else it won't. If it doesn't, we need to examine why. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GNUduino - Arduino made with gEDA
KiCAD -- I haven't tried it myself, so I don't know much about it's capabilities. -dave On Oct 9, 2010, at 3:48 PM, Rick Collins wrote: I assume one is gEDA... what is the other? Rick At 01:56 AM 10/9/2010, you wrote: Good on you. It really gripes me when open hardware projects use something like Eagle for the schematic/pcb flow. The current object of my derision for doing that is the RepRap foundation. Today there are at least two reasonable choices for open source schematic and pcb design -- why do open hardware projects go with closed-source tool flows? I boggle. -dave On Oct 8, 2010, at 9:56 PM, jeffrey antony wrote: Hello all, I have designed a board named GNUduino ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: other FOSS layout tools
On Oct 9, 2010, at 6:44 PM, John Griessen wrote: On 10/09/2010 08:14 PM, Dave N6NZ wrote: KiCAD -- I haven't tried it myself, so I don't know much about it's capabilities. When I first looked at it a couple of years ago it was a small group, but now it seems to have critical mass -- about 12 developers. It's a integrated-through-GUI kind of program, but has some kind of scripting possible. I've not run it but for a few minutes -- please try it and tell us what it's like. One of the other guys in the robot club is giving KiCAD some mileage. I'll try to get some information out of him. Although, he is a bit distracted at the moment because he is cleaning out his garage to make room to take delivery of one of these... http://www.mikinimech.com/1610L.html -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb for kitchens (was: Re: pcb crooked traces)
On Oct 8, 2010, at 8:57 AM, Levente Kovacs wrote: On Fri, 08 Oct 2010 10:31:10 -0400 Rick Collins gnuarm.2...@arius.com wrote: Personally, I can't imagine a PCB larger than 2 meters much less 4 meters. Or is the possibility of uses other than PCB design being considered here? I ended up designing my kitchen layout using PCB. I started with QCAD, gave a try for SweetHome (for java), and IKEA's tool. I realised that PCB was good for the job. ?? Wow. I use QCad a lot, so I've climbed the considerable learning curve, but designing a kitchen is something where I would definitely choose QCad over pcb. pcb is great for... pcbs... who'da thunk it? But if I'm doing something that is going to be fab'ed in my wood shop on a CNC tool, QCad is a better fit. I admit that QCad's UI takes some work to learn, but fundamentally it is very well done and once you learn a few tricks you can really fly with it. All that said, QCad is a 2D tool, and for architectural design a 3D tool is going to be better, assuming it is complete enough. -dave Levente ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Oct 8, 2010, at 8:57 AM, Levente Kovacs wrote: On Fri, 08 Oct 2010 10:31:10 -0400 Rick Collins gnuarm.2...@arius.com wrote: Personally, I can't imagine a PCB larger than 2 meters much less 4 meters. Or is the possibility of uses other than PCB design being considered here? FYI -- the largest dimension I ever did on a board was 54 inches. The board was 54 x 5 inches. It was a specialized back-plane board. As I recall (this was in the 1980's) the 54 limit was determined by the maximum panel size of our vendor. The actual raw pcb panel was a little larger, but 54 inches allowed appropriate margins. Even as it was, the board was odd-ball enough that we had to hunt for a vendor that actually wanted the business (of course, it was a controlled-impedance board also, so it had some other unusual specification in addition). I couldn't say what the standard panel sizes are in the industry, but I could make an effort to find out. Of course, that could grow over time, but somehow I don't think a 4m x 4m board is likely even in the long term. IMHO, pcb design decisions should be based around making pcb a good tool for designing pcb's... if people find other uses or it, OK fine, but don't drive design decisions around odd-ball uses. There are other tools for mechanical CAD, architectural, etc. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Oct 8, 2010, at 12:42 PM, Andrew Miner wrote: For flexible PCBs which are made on roll to roll machinery, Good point, I forgot that a few months ago I saw some of these at a show. The vendor said you could do printed circuits 8 inches wide by arbitrarily long. Nice flex boards, too. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Oct 8, 2010, at 10:27 AM, Dave N6NZ wrote: I couldn't say what the standard panel sizes are in the industry, but I could make an effort to find out. FWIW, A quick poll of my friends indicates that 18x24 inches seems to be a standard panel size, but 48 x 22 inch boards used to be common in telecom, fabbed on 48 x 48 inch panels. A friend at Cisco says they regularly do 16x26 inch backplanes now. (and 14x21 inch 14 layer (!) boards that's a lot of layers in 21 inches. When I was at Amdahl, we did boards with 50 signal layers (and 12 or so power layers) but that was a smaller board, and we weren't trying to build thousands of them) Max size seems to vary a lot depending on the fab's equipment. I think the fab house that did my 54 inch board in the 1980's used panels around 60 inches long. So... if pcb were to be limited to a 2 meter by 2 meter board, would it actually be a painful limitation to anyone? Now that I think of it, my 54 inch board had to be done in two pieces because of the CAD software... but it was easy to line up the pieces because it was all transmission lines crossing the middle, and so vendor somehow got his photoplotter to paint left and right half files on the film with good registration. I also had an adventurous tech working for me who enjoyed challenges...) -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
On Oct 7, 2010, at 7:50 AM, Stefan Salewski wrote: On Thu, 2010-10-07 at 22:29 +0800, Steven Michalske wrote: I cannot get rid of the jagged diagonal lines on my design. There's lots of them. The picture shows a couple of examples. I've tried different grid sizes, line widths, but nothing fixes the problem. Redrawing them in order to eliminate any sections does not help. On PCB, it shows at some zoom levels but not others. It is in the gerbers as well and it is in the photo-mode picture I attached. Another thought, When I am laying out mixed pitch mm vs mil parts, I often leave the grid at a comfortable 10 or 25 mil setting. Turn on snaps to pins and pads. Then I largly ignore the grid. What I am saying here is that I Use the grid as a guideline. So to accomplish this I draw from the off grid pin out to the pcb and let the 45degree tail end on the grid. then off to the rest of the layout, on grid. When that tail is not quite correct, while drawing I use the u key to undo the 45 degree tail, this leaves the off grid stub that i can continue drawing from. Having a small grid usuially allows me to make a messier layout. Fine description, maybe such a text should be part of a beginner tutorial. If these things don't help then we have a bug. Sure, we had bugs, and maybe some are still alive. 8 mil traces with 8 mil clearance can be a problem due to arithmetic errors, 8 may be rounded up to next grid position, which is 9 with 1 mil grid. (I would use 8 mil traces, 8 mil grid and 7.9mil clearance to prevent problems) And we had the problem of 0.01 mil traces due to arithmetic errors when mm units are used. I guess the step to nm base units in PCB is still on the todo list. I've had perfectly explainable jaggies that occur when I am routing parallel traces. The 2nd through Nth traces of a parallel group can be pushed up against the previous traces as close as min-space, and therefore end up off-grid. This is great for routing density, but leads to a little weirdness when breaking them out again. One sources of jaggies occurs when I form a straight track with two or more segments, one that is off-grid and the new one on. Also snap to center of pad is often off-grid for TQFP's, etc, so that is another source of geometric oddities. I've never had a jaggie that wasn't a PEBKAC, or that couldn't be fixed by a little bit of careful editing. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: physicists (Re: new footprint guidelines)
I think a lot of people confuse the difference between a theoretical physicist and an experimental physicist. A theoretical uses a whiteboard and marker. He/She writes a paper. An experimental physicist reads the paper and goes -- Oh, really?. He/She constructs experimental apparatus using scrap metal, some custom glassware from the chemistry department glass blowing shop, an expensive sensor robbed off of last year's project, a chunk of stainless steel turned on a lathe by his/her own hands, some computer software, a little liquid nitrogen, and of course duct tape. He/She writes another paper. The theoretical reads the second paper and has one of two reactions: a) I told you so. b) Well, that sucks. -dave (an EE with physicist friends) On Oct 6, 2010, at 10:22 AM, John Doty wrote: On Oct 1, 2010, at 3:55 PM, Rick Collins wrote: Oh, I almost forgot, NEVER ask a PhD anything to design PCBs. What the heck are you thinking??? Speaking as a physicist, let me comment. 1. Learning to do a variety of engineering tasks is an important part of an experimental physicist's education. A good experimental physicist must be a more versatile engineer than most engineering specialists. This is exactly the kind of job a Ph.D. student *should* be doing. 2. The specific problem mentioned was a super noiseless detector circuit. Few EE's understand detector physics or noise physics well enough to tackle this. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GPLv3 question
On Oct 6, 2010, at 1:01 PM, DJ Delorie wrote: You don't need to deliver *any* source code unless it is requested by the user. In the case of an embedded product, with GPLv3, the *only* way to not include the source is to include the written offer, which opens you up for a DDNS. You can only use the web download option if the binary is itself web downloaded. ?? OK, I admit I haven't read the GPLv3 that carefully yet. Is it because it ships as a physical good that the written offer must be physically realized? Does a silk screen of: For sources: ftp://foo.org/public/sources/wonderwidget.tgz; comply with the written offer clause? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: GPLv3 question
On Oct 6, 2010, at 3:20 PM, Geoff Swan wrote: So just to clarify - if you distribute an embedded device that runs a GPLv3 binary; to comply with the GPLv3 you must not only provide the source, but also a hardware-programmer/uploader? I suppose in most cases this isn't necessarily a huge issue - where firmware upgrade capability is built into the device (such as most routers, and development style boards). I play with the Atmel AVR range a fair bit and typically only create boards that require a separate hardware programmer to upload firmware. In this case to distribute such a board with GPLv3 firmware I would technically need to provide the in-circuit-programmer with the board and source. IANAL, but that is not my interpretation. Certainly, GPLv3 precludes you from making it impossible to update the software by requiring secret keys and such. But I always thought you were in compliance as long as you provided all source, and that someone with the skills and easily available tools could reprogram the device. I don't even see the necessity of providing the standard ISP or JTAG connector as long as the nets are exposed and you can clip into them with an octopus pod on a JTAG ICE, you are in compliance, although it won't win you many friends. After all, if you write an open source pcb design package, you don't have to ship a color monitor with it to be in compliance with the GPL, the user can provide his own. The user can provide his own AVRISP clone just as well. -dave I could imagine in some cases the uC may be programmed *before* it is soldered in place and no mechanism provided by the circuit for firmware modification. In this case I presume you would not be able to make use of GPLv3 firmware - as no mechinism is readily available to modify the firmware... I know these are perhaps somewhat unrealistic scenarios - but if I have understood them correctly it certainly seems that GPLv3 could have been a little more embedded platform friendly. cheers, Geoff On Thu, Oct 7, 2010 at 7:01 AM, DJ Delorie d...@delorie.com wrote: You don't need to deliver *any* source code unless it is requested by the user. In the case of an embedded product, with GPLv3, the *only* way to not include the source is to include the written offer, which opens you up for a DDNS. You can only use the web download option if the binary is itself web downloaded. Also - for embedded products, to comply with GPLv3 you must enable the user to change the code *in the device*. Just providing source code isn't enough unless they can use it too. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: kicad/gerbview vs. pcb/gerbv: interpretation of Circular Interpolation
Yeah. I can't imagine a modern photo plotter having trouble with it. In CNC code, doing a circle cut in arc segments is considered 'good practice' by some, since a machine controller will only pause between lines of G-code. If a circle is done as quadrants, then if something goes wacky you can pause the machine between quadrants. Otherwise your only option is the E-stop button, where you lose position and probably the work piece also. Not an issue for photo plotters. Maybe that is where the bug report originated? Somebody commenting on G-code 'best practices'? (Which I agree don't necessarily apply to gerbers...) -dave On Aug 31, 2010, at 1:02 PM, DJ Delorie wrote: PCB uses the G02/G03 codes that way too. My point was, if RS274X has a way to differentiate between 135 degree arcs and 225 degree arcs, that same way should work for 315 vs 45. I suspect the one-quadrant format is ancient, and people added the multi-quadrant format to fix and replace it, but never deprecated the older one. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: kicad/gerbview vs. pcb/gerbv: interpretation of Circular Interpolation
On Aug 31, 2010, at 10:32 AM, DJ Delorie wrote: That all depends on what the software says the difference is. I can see those being very different things. One is an arc that is less than half a circle and the other an arc that is more than half a circle. But if the software interprets all of these as being less than half a circle, then they are the same. I meant the difference in G-codes :-) Ah! A *technical* question... Well, in regular G-code G02 or G03 says clockwise/counter-clockwise arc interpolation, given X,Y, and some combination of I,J,K,R parameters. I presume RS-274X works the same way, but I honestly only look closely at milling machine CNC code these days. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf and PCB on OS X
On Aug 14, 2010, at 2:16 PM, John Doty wrote: The only real problem with Fink is that it gets itself tied in knots occasionally. Every couple of years, I have to rm -rf /sw and reinstall the whole thing. The only *other* problem with Fink is that is doesn't always play well with MacPorts. For my part, I pretend Fink doesn't exist. I use MacPorts, which is very much like the BSD ports system, or simply build from a source tarball. OS X is BSD underneath, after all, and for the most part Apple hasn't h0rk3d it up too badly. gEDA runs swell on OS X. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Commercial CAD, land pattern generators report
On Aug 12, 2010, at 7:17 AM, John Griessen wrote: certain 3D entities are *not* documented, they are binary blobs and you can only get the spec by paying for a license from Autocad and signing an NDA. So no open source dxf library will ever be able to handle all of dxf. My immediate goal is to write a library that can make sense of all 2D information in a complete and coherent way, provide a Pythonic interface for reading and writing dxf, and gracefully ignore or perhaps read-and-blobify anything it doesn't understand without crashing or hanging. Sounds good. Does the blobify function you imagine get the physical max boundaries of the unknown correct? My near-term goals are pretty limited. Beyond processing 2D intelligently and presenting a clean object-oriented interface to 2D entities, my goals are simply to not choke, and to gather information for a single entity all into one place, without trying to process intelligently -- more of a here it is if you know what to do with it. I know someone else working on getting 3D usable by FOSS tools by way of a common open format available as a standard or defacto standard. In electronics it seems defacto standards are better than official ones, so... He's looking at Rhino's OpenNurbs definitions in c++. OpenNurbs.org has the code, public domain. He's considering forking and licensing it GPL. I've been watching FOSS 3D CAD for a while, and until FreeCAD came along the outlook was pretty depressing. The FreeCAD guys, however, are making progress a bullet-train speed. My first instinct would be to find a way to help them. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Commercial CAD, land pattern generators report
On Aug 13, 2010, at 12:51 PM, Felipe De la Puente Christen wrote: On Fri, 2010-08-13 at 11:21 -0700, Dave N6NZ wrote: I've been watching FOSS 3D CAD for a while, and until FreeCAD came along the outlook was pretty depressing. The FreeCAD guys, however, are making progress a bullet-train speed. My first instinct would be to find a way to help them. -dave snip According to my Aerspace related partners, DXF has almost nothing to apport to 3D CAD. Yes, well, I can't imagine using dxf for any serious 3D work. But it does have 3D entities in the file format. My earlier comments w.r.t. a dxf i/o library reflect both of those statements. :) I don't know much about 3D file formats. I know stl is basically a bag of triangles, and I think stl is also. So while you can communicate a hull, you can't do much more. No parametric information, no material information, no joint information, etc. Not sure about iges, I know pretty much nothing about it. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Commercial CAD, land pattern generators report
On Aug 11, 2010, at 12:28 PM, John Griessen wrote; What's a good reference about DXF? Arghhh... I've spent a bit of time trying to read .dxf correctly. My first shot was for reading .dxf to drive a simple laser cutter that used bastardized HP/GL. I did an ad hoc parser in C after reading Autocad's online documentation, and only attempted to pull out the fraction of the information that interested me. Let's just say I recommend against that approach. ;) My next version of the laser cutter CAM used the Ribbonsoft's dxflib (GPL). dxflib is C++ and is actually a pretty reasonable interface for reading dxf and is very robust. Writing dxf with it requires a pretty good knowledge of the structure of dxf, but reading is straightforward. About that... the structure of dxf... Imagine a design committee consisting entirely of passive-aggressive, 'B' ark chimpanzees that were only convinced to join the project for the meeting donuts. Now imagine the file format they would specify. Now imagine that file format evolved to support things that were never originally intended. That is dxf. I am now working on a new project -- with the intent of reading 2D dxf and producing real, proper, good-to-go, CNC machine g-code that doesn't crash the milling machine or break tools. Wish me luck. (Or volunteer to help??? :) Anyway, I'm doing the project in Python, and after looking for a good dxf reader in Python, briefly considered putting a Python wrapper around dxflib. But that is not a great fit... it's hard to make a Pythonic interface to dxf around dxflib. So... I decided to commit the cardinal sin of all programmers, writing my own library... I can get away with that since there is no one to fire me for such a silly decision. And now I finally get to the point of this rambling e-mail. Since what I want is 100% interoperability with QCad (from Ribbonsoft, uses dxflib for file I/O), I concluded that reading the dxflib code very carefully is about the best dxf file documentation that is around. Autodesk has a lot of online documentation of the file format, and that is indispensable. dxf comes in several versions, and each is documented separately. The documentation that exists on the Autocad web site is reasonably well organized once you learn to navigate it. Be aware, however, that certain 3D entities are *not* documented, they are binary blobs and you can only get the spec by paying for a license from Autocad and signing an NDA. So no open source dxf library will ever be able to handle all of dxf. My immediate goal is to write a library that can make sense of all 2D information in a complete and coherent way, provide a Pythonic interface for reading and writing dxf, and gracefully ignore or perhaps read-and-blobify anything it doesn't understand without crashing or hanging. The not-crashing-and-hanging part will put it ahead of at least some commercial alternatives. HTH If you are interested in talking about my Python dxf I/O lib we should take that off-list. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gschem/PCB: how to deal with special pins pads?
On Jul 21, 2010, at 1:03 PM, Richard Rasker wrote: Hello, I'm a happy GSchem + PCB user for quite a few years now, but I'm still puzzled about one aspect of defining symbols and footprints, and that is special pins and pads. With special I mean the following types of pins/pads: - Internally connected pins and pads, e.g. SO8 MOSFETs with S on pins 1-3, G on pin 4, and D on pins 5-8. I can of course create a GSchem symbol with 3 pins for S and 4 pins for D, but is there a more elegant way in GSchem to deal with this? Well, I'm not saying this is more elegant, but it is different: You can create a copy of the SO8 footprint where the S pins all have the same pin number, and the D pins all have the same pin number. It keeps the gschem symbol looking 'normal'. - So-called don't care pins and pads, e.g. mounting pads for SMD connectors. I found that I can at least connect these to each other when I give them all pin number 0 (zero), but I can't connect these to any net (e.g. Gnd) in the circuit without the DRC check crying foul. Is there a way to define these pads in such a way that PCB doesn't care to which net each one is connected? In every case I've had in my own design so far, these pads are all connected to ground anyway, so I just give these pads the same pad number as the ground pin. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Gschem/PCB: how to deal with special pins pads?
On Jul 21, 2010, at 1:35 PM, DJ Delorie wrote: - So-called don't care pins and pads, e.g. mounting pads for SMD connectors. I name them M1 through M4 for example, and if you want to connect them to something, yeah, they need to be in the netlist. I'm not sure if DRC ignores them if they don't *have* a name, though. In my symbol library, I usually split parts into a functional symbol and an infrastructure symbol (power and ground, and similar), so my implementation of DJ's suggestion would be to have a symbol for the functional pins of the connector, and then another symbol for mounting holes, shell ground, what-have-you. You could even have different infrastructure symbols for different manifestations of the extra pins from different manufacturers. If you give all the symbols associated with a particular component the same refdes, the netlister will sort it out. I like having the infrastructure on separate symbols because then I can put all the power (etc) distribution glorp on it's own sheet(s), and it doesn't clutter up the functional schematic. That's obviously a matter of taste and your personal documentation conventions. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dxf again
On Jul 16, 2010, at 7:17 AM, Armin Faltl wrote: Dave N6NZ wrote: But my application is a little different. I want to get a DXF file that I can run through a CAM package, in particular the paste layer, which isn't a 'real' layer, unfortunately -- it is synthesized in the output HID as I understand it. I somehow feared this while I wasn't sure: so it is not posible to manually define the paste mask on a footprint? If it's possible, how? I need this to create the footprint of a part with thermal central pad. The manufacturer recommends the mask should cover 55-70% of the central area while near 100% of the electrical pads are to be covered with paste. The industry std-solution is to grid hatch the large continuous areas which also helps to keep the paste in place. Hand-soldering is a nightmare-option with 0.5mm pad-pitch ;-) Is it possible to define an offset to the copper area per pad? pcb footprints don't directly support that kind of complex solder mask. You might be able to employ some trickery by making the large pad out of an array of smaller pads with appropriate mask definitions and all with the same pin number. Kinda clunky. -dave If nothing else helps, how difficult would it be, to just create an attribute that triggers a stub that fetches and inserts a handcrafted gerber-snippet from a file instead of running the generator? Thanks in advance, Armin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Draft Licence for Open Source Hardware published (OT)
On Jul 14, 2010, at 10:50 PM, timecop wrote: You said you wanted a 100% open source tool chain and gave FPGA as example. So, please name a vendor who provides such hardware/software (for FPGA design) which would satisfy this license requirement of being 100% open. I don't believe there is one. Yet, a license that says only that you must publish design data in publicly documented file format would allow such a design. That is my point. On Thu, Jul 15, 2010 at 2:06 PM, Dave N6NZ n...@arrl.net wrote: On Jul 14, 2010, at 9:47 PM, timecop wrote: Example: FPGA's. Verilog source isn't going to help if the FPGA fitter tool proprietary OK. Please name a vendor for FPGA hardware + toolchain that fits into this absolutely ridiculous requirement. I don't understand your question. Can you clarify? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Draft Licence for Open Source Hardware published (OT)
On Jul 15, 2010, at 7:47 AM, asom...@gmail.com wrote: On Wed, Jul 14, 2010 at 10:32 PM, Dave N6NZ n...@arrl.net wrote: On Jul 14, 2010, at 7:46 PM, Windell H. Oskay wrote: On Jul 14, 2010, at 7:36 PM, Ales Hvezda wrote: And my usual questions: http://lwn.net/Articles/396011/ I've had some part in this. Whether or not proprietary design files can be compatible with open source hardware has been an active topic of debate, even amongst the people writing that draft definition. It's a tough, tough call, for all the reasons that Bunnie mentions. I think that the proper place to resolve this issue is in the actual *licenses,* which as with OSS may vary from permissive to restrictive. I'd like to see the evolution of at least one OSHW license where a requirement is that the design files for the project-- and its derivative works --need to be in open, documented formats. That's the right answer -- let there be a battle of licenses. Although hopefully, it is a small set and we avoid the license salad issues that have sprung up in software. I, too, want to see (and would use) a license where all source files for all aspects of the design are in open, documented formats, but that isn't going to be to everyone's liking or practical in all cases. But also, I'd like to point out that just having an open documented source language isn't really enough. What I really want in the end is a 100% open source tool chain, and simply having an open file format isn't sufficient. Example: FPGA's. Verilog source isn't going to help if the FPGA fitter tool proprietary. So (thinking out loud) maybe some kind of license that says the file format documentation *and* sources (or mirror pointers) for all the development tools are a required part of the distribution source. I too _want_ a 100% open source tool chain, but it's not going to happen anytime soon and I don't think it's appropriate to insist upon it in a license. If a developer wants his work to be maximally free, he should ensure that it _can_ be built with an open-source toolchain, Yes, good point. And that is what I would like also, that it *can* be built with an open source tool chain. Coming up with both practical license language and operationally practical design file packaging practices that accomplish that is challenging. My key point is that simply requiring publicly documented design file formats is not sufficient. There is certainly a place for a license that requires publicly documented design file formats, and nothing more. But I'd also like to see some kind of license ensures the design can be built with an open source tool chain. snip ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dxf again
On Jul 15, 2010, at 12:40 PM, Mark Rages wrote: Hi all, Having reached the limits of pcb's feeble editor, I want to take some traces on a pcb through a pcb-???-dxf-qcad-dxf-dxftopcb-pcb cycle. I had already written the dxftopcb tool. (http://vivara.net/software/dxftopcb) when I discovered dxf2pcb (http://archives.seul.org/geda/user/Sep-2009/msg00134.html). So before I start on the pcbtodxf tool, has anybody done this already? Done, no. Thought about, yes. But my application is a little different. I want to get a DXF file that I can run through a CAM package, in particular the paste layer, which isn't a 'real' layer, unfortunately -- it is synthesized in the output HID as I understand it. And while preserving dimensions is useful in some situations, I also want to be able to do rule-based adjustments of dimensions. And I also want to be able to deal with a pcb design from any tool. Anyway, my last thoughts were that pcb is the wrong place to do what I want to do. The correct place is a gerber2dxf conversion tool. The new gerbv is librarized, so one could write a front-end to libgerbv that read gerbers via libgerbv and then did the massage and output function. You might checkout the gerbv library API, and consider if maybe that is a better place to accomplish your job. -dave PS. Another application is simply creating a component for a 3D mechanical CAD package. For that, exporting an outline layer and the drills as a .dxf would be sufficient for making a component that could be slurped into SolidWorks or FreeCAD or such. Again, probably a nice application of libgerbv. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Draft Licence for Open Source Hardware published (OT)
On Jul 14, 2010, at 7:46 PM, Windell H. Oskay wrote: On Jul 14, 2010, at 7:36 PM, Ales Hvezda wrote: And my usual questions: http://lwn.net/Articles/396011/ I've had some part in this. Whether or not proprietary design files can be compatible with open source hardware has been an active topic of debate, even amongst the people writing that draft definition. It's a tough, tough call, for all the reasons that Bunnie mentions. I think that the proper place to resolve this issue is in the actual *licenses,* which as with OSS may vary from permissive to restrictive. I'd like to see the evolution of at least one OSHW license where a requirement is that the design files for the project-- and its derivative works --need to be in open, documented formats. That's the right answer -- let there be a battle of licenses. Although hopefully, it is a small set and we avoid the license salad issues that have sprung up in software. I, too, want to see (and would use) a license where all source files for all aspects of the design are in open, documented formats, but that isn't going to be to everyone's liking or practical in all cases. But also, I'd like to point out that just having an open documented source language isn't really enough. What I really want in the end is a 100% open source tool chain, and simply having an open file format isn't sufficient. Example: FPGA's. Verilog source isn't going to help if the FPGA fitter tool proprietary. So (thinking out loud) maybe some kind of license that says the file format documentation *and* sources (or mirror pointers) for all the development tools are a required part of the distribution source. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Draft Licence for Open Source Hardware published (OT)
On Jul 14, 2010, at 9:47 PM, timecop wrote: Example: FPGA's. Verilog source isn't going to help if the FPGA fitter tool proprietary OK. Please name a vendor for FPGA hardware + toolchain that fits into this absolutely ridiculous requirement. I don't understand your question. Can you clarify? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Matching footprints with symbols
On Apr 14, 2010, at 10:18 AM, Kai-Martin Knaak wrote: 3) There is consensus, that the current library is in poor shape. But there are diverging opinions how a good default library should look like. And I doubt there will ever be a one size fits all library. The flexibility of the current system is it's strength, you can pretty much always get what you want, or close enough. OTOH, the flexibility of the current system causes no end of confusion to new users. I think that there are probably different libraries for different user communities. I can think of two footprint libraries right off: a) result must be easy to hand solder -- either because the user is a hobbyist or someone who wants to create kits for a hobbyist community where you want good results to come easily, and b) result targets automated manufacturing at low cost, using lots of SMT. And when it comes to symbols, then it gets into religious arguments :) I like symbols that might pass for ANSI compliant. And I split the power/ground/infrastructure into a second block. Either of those ideas can make other people wince. So it gets tangled up in methodology arguments, too. So, in an ideal world, I could see having different communities (Library SIGs) support different libraries. A community/library being defined by a list of design rules and methodology guidelines. Anyway, all that said, I think that is expecting a lot for the gEDA community to form library SIGs around different design rule manifestos. There just aren't enough of us to go around. For the time being we are all Library SIGs of one person each :) -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I reference a shell variable from guile script?
On Apr 8, 2010, at 3:31 AM, Kai-Martin Knaak wrote: On Wed, 07 Apr 2010 11:21:53 -0700, Dave N6NZ wrote: No amount of googling brought up a simple syntax example like that. I added a note in the wiki. Great! The on-line guile documentation that I found via google was pretty hard for me to navigate, since I don't know guile. It's a case of if I knew what I was looking for, I could have found it For those of us that use guile only with gEDA, simple cookbook examples are perfect. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: hierarchy and net attributes.
So as I understand the current situation in gschem/gnetlist, there is no way to get a global net in a hierarchical design other than to set: (hierarchy-netattrib-mangle disabled) in gnetlistrc. However, now all net attributes will become global nets. So, if one uses off-page connector symbols, the net attribute in off-page connectors will now become a global net. So, in essence, there is no way to have a multi-sheet lower level schematic that accesses global nets using the disable mangle hack. Disabling mangling has the side effect of turning any signal in a lower level sheet with an off-page reference into a global net. Is this correct? Or am I missing something? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: hierarchy and net attributes.
On Apr 8, 2010, at 2:28 PM, Dave N6NZ wrote: So as I understand the current situation in gschem/gnetlist, there is no way to get a global net in a hierarchical design other than to set: (hierarchy-netattrib-mangle disabled) in gnetlistrc. However, now all net attributes will become global nets. So, if one uses off-page connector symbols, the net attribute in off-page connectors will now become a global net. So, in essence, there is no way to have a multi-sheet lower level schematic that accesses global nets using the disable mangle hack. Disabling mangling has the side effect of turning any signal in a lower level sheet with an off-page reference into a global net. Is this correct? Or am I missing something? I see that I was missing that hierarchy-netattrib-mangle and hierarchy-netname-mangle are two different things. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I change initial window size on gschem and pcb?
On Apr 7, 2010, at 5:38 AM, Peter Clifton wrote: On Wed, 2010-04-07 at 14:23 +0800, Atommann wrote: Hi, 2010/4/7 Dave N6NZ n...@arrl.net: This may be an X-windows-on-Mac question, not a gEDA question, but... When gschem or pcb open on my macbook, the window is too tall, and the resize grabber is off the screen on the bottom and I can't reach it to resize the window. Normally, not an issue since I immediately move the window over to a nice big second monitor... but... when I am on the road, this sucks hugely. So... is this an X-windows setting someplace? Or is there some place in the source code where it asks for the screen size and opens over the whole works? -- I'm building both gschem and pcb from sources so I can easily tweak if that is the case. When gschem starts up, it show: ... Read system config file [/usr/share/gEDA/system-gafrc] Read system config file [/usr/share/gEDA/system-gschemrc] Read user config file [/home/atommann/.gEDA/gschemrc] Read init scm file [/usr/share/gEDA/scheme/gschem.scm] ... So, you can open /usr/share/gEDA/system-gschemrc and search for keyword window, read it and you will find how to change the initial size of the gschem window :) You can also add the following line to the file ~/.gEDA/gschemrc to override the settings in system-gschemrc (window-size 950 712) ; Good size for 1152x864 Looking at the code, I'm not sure that will actually do anything.. let me know if it works. OK, great. I will try that and report back. That will be convenient if it does work. Of course, someone reminded me that the green button on a Mac window will do a full-screen resize, which has the effect of reshaping an oversize window to something useable. Another face-palm moment for me. We now have a file which remembers location and size of various windows, but not the main window - the window manager is in charge of that kind of thing. Yes, which is an annoyance for me but not something it seems we can do anything about. When at my desk, I run my Mac laptop with a 24 external monitor, which is of course the natural place for gschem, pcb, and any other CAD program. But the Mac X Windows system always opens windows on the first monitor, which is the laptop screen, so I'm constantly dragging them over. The native Mac applications using the Quartz window manager open where they were when the program last shutdown, assuming the monitor is still available. For whatever reason, the Mac X Windows subsystem doesn't do that. Thanks, Dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: paid help?
On Apr 7, 2010, at 9:25 AM, Stefan Salewski wrote: On Wed, 2010-04-07 at 13:43 +0900, timecop wrote: I would never trust pre-made symbols for any project, it takes very Similar for me, and I do not trust my own symbols also! True enough. The only time I have been badly burned is when using a downloaded footprint without checking it. OK, not true. The *other* time I was badly burned was when I expected that the footprint in a Freescale data sheet would actually be somewhat close to the actual part -- I do admit it had the same number of pins... And then I've made goofs that were my fault, but mostly of the silkscreen polarity backwards variety. And I have to admit that I do not really trust the linux kernel, my web browser and email client, ... Maybe I should try to write all of this myself, when I am finished with building my own car and CPU. I've got a friend like you. He doesn't like C, so he wrote his own compiler. He won't pay for SolidWorks or similar, so he wrote his own 3D CAD package. He's now working on his own CAM package -- someday he may make a part, but last week he did a spindle-off rapid plunge into a piece of 1/2 aluminum plate on the HAAS at San Jose City College. HAAS rapids are pretty fast :) It's interesting working on CNC and robotics... the phrase software crash takes on a whole new meaning. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: How do I reference a shell variable from guile script?
Suppose I want to build a path like: $HOME/path/gedasymbols to pick up component libraries, without unrolling $HOME into a hard path in a (define..) -- how do I get guile to pick up the value of $HOME from the shell, and then get it pasted into the rest of the stuff? I'm aiming for: (define gedasymbols path built off $HOME) (component-library (build-path gedasymbols foo)) TIA -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How do I reference a shell variable from guile script?
On Apr 7, 2010, at 11:05 AM, John Doty wrote:
On Apr 7, 2010, at 11:49 AM, Dave N6NZ wrote:
Suppose I want to build a path like: $HOME/path/gedasymbols to pick up
component libraries, without unrolling $HOME into a hard path in a
(define..) -- how do I get guile to pick up the value of $HOME from the
shell, and then get it pasted into the rest of the stuff?
Use ${HOME}. Here's a related (working) example from one of my projects:
(component-library ${EDCCD_DEV}/hardware/symbols/EDCCD)
Perfect! No amount of googling brought up a simple syntax example like that.
Thanks,
-dave
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: symbol edit-translate working strangely
I've created some symbols with non-zero width outlines using line elements of width 40. edit-translate(0) seems to get confused, and offsets the symbol so the pins don't line up on 100 unit grid. edit-translate with independent x,y values seems to by broken. How can I fix this, short of writing a script to translate the X/Y coordinates? (And no, I'm not going back to zero-width boxes. Wide lines are too pretty.) -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: paid help?
On Apr 6, 2010, at 10:52 AM, Mark Rages wrote: On Tue, Apr 6, 2010 at 12:27 PM, Anthony Shanks yamazak...@gmail.com wrote: Didn't bother with any kind of scripted footprint generator as I wanted to know exactly what the file format was for footprints. Once I discovered how easy it was I felt it wasn't worth fighting with a script that may or may not do what i needed to do. It's been working fine for me and I haven't had any problems with footprints thus far and I spent very little time making footprints compared with the rest of the layout process. For a programmer, it is easier to write a scripted footprint generator than to roll a footprint by hand with a calculator and text editor. Where the script really pays off is when you need to update/tweak the footprint. Staring at a bunch of numbers 3 weeks (or months) later is hopeless. So I pretty much use script-generated footprints because then I know how to update and regenerate them. In fact, all of my footprint generating tools emit the script command line as a comment embedded in the symbol, along with date stamp and other simple history. The idea is that I can get the exact same footprint back by cutting/pasting the comment into a command line prompt. Which of course is much less interesting than making some tweak to the command line to generate a slightly different footprint. Or, in the case where the script contains an error (that never happens. :) it is easy to regenerate all the effected footprints. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: paid help?
On Apr 6, 2010, at 4:21 PM, Levente Kovacs wrote: On Tue, 6 Apr 2010 09:41:37 -0700 Anthony Shanks yamazakir2-re5jqeeqqe8avxtiumw...@public.gmane.org wrote: In my opinion it's worth spending an hour going over the footprint file format and just making your footprints in an ASCII editor. Once you know the file format it's very fast ( 10 min per footprint on average) and you get the exact dimensions you need specified by the datasheet. Making footprints with this method in my opinion is easier and faster than most closed source tools I have used. With that said, I still think pcb has many shortcomings, but footprints aren't one of them. Is there any non-interactive footprint editor around? Like a perl script which can set mask and clearence. It would be nice for example run it through your library, and it would set the mask offset to x. Yes, well, some of DJ's footprint generators are on the geda symbols website as interactive web pages. And I have written a couple of quick generator programs that I've yet to make public -- first excuse being that until I fabbed some boards with the footprints I didn't think that wise, (excuse no longer applicable), second excuse being that they aren't really in a form where I'm not embarrassed to have other people read my code :( I've just never cleaned them up. Of course, you are asking about something different it seems, not a generator, but a parametric tweaker all masks shall now have offset X -- which is suppose could be handy, but I just regenerate the footprint with different parameters. -dave It would also be nice to do this on a footprint in *.pcb file. Thanks. Levente P.S.: If no one have such thing... I warm up my editor to write it. :-) On Tue, Apr 6, 2010 at 9:35 AM, John Doty jpd-eogpokeig7iavxtiumw...@public.gmane.org wrote: On Apr 6, 2010, at 9:25 AM, DJ Delorie wrote: I am just getting started and may say things that sound stupid. Even something you think sounds stupid gives us some insight into how new users perceive our software :-) One of the problems here is that the gschem GUI channels new users in a dysfunctional direction. Referencing library symbols is more often than not the wrong way to go. Embedding, sometimes given as an alternative, scales poorly, so it's only applicable to the smallest projects. A better way is to import every symbol you're using into your *project* (not just the schematic page you happen to be working on). One you have a project-local copy, the needed customizations are easy through Hierarchy-Down Symbol. I keep a shell window open for this purpose. Use gschem to browse for a symbol similar to what I need, go to shell window and copy to project, hit the #...@% refresh button on the symbol browser, then pick it up from the project symbol directory. This isn't at all time consuming, and in the end saves a *lot* of time, but it sure isn't obvious to the beginner. I guess this leaves me with a question... Is geda meant for the non-lazy high end user that roll's his/her own footprints? It's a mix of both. We *do* have libraries of symbols and footprints for many of the commonly needed parts. People *still* often have to roll their own because we just don't have *every* part in our library. Not just that: the symbols in the library are inevitably wrong in some way in light of the needs of a particular project flow. Yes, we'd like our library to be more complete, but we've been discussing this problem for YEARS and have yet to come up with a workable solution. If so then if I paid for a few more then it would not really help as this is not the intended direction. Hmmm... no, that's not right. Intent has nothing to do with it, it's just not practical for us to have every part in our libraries. Every part in every manufacturer's variant for every customer's documentation requirements using every design flow and every manufacturing flow... A trillion symbols would not be sufficient. If the project does need more footprints then would it not be good to come up with a viable solution to create them? Sure. Go ahead :-) For instance could someone sell a support package, i.e includes 50 footprints for X amount of money. These footprints would then become open source and available to all, free as in beer. Would this approach not bring more people to the project? or would it bring the wrong kind of people? I think this would be a great idea, if (1) you could find people willing to do that, (2) you could find people willing to pay for it, and (3) they could agree on a price. But this has nothing to do with *our* desires, it's a free market - all it needs is two people willing to deal. We already have gedasymbols.org where people can put freely usable symbols and footprints, I don't think anyone would have a problem with someone promoting their own services and rates on their gedasymbols
gEDA-user: How do I change initial window size on gschem and pcb?
This may be an X-windows-on-Mac question, not a gEDA question, but... When gschem or pcb open on my macbook, the window is too tall, and the resize grabber is off the screen on the bottom and I can't reach it to resize the window. Normally, not an issue since I immediately move the window over to a nice big second monitor... but... when I am on the road, this sucks hugely. So... is this an X-windows setting someplace? Or is there some place in the source code where it asks for the screen size and opens over the whole works? -- I'm building both gschem and pcb from sources so I can easily tweak if that is the case. TIA, -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA logo title block, footprint
On Apr 5, 2010, at 3:22 PM, kai-martin knaak wrote: Dave N6NZ wrote: I'm getting started on an open-hardware project using gEDA, and did a couple of gEDA logo items. 1. logo'ed title block symbol. This is pretty much a clone of the standard title-B symbol, with these tweaks in the title block: * sub-block for copyright * sub-block for license (reference, not the whole thing :) * space for a project logo * gEDA logo You might add attributes for title, author, license and date. Of course gschem does not automatically fill the values. But they can be properly formatted ready for a one click edit. Yes, good point. And also grep-able by attribute name. Another option is to just define the title block and draw the large rectangle as needed. You never know the size of the schematic in advance... Umm and then when the page is scaled for printing the symbols and text on different sheets are all different sizes, aren't they? I'd like to avoid that. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gEDA logo title block, footprint
I'm getting started on an open-hardware project using gEDA, and did a couple of gEDA logo items. 1. logo'ed title block symbol. This is pretty much a clone of the standard title-B symbol, with these tweaks in the title block: * sub-block for copyright * sub-block for license (reference, not the whole thing :) * space for a project logo * gEDA logo 2. gEDA logo as a pcb footprint (all silk). This is derived from Peter Clifton's geda-logo.pcb. I wanted a .fp file, and wanted all silk -- how hard can that be, I thought? So I basically did a tracing of Peter's logo with silk tracks, and did a bit of adjusting. The 'bit of adjusting' took way more time than I expected, but anyway, it seems to be complete and correct. The files are attached. I haven't used them in a design yet, so while I believe they are correct, be on the lookout for bugs and other wonkiness. -dave tbtitle-B.sym Description: Binary data geda_logo.fp Description: Binary data ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Are multiple pinlabels on a symbol pin OK?
Normally when I construct a symbol for a microcontroller or such part where the
I/O pins can have multiple functions, I like to include the alternate functions
in the pin label, like this example from an Atmel part:
pinlabel=PE2 (XTAL2/ADC0/PCINT26)
But... I've run into a part where the list of alternate functions on some pins
makes the resulting symbol outrageously wide. I'd like to display the GPIO
name in the default font (10), and the alternate names in a smaller font (say 7
or 8).
Can I have two pinlabels on a pin? Like so:
P blah
{
T X Y 9 10 blah
pinlabel=PE2
T X Y 9 7 blah -- note smaller font size
pinlabel=(XTAL2/ADC0/PCINT26)
blah
}
Is that OK, or will gschem get confused down the road?
-dave
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf release branch in git? mac build?
On Mar 31, 2010, at 9:06 AM, John Griessen wrote: Peter Clifton wrote: On Tue, 2010-03-30 at 15:41 -0700, Dave N6NZ wrote: I want to follow the git -- but for now on the release branch (if there is one??) not the dev head. Use the stable-1.6 branch in that case. Individual releases are tagged as well. What's the git command to list tags? You are probably more interested in listing branches: git branch -r(list remote branches) git branch -a(list all branches) git branch(what branch am I on now?) What's a good write up of a short cheat sheet style list of commands for git? Read this for a start: http://www.geda.seul.org/wiki/geda:scm Otherwise, google. Lot's of folks have put up cheat sheets, there is no shortage. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gafrc/gschemrc ordering issue?
I am trying to get gschem to come up with my personal title block. Seems like it should be easy. But... Here is an rc file in the project directory: (component-library /Users/dave/gitrepos/gedalib/tbsymbol2) (define default-titleblock tbtitle-B) If that file is named gafrc, the 'define default' is ignored. If that file is named gschemrc, it whines about not being able to find the symbol. Likewise, if gafrc contains only the library line, and gschemrc contains only the titleblock line, it whines. And yes, the library path works fine. I can add my title block manually. ?? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gEDA/gaf release branch in git? mac build?
Hi, I'm about to attempt building gEDA/gaf on a Mac. My plan is to use the git repo. Two questions: 1. Is there a branch or tag or such for the latest release? I'd like to track that and not follow the development head for now. 2. Any special Mac build tricks I should know about? I use macports, not fink, and don't plan to use fink since macports and fink don't always get along. My naive plan is to simply chase all the dependancies away with macports until gEDA/gaf builds. Now would be a good time to stop me from doing something dumb. Thanks, dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf release branch in git? mac build?
On Mar 30, 2010, at 3:05 PM, Steven Michalske wrote: On Mar 30, 2010, at 2:49 PM, Dave N6NZ wrote: Hi, I'm about to attempt building gEDA/gaf on a Mac. My plan is to use the git repo. Two questions: 1. Is there a branch or tag or such for the latest release? I'd like to track that and not follow the development head for now. 2. Any special Mac build tricks I should know about? I use macports, not fink, and don't plan to use fink since macports and fink don't always get along. My naive plan is to simply chase all the dependancies away with macports until gEDA/gaf builds. Now would be a good time to stop me from doing something dumb. sudo ports install gtk2 guile Then build gaf from source, pretty easy or sudo port install geda-gaf It gets 1.6.0 I want to follow the git -- but for now on the release branch (if there is one??) not the dev head. PCB is a bit outdated in the ports system and there are two bugs reporting it out of date, but the macports team has not patched them I'm already following the pcb development head in git. Thanks, dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA/gaf release branch in git? mac build?
On Mar 30, 2010, at 3:53 PM, Peter Clifton wrote: On Tue, 2010-03-30 at 15:41 -0700, Dave N6NZ wrote: I want to follow the git -- but for now on the release branch (if there is one??) not the dev head. Use the stable-1.6 branch in that case. Individual releases are tagged as well. Very good. Have it up and running. Thanks, -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
On Mar 10, 2010, at 4:24 AM, Peter Clifton wrote: Questions though.. What to do with a manually defined paste layer if the user fiddles with the size of the copper pad / solder mask? (Assuming that eventually becomes more flexible to edit). ? I don't think I understand the question. Are you asking what to do if the user is editing pads and masks inside of a placed footprint inside PCB? I think the answer is, if the user wants to change the solder mask, he fiddles that, too. Solder mask aperture is important as well as pad size, since the stencil opening probably ought never include areas which are solder-masked. It is possible (although I'm not sure how useful) to set a partially masked pad - perhaps as some kind of heat-sink for a transistor, with a defined mask opening. There is such a thing as a mask defined pad where the copper is larger than the mask aperture, and the mask aperture is what defines the effective size of the pad. In that case, the stencil should be the smaller of pad or mask aperture. I've never built a board that way, FWIW. Heat sinks are an interesting case. First off, the pad might be much larger than the device tab. The whole thing will be unmasked. But it probably wants a pattern of a few dots of solder on it, not a giant puddle. The problems I am trying to solve in my particular case are: 1. In some cases, heuristics have no chance what so ever of deriving the mask that I want from the pad layer. So I want to specify it precisely in a footprint file and not have any tool do any underhanded automatic tweaks to it, ever. 2. My personal technology for homebrew stencils has limitations that require modifications to the current paste layer that are not easily programmed into an automated tool. Again, I just want to say it once in a footprint file, and no tool should ever try to out guess that. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
Well, for one thing, dxflib is rock solid, and pstoedit was broken in many ways the last time I tried to use it. -dave On Mar 9, 2010, at 2:48 PM, Windell H. Oskay wrote: Doesn't pstoedit already do this, too? http://www.pstoedit.net/ Are there advantages to these custom versions? I've wrote some C++ code to convert a DXF to PCB. It is in works for me state. Levente I've written one as well, in the same state. http://vivara.net/software/dxftopcb/ I'd like to see pcb link to dxflib for import and export. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
On Mar 9, 2010, at 3:33 PM, Peter Clifton wrote: On Tue, 2010-03-09 at 18:27 -0500, Dan McMahill wrote: pstoedit converts postscript to various formats. So I suppose you could try pcb export to postscript and then pstoedit to produce dxf. That said, there are always issues with file conversions and I suspect you're much better off letting pcb directly produce dxf. But it may just work. NB: The code being talked about is DXF - PCB outline... not PCB-DXF. It seems that we now have _three_ people who have independently written such a tool. I guess this suggests people are wishing to design boards which fit in a given mechanical envelope, as exported from a mech.-cad package. Which is an interesting thought. For my part, if I could get the board outline and the location of mounting holes to/from a .dxf file, it would cover everything that I need for chassis fit. My designs are so small that doing it manually isn't a hassle for me, but of course that doesn't scale in the real world. What I really want, though, is a way to get the stencil layer pad outlines as .dxf entities. I took a look at the code, and it appears that the stencil layer isn't a real layer -- is that true? Is it simply generated on the fly off the pad information during gerber export? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
On Mar 9, 2010, at 4:01 PM, DJ Delorie wrote: is that true? Is it simply generated on the fly off the pad information during gerber export? That's true. Just in case anyone is confused by the tight snippage: It is true that there is no real paste layer, it is generated on the fly off the pad information. OK, so... for a long time, I've been thinking about how to add refined paste information. My approach would be: 0. Extend the lexer and parser to warn and ignore on unrecognized keywords in footprints. This allows some backwards compatibility of pcb with new footprint keywords, although at the expense of error checking. Maybe should have a 'strict' option to cause an error. 1. Extend footprints to include a paste (...) keyword that looks pretty much like the 'pad() keyword. 2. If paste() doesn't exist for a footprint, synthesize one from the pad() information. That way, old footprints work just as they do now. 3. Add a paste layer to carry around the paste() information through all the translation/rotation of the symbol. 0, 1, and 2 I think I can sort out relatively easily. I have no idea how to add a layer and do all the necessary updates for footprint relocation. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Looking for my first fab shop.
If this is your first board, I'd go with a shop that is reasonably fast and known for quality work. Fast because: * this is your first board, and you are excited to have it. * this is your first board, and now is the time to make mistakes quickly. Quality work because: * this is your first board, and you don't need to chase any red herrings. On this side of the pond, I'd go for APCircuits or PCBExpress (not to be confused with express PCB). Either will give you a very high quality board, quickly. Either is as easy to work with as ordering a book from Amazon. Either will appear costly compared to slower solutions of less predictable quality. IMHO, today is your day to spend a few more dollars on a PCB and eat a cheap lunch. :) My friends have used Olimex with happy results, although you will wait. I used to be high on SparkFun's BatchPCB, but soured on it after experiencing long waits and getting back junk. Well, not total junk. I ordered multiple units of several different designs, and got back nearly 2X of each that I ordered. OK, at first I'm thinking they felt generous when they were panelizing, nice customer service. Turns out, many were bad boards. I think somebody *knew* they had just created a batch of dodgy boards, and ran another batch of panels and sent the whole output to their customers to sort it out. I consider 60% yield, expecting the customer to weed out the pigs, as unacceptable quality. The BatchPCB vendor is Gold Phoenix, a Chinese vendor. If you are outside North America, then APCircuits or PCBExpress may not be cost effective options. -dave On Mar 8, 2010, at 10:36 AM, jason duhamell wrote: Are you willing to work with chinese? On Tue, Mar 9, 2010 at 2:30 AM, Jim [1]...@k4gvo.com wrote: Are there any fab shops that would be gentle with a very new, very inexperienced PCB designer? OH and reasonable for a prototype. Last time I laid up a board I used a drafting table and mylar. I may need a bit of handholding as I go along. Thanks, Jim. ___ geda-user mailing list [2]geda-u...@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:j...@k4gvo.com 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: I am such a troll for posting to slashdot
On Feb 27, 2010, at 8:51 AM, John Luciani wrote: John hasn't had time to finish :( So John, post a to-do list and your check-in check-list. If several of us volunteer to do a symbol or three we should be able to push it over the hump by a reasonable deadline Symbols by the Solstice or some other alliterative motto... -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Native Mac OS X?
On Feb 27, 2010, at 12:44 PM, Peter Clifton wrote: Someone with a Mac might like to try building gEDA and PCB with a native version of GTK? OK, I'll play dumb. I recently built PCB from git after naively using macports to make all the dependancies go away. How is that different from what I did? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Native Mac OS X?
On Feb 28, 2010, at 9:35 AM, Charles Lepple wrote: On Sun, Feb 28, 2010 at 11:24 AM, Dave N6NZ n...@arrl.net wrote: On Feb 27, 2010, at 12:44 PM, Peter Clifton wrote: Someone with a Mac might like to try building gEDA and PCB with a native version of GTK? OK, I'll play dumb. I recently built PCB from git after naively using macports to make all the dependancies go away. How is that different from what I did? When you run PCB, does it require an X server? In this context, a native PCB would not need X11.app to run. Ahhh... OK, I get it. Yes, my build brings up the X server. But other than the start-up time, that doesn't bother me. X11 is preinstalled as of 10.6 (or maybe 10.5, I forget which) so the hassle factor is pretty minimal. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open Source mechanical CAD on the horizon
On Feb 24, 2010, at 6:09 PM, Girvin R. Herr wrote: Kai-Martin Knaak wrote: I just got aware of the open source mechanical CAD project freecad. It hit the debian repository a month ago. Although it is still lacking important features, much of the basic infrastructure is already up and running. http://en.wikipedia.org/wiki/FreeCAD_(Juergen_Riegel) ---(kaimartin) Kai, Have you, or anyone in the group, used FreeCAD for any useful work? I just downloaded the source code for Linux and took a look at the docs. Although they may not be up to date (file date of Jan 7, 2010), they have no substance. It is proclaiming there isn't yet much in the way of GUI commands to implement the internal drawing functions. A couple of weeks ago I took a look at the state of FreeCAD, but haven't done anything very useful with it. I had a brief forum chat with the developers. I think they will tell you that the current state is mainly useful to developers. They are driving it via scripts to build things, and gradually adding a GUI. I think if you are expecting much in the way of GUI today, you will have to start following the source code repository and surf the bug frontier along with the developers. Of course, you may find if you download it that I haven't gotten quite the correct impression, because as I said I haven't done much of anything with it yet -- too busy with other things. All that said, FreeCAD has come a huge distance in a year. If they make as much progress in the next year as they have in the past, we will have the makings of a good 3D parametric modeling program. They certainly deserve support and encouragement. If you are looking for 2D CAD, then go with QCad. I've done a lot with that. It is very mature and very solid. I use it for all my 2D CAD designs, and I've used their .dxf I/O library in a CAM program for one of my tools. -dave much stuff snipped out ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Making circles in PCB
On Feb 25, 2010, at 10:45 AM, DJ Delorie wrote: Everything in pcb supports non-90 arcs, except for the ability to create them. Someone needs to come up with a friendly way to create/edit arcs that aren't 90 degrees, that's all. FWIW QCad has 3 pimary arc creation modes: 1. click1 sets center, click2 sets radius, click3 sets end point 1, click4 sets end point 2 2. click1 sets endpoint 1, click2 sets a point on the arc, click3 sets end point 2 3. click 1 selects a point of tangency on a line, radius set by dialog, click 2 sets end point 2 One mode of elliptical arc creation: click for center, click for axis 1/radius 1, click for axis2/radius 2, click for end point 1, click for end point 2. Not that pcb needs to or should follow QCad, just posting the info for reference. The center/radius/end1/end2 method seems pretty natural and if PCB did only that it would cover a lot of ground. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Making circles in PCB
On Feb 25, 2010, at 4:01 PM, Vanessa Ezekowitz wrote: On Thu, 25 Feb 2010 14:57:20 -0800 Dave N6NZ n...@arrl.net wrote: On Feb 25, 2010, at 10:45 AM, DJ Delorie wrote: Everything in pcb supports non-90 arcs, except for the ability to create them. Someone needs to come up with a friendly way to create/edit arcs that aren't 90 degrees, that's all. FWIW QCad has 3 pimary arc creation modes: [snip] Not that pcb needs to or should follow QCad, just posting the info for reference. The center/radius/end1/end2 method seems pretty natural and if PCB did only that it would cover a lot of ground. The way I as thinking, the user could click once to set the center, make a second click to set the radius and the first endpoint of the arc at the same time, and a third click to set the second endpoint of the arc. One might also want to support the control key to constrain the arc to regular steps like 22.5 degrees. Yes, that makes sense for pcb, I think. In QCad the extra click to set radius separately is convenient because the snap point (and snap type) for the radius often wants to be different than the snap point for the first end point. (*) But in pcb, I don't see that being much of an issue. -dave (*) QCad allows a variety of snap types, including snap to intersection which is a way cool power user trick. I usually create a layer of construction lines, using a distinctive color, and then set snap to intersection. That eliminates huge amounts of time spent trying to niggle 0.1mm adjustments to line ends. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Eagle to gEDA conversion path??
Hi, Is there any automated Eagle to gEDA conversion path? (He says hopefully, but knowing it's highly unlikely.) -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eagle to gEDA conversion path??
On Feb 22, 2010, at 9:08 PM, timecop wrote: Diptrace has a pair of ulp scripts to convert eagle project to ascii schematic and pcb. OK, although I don't know what either Diptrace or ulp are. Sounds like a good place to start, though. I'm wondering how the library issue would be handled. Presumably, it reads the Eagle library and spits out symbol information as part of the ascii? after some creative editing to make output format match geda, it should be fairly feature compelte On Tue, Feb 23, 2010 at 1:36 PM, al davis ad...@freeelectron.net wrote: snip I proposed a translator system, using an intermediate language, to translate both ways between schematic, layout, and simulation. It needs to happen. Really? Is there a use for gEDA-Eagle? I never would have cared about Eagle, except that the RepRap PCB's are done with Eagle. Now, why someone would do open source hardware with closed source tools is a mystery to me... but anyway so far in a total of 30 minutes of Eagle usage I've discovered: 1) the crippleware version only allows a single schematic sheet, leading people to create unreadable glop, and 2) printing is truly bizarre. I can't imagine someone going from gEDA to the free/crippled version of Eagle. And as to going to the commercial version, OK I can see some customer requiring that, but isn't that Eagle's problem? After all, nobody is hiding gEDA's file formats. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eagle to gEDA conversion path??
On Feb 22, 2010, at 10:29 PM, timecop wrote: ulp is eagle script file. Ahhh i assumed if you wanted to convert something, you'd have eagle running. Just barely, and just recently. And not for much total time yet. im pretty sure ulp can access to library data as well, so something to output ascii can be easily written. Well, diptrace must have the same problem. You either need to map from one library to the other, or export enough of the library that you can import into the new library the required symbols. diptrace is payware pcbcad, but freely downloadable version also includes these 2 conversion scripts. (Eagle_to_DipTrace_SCH.ulp and Eagle_to_DipTrace_PCB.ulp). A^2 since eagle .sch/.pcb format isnt documented and no external libs available to read it (as far as i know), the only way to export anything is write/use a script run inside eagle. That makes a lot of sense, even when the file format *is* well documented. The question is then, how much munging does it take to transmute diptrace ascii exchange format into gEDA stuff. -dave On Tue, Feb 23, 2010 at 2:53 PM, Dave N6NZ n...@arrl.net wrote: On Feb 22, 2010, at 9:08 PM, timecop wrote: Diptrace has a pair of ulp scripts to convert eagle project to ascii schematic and pcb. OK, although I don't know what either Diptrace or ulp are. Sounds like a good place to start, though. I'm wondering how the library issue would be handled. Presumably, it reads the Eagle library and spits out symbol information as part of the ascii? after some creative editing to make output format match geda, it should be fairly feature compelte On Tue, Feb 23, 2010 at 1:36 PM, al davis ad...@freeelectron.net wrote: snip I proposed a translator system, using an intermediate language, to translate both ways between schematic, layout, and simulation. It needs to happen. Really? Is there a use for gEDA-Eagle? I never would have cared about Eagle, except that the RepRap PCB's are done with Eagle. Now, why someone would do open source hardware with closed source tools is a mystery to me... but anyway so far in a total of 30 minutes of Eagle usage I've discovered: 1) the crippleware version only allows a single schematic sheet, leading people to create unreadable glop, and 2) printing is truly bizarre. I can't imagine someone going from gEDA to the free/crippled version of Eagle. And as to going to the commercial version, OK I can see some customer requiring that, but isn't that Eagle's problem? After all, nobody is hiding gEDA's file formats. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is it possible to do square holes in PCB?
On Feb 21, 2010, at 2:01 PM, Mark Rages wrote: On Sun, Feb 21, 2010 at 1:55 PM, Anthony Shanks yamazak...@gmail.com wrote: Some parts have mounting brackets that are square, not round. Yes I know I can make a equivalent circlular hole that would fit but it wastes a lot of space doing that and it interferes with routing. Have you talked to your board house about this? I wonder what happens if you specify a reuleaux drill in the fab drawing... How large is the square that you need? At some point, this is just another routed cut-out. You end up with a corner radius the size of the router bit in use, or else you can route a little past the corner to clear the corner of your square bracket. You would have to talk to your PCB house, but I'd be thinking along the lines of agreeing on what router bit is going to be used, and then adding a layer where the tracks represent the centerline of the routing operations. Wacky board shapes done by a CNC router are nothing new, routed cut-outs fall into that category. I'm sure your PCB house has a preferred way of getting the information. They will no doubt charge you the full freight, though, I don't know of any prototype service that does non-rectangular boards, although they might exist. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Problem With Macports Install
On Feb 16, 2010, at 7:37 AM, Chris Maness wrote: Would I just download the source myself and compile? Thanks, Chris I recently built pcb from the git repo without issues on 10.6.2. There were a number of dependencies that I had to resolve first -- IIRC they were all documented in the readme. In any case, I used macports for all dependencies and then simply built pcb from git head (living dangerously) and all went well. Good luck. -dave References 1. mailto:pc...@cam.ac.uk 2. mailto:ch...@chrismaness.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: All v. Any pin connectivity (was: Taking advantage of internally connected pins)
On Feb 3, 2010, at 12:33 AM, timecop wrote: At the very least, it seems that there should be a way to specify that any pin with the same number satisfies the connection. fairly ridiculous assumption especially with ICs, many of which specifically say something like all GND/VCC pads must be connected. Maybe if you go re-read the entire thread from the beginning, you will see how ridiculous and off-target your rant looks and will take another stab at it. This time spare me the insults and comment thoughtfully on the technical implications, please. I'm not talking about IC's I'm talking about switches. An IC would have separate pin numbers anyway. Two footprint pin/pads with the same pin number is the topic of discussion here. -dave (doing schematics as a paid professional since 1979) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: All v. Any pin connectivity
On Feb 3, 2010, at 7:53 AM, Vanessa Ezekowitz wrote: On Wed, 03 Feb 2010 06:47:19 -0500 Ethan Swint eswint.r...@verizon.net wrote: On 02/03/2010 03:33 AM, timecop wrote: At the very least, it seems that there should be a way to specify that any pin with the same number satisfies the connection. fairly ridiculous assumption especially with ICs, many of which specifically say something like all GND/VCC pads must be connected. In which case, the pins have unique numbers, if not names. snip Routing signals through those internal connections would have been no issue at all, though I wouldn't have thought to actually do so in the projects in question (and adding the extra copper to satisfy the netlist was no big deal). I imagine that's often the case. With a switch matrix, however, it can be a huge help in eliminating crossings. To that end, if I had to make a suggestion, it would be if the component can't handle the possibility of signals flowing through its internal connections (unsafe, won't work, etc.), then the footprint should get unique pin numbers and the existing policy should apply. That also seems correct to me, but I haven't gone on a thorough hunt for counter-examples. Otherwise, give each of the pins in an electrically-connected set the same number, and PCB should simply assume they're electrically equivalent. PCB should also further assume that connecting two such pins together with a copper trace does not violate the netlist. Yup. snip (Yeah, that's fine Vanessa, but who's going to write all the code to implement it? :-) ) The $64 question. Somebody that is familiar with the code will have to comment on the scale of this effort. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: All v. Any pin connectivity (was: Taking advantage of internally connected pins)
On Feb 3, 2010, at 9:59 AM, Peter Clifton wrote: The danger comes if you don't populate the switch. This then causes break in the board connectivity. True enough. But population options are an orthogonal conceptual axis. Not populating the microcontroller causes a loss of functionality, too. Population options are always specified elsewhere. I personally think such cases ought to be handled by making the connections explicit on the schematic - perhaps showing a two-pin through-connection on the switch symbol. That is a matter of methodology. I prefer showing a generic two-terminal SPST switch on the schematic, and mapping it to the footprint for the chosen device. Your suggestion intermingles function and implementation in a way that I don't like. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: close tracks leaving copper remnant in polygon
I've got a pcb where close tracks through polygons are leaving thin shards of copper between tracks. These are 8 mil tracks on a 10 mil grid. Seems to me these have always been cleared out in the past because they are below minimum copper size, but then again, I usually close space my tracks -- this is a very sparse, somewhat silly design my daughter is doing, so no design rules are being pushed. (But hey, if you can get a 10 year old kid begging to design pcb's, it seems like a worthwhile use of time and money...) Anyway, am I misremembering, missing a setting someplace, or is this a glitch in this particular build? This build happens to be just whatever was handy in the Ubuntu repo, and reports itself as 20080202. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: close tracks leaving copper remnant in polygon
On Feb 3, 2010, at 7:51 PM, Dave N6NZ wrote: I've got a pcb where close tracks through polygons are leaving thin shards of copper between tracks. These are 8 mil tracks on a 10 mil grid. Seems to me these have always been cleared out in the past because they are below minimum copper size, but then again, I usually close space my tracks -- this is a very sparse, somewhat silly design my daughter is doing, so no design rules are being pushed. (But hey, if you can get a 10 year old kid begging to design pcb's, it seems like a worthwhile use of time and money...) Anyway, am I misremembering, missing a setting someplace, or is this a glitch in this particular build? Hm guess it was just me. I have discovered the 'k' key -- I guess in the past when I've used 8/8 rules I've always jammed my tracks at minimum spacing in polygons and simply never noticed this behavior before. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: new components
I find it best(*) in the long run to crank out my own symbols. For things like the PIC, I use a modified version of DJ's djboxsym. I also have a couple of little generator scripts for other parts. -dave * By best, I mean best way to get symbols that match my personal taste. On Feb 2, 2010, at 5:32 AM, Chris Cole wrote: Hey all, I'm new to the gEDA community (and fairly new to electronics in general), and I have a pretty simple question for the gurus. I was working on converting a PIC project schematic into gschem when I realized that none of the Microchip IC's I was using were in the component library. What's the standard procedure for this? Is it easier to mooch off an existing part or to create your own? Thanks, Chris ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Confusion about symbol file and footprint file
On Feb 1, 2010, at 8:42 AM, Luke wrote: My questions are: 1) What is needed to associate a symbol to a footprint when you drawing the schematic in gschem? Is it a filename? set footprint attribute to the name of the file foo.fp If so, where does that file need to be located? I set a symbolic link named packages that points to my footprint library. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Pin pads on only one side
On Jan 30, 2010, at 9:21 PM, Kai-Martin Knaak wrote: On Sun, 31 Jan 2010 01:10:28 +, Phil Frost wrote: Is there some way to instruct PCB to put a copper pad for through-hole pins only on the bottom of the board? No. This is an aspect of the long standing feature request user definable pad-stack. True enough. Until then, you could do a hack by creating a footprint defining a very small annulus for the pin, and then on the back-side only put a surface pad over each hole. Some folks (me among them) do something similar to create easy hand soldering footprints for through-hole parts. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Taking advantage of internally connected pins
On Jan 30, 2010, at 4:00 PM, Ben Jackson wrote: I need to make a key matrix. I'm considering selecting a switch which has 4 leads (two leads per internal net): o--+--o ' / | o--+--o This appears to be a boon for the grid-style routing I need for the switch matrix. The rows can hop the columns inside the part, making everything fit on a single layer. (obviously I wouldn't do this with an IC, but it seems harmless for a switch) Anyway, if I give all pins different numbers, PCB doesn't know about the internal structure. If I give the electrically connected pins the SAME numbers then PCB thinks it needs to connect them with copper itself. If I connect them on a 'fake' layer then the autorouter works but the toporouter spins and I have to kill pcb. Any better ideas? I have no better ideas, and in fact have this exact problem on a design I am doing right now. Since PCB can't differentiate between like numbered pins must all be connected and one of the group of like numbered pins is sufficient, I think we are stuck with PCB doing the wrong thing on some designs. At least until the new pin swapping syntax becomes reality -- although I'm not sure how the current spec would handle this situation. Thinking about it, is PCB making the correct choice here? On IC's where several pins must be connected together, the IC typically has different pin numbers -- I'm thinking here of parts with multiple ground pins, for instance. What is the case where multiple footprint pins with the same pin number must be connected together in the PCB? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Solder Mask Layer
On Jan 28, 2010, at 12:46 PM, DJ Delorie wrote: I've done some hacks that look for layers named cmask or paste and just appends those to the gerbers, but nothing that can be committed. For those of us less familiar with the code, what is the internal design of pcb that forces you to do that? Are paste and mask layers not carried along at design time, but only created by output hids? (he speculates having only looked at the code enough to do tiny local patches). My reason for asking is that I would like to dig on a moderate-sized patch to add more capabilities w.r.t. paste layer handling. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Solder Mask Layer
On Jan 28, 2010, at 4:20 PM, DJ Delorie wrote: One of the LF tasks LF? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 26, 2010, at 11:25 PM, Bert Timmerman wrote: FWIW, There lives a dxf exporter for pcb in a not yet finished state at: http://github.com/bert/pcb-dxf-hid Thanks, I wasn't aware of that. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 24, 2010, at 3:40 PM, d...@umich.edu wrote: snip Dave, I have been following the RepRap project with interest. A 3D printer that anyone can make is a very cool scratch to itch. I am fascinated by the artwork of the sculpter, Bathsheba Grossman. She really shows what is possible with 3D printing. (http://www.bathsheba.com) Maybe the RepRap will progress to this level of precision, eventually. I am very impressed with the parts that people are currently making with it. I just placed an order for a MakerBot CupCake http://www.makerbot.com/ -- mainly just as a toy to share with my 10 year old daughter, who is both nerdy and arty (her self-chosen free-time activities this past Sunday were: a) drawing with her oil pastels, b) doing pcb layout on a game she is building for herself with my help, c) building cholesterol with her organic chemistry model kit) The CupCake should be an interesting toy. If you already have a good X/Y mechanism, I think just taking the CupCake's plastruder and mounting it on your mill or CNC router or whatever makes sense. I like the idea of using a cnc mill to vector plot the pcb artwork onto a photo-resist board with a laser. I do not think mounting a laser would be very difficult. There must be a low intensity laser that is in the correct frequency range to cure the resist. You could make different apertures easily by creating transparent slides with a single white dot against a black background. As far as a cheap x/y bed, how about doing it with a cheap machine that is massive and solid, like rock? I have been following the epoxy-granite thread on cnczone.com for a long time: Moving a laser pointer or a plastruder around doesn't require a highly rigid X/Y, not like milling or routing. How much rigidity you need really depends on what all you want to do with it. One of the light X/Y's like the Probotix Fireball V90 might be a reasonable choice for plotting and plastruding and light routing. In other news -- a few weeks ago some of us from the robot club visited a local used machine dealer and also the local Haas dealer, kicking tires, mainly. If you want a nice, rigid X/Y the Fanuc Robodrill is a nice rig. :) I won't have one any time soon, but I did get checked out on the Tormach at the TechShop. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 24, 2010, at 9:15 AM, John Doty wrote: CO2 is way out in the IR. I guess the way to use it is to vaporize the resist. Note that black in the visible may not be black at the IR wavelength in question, and vice-versa Good point... I should have remembered that because I was part of the local robot club crew that built official IEEE micromouse maze bases, which specifies flat black IR absorbing paint on the maze floor. One of the guys was in charge of testing paint. I was on the ShopBot crew at the TechShop that's my excuse :) -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 23, 2010, at 12:10 PM, Bob Paddock wrote: snip Management saw this: http://www.epiloglaser.com/ at CES and is thinking of spending money (a rare event) on one of them. There actually is a lot of industrial related stuff at the consumer show. I've used modern Epilog machines, and own a very crotchety old one that is no longer supported. I pray to the $DIETY of lasers that the tube doesn't die What I wonder is if this Epilog machine can really do PCBs. I have my doubts about etching the copper directly, CO2 laser is the wrong wavelength to cut metal. Only a couple percent of the radiation is absorbed. Great for plastics, though, and many other materials. With respect to PCB etching, one thing I've thought about but haven't yet tried is simply using paint. Apply a thin code of flat black paint as a resist (I'm guessing enamel would work best) and let the laser ablate the paint where you want to etch. Contact me off-line if you want to chat laser cutters. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 23, 2010, at 3:51 PM, Windell H. Oskay wrote: We have an Epilog. Low-power lasers of this type cannot cut (or even etch) copper foil, nor can they cut FR4. You can potentially use it to blast away an etch-resist layer, however; I've seen several examples of this. Here is one: http://www.cnczone.com/forums/showthread.php?t=41222 cool link. hadn't seen that one. He talks about getting the speed/power settings right so that the paint totally ablates without burning, and also so that flakes don't re-deposit back onto the board. Of course, you don't want it to re-deposit onto your optics, either. I can imagine it all being very tweaky. The modern Epilogs have what they call air assist which is essentially a small jet of air directed on the focal point that disperses the flammable gasses created in the kerf. It helps tremendously with flamage when cutting certain materials. My machine doesn't have that, I'd like to jury-rig a blower of some kind. Of course, if stuff comes off in large flakes, like it sounds like the paint does, you probably want just a big exhaust flow going across the board to pull it out before it can land anywhere. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 20, 2010, at 11:52 PM, Ben Jackson wrote: The polygon code is fully generic. It can do what you describe (in fact, it does, it just probably doesn't output in the format you want). Hmmm well, point me at the code, and I'll have a look at seeing what it would take to sew in Ribbonsoft's dxflib as a writer. All I really want to do is convert the edges of pads into lines and arcs. This sounds like an exercise in pulling X's and Y's out of pcb and stuffing them into dxflib objects. Assuming I can get arcs for the ends of rounded pads polygon1.c is PCB code that knows how to render PCB objects (like pads and lines) as polygons. polygon.c is a polygon library of sorts. Someone pasted in a long explanation I wrote into one of those (polygon1, I think). It knows how to make arcs, but it makes them out of straight segments. Upon reflection, it still seems to me that the correct place in the tool flow for gerber-dxf is in gerbv, not pcb. I've never looked at the new internals of gerbv since it has been rewritten and library-ified. So... am I deluded, or does this scenario make sense: 1. Turn the polygon code in pcb into a formal library 2. Add an export dxf outlines dialog/functionality to gerbv 3. Use the polygon library in gerbv to recognize connected gerber stroke outlines. 4. Add some new code to convert stroke outlines into dxflib objects 5. Use dxflib to write a dxf file. This seems to me like it would solve my paste layer extraction problem, as well as provide a path to pcb milling. In addition, it would provide a path to get a pcb design into the mechanical design flow. For example: A. To get a paste layer, I would load my design in gerbv, and simply export the paste layer as dxf outlines, and drop into my current tool flow. B. To mill a PCB, select a copper layer, and export as dxf outlines. Then use your regular CAM tool to create gcode from the dxf. C. To feed the mechanical design assembly, export the outline layer and drill layer (to get the mounting holes) as a dxf file, probably with two different layers in the dxf file, or perhaps as two dxf files. Import into Solidworks (or whatever) and turn it into a part drawing. (At this point, we'll probably start wishing footprints contained a model of the component hull.) I believe gerbv is the right place for dxf export, since that creates a tool that works with any gerber file from any tool. The overall tool flow is more logical that way. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 21, 2010, at 12:28 PM, Peter Clifton wrote: snip I believe gerbv is the right place for dxf export, since that creates a tool that works with any gerber file from any tool. The overall tool flow is more logical that way. Keep it modular enough, and it could live in PCB as well.. keeping the CAM export steps all together. Or.. go more modular (and Unix-y?): The argument for modularity is partly that not everyone designs pcb's with pcb. Intercepting the workflow before the gerber step cuts off those users. The only argument for including the functionality in pcb is short-term coding convenience. In the long run, modularity split along well defined interfaces wins. Have a gbr2dxf tool which links against libgerbv to do the work, but keep it out of gerbv. Yes, well, I thought of that. I was thinking that a gbr2dxf tool would want some kind of layer selection mechanism, but now that I reflect on it, all the layers are in their own file anyway. So the selection function is simply listing the gerber files on the command line. gbr2dxf could reasonably be a gui-less one-shot tool. Maybe the 2D boolean sub-library of CGAL makes sense for polygon-izing? Or modifying the pcb polygon code to run off of gerbv data structures? -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 21, 2010, at 1:08 PM, d...@umich.edu wrote: snip An alternate place in the software tool chain to put a 'DXF' button could be in gEDA's gerber viewer program - gerbv. Under gerbv's 'File' menu, there is an 'Export' command, which gives you the choices to save the file as a PNG, PDF, SVG, or a PostScript file. A 'DXF' choice could be added to the list. Yes, requires constructing polygons from aperture strokes. That's where the rubber meets the road. snip If you convert the backmask or the frontmask files either with the 'gEDA/pcb to dxf' route or the 'Gerber to dxf', you can very quickly have your solder paste mask. Almost. There *is* a paste layer, although it isn't very flexible (I have plans for that, too). The paste layer and the mask layer are not the same. The paste layer reflects only surface pads, not through-hole pads. If you are laser cutting it, I imagine that you might have to do some standard offsetting of the .dxf file outlines in the CAM program to get the dimensions perfect. Yes, currently I use the ps shrinkage to adjust sizes, which isn't perfect. I want to add a paste layer keyword to footprints so that I can control the aperture directly. Ben and Dave, If you are interested in writing some code to add a dxf conversion button to pcb and gerbv, maybe trying these two methods on a few of your own pcb images will give you some ideas. I think creating a backend program that both pcb and gerbv can use would be a good idea. If the starting point is a .ps file, then both programs could use the same backend. The postscript file is a kludgy intermediate step that needs to be eradicated in the 'clean' solution. -dave n6nz ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 20, 2010, at 1:01 PM, Ben Jackson wrote: On Tue, Jan 19, 2010 at 11:56:25PM -0500, d...@umich.edu wrote: I just created a thread on cnczone.com, which I want to bring to your attention. I titled it, Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit: I have been thinking about how to do improved isolation routing. Someone mailed the list a picture where the only cuts were the ones necessary to cut the board into islands congruent with the copper. So imagine you have just two pads on your board. The 'outlines' would cut two boxes. The 'isolation' would just be a line bisecting the board between the two pads. How do you differentiate between pads that must be a certain shape, like for an SMT capacitor, and islands that simply need to be separated? If you want to save something like that directly from PCB, though, the polygon code could do all of your Inkscape steps internally. Ahhh so... does that mean the polygon code could be easily tweaked to produce the vector outlines of all the pads on the paste layer? That would be 95% of what I need for laser cutting solder stencils. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
On Jan 20, 2010, at 10:14 PM, Ben Jackson wrote: On Wed, Jan 20, 2010 at 09:20:34PM -0800, Dave N6NZ wrote: On Jan 20, 2010, at 1:01 PM, Ben Jackson wrote: I have been thinking about how to do improved isolation routing. How do you differentiate between pads that must be a certain shape, like for an SMT capacitor, and islands that simply need to be separated? We're talking about issues of parasitic capacitance here? I wasn't worrying about those issues. No, I was concerned about the shape of the pad w.r.t. correct solder reflow. The shape of the pad and the surface tension of the solder is what pulls the part into place. Assuming, of course, that you are not hand soldering -- but I bought a refurbished toaster oven off Amazon for cheap :) And Target has a nice selection of electric skillets If you want to save something like that directly from PCB, though, the polygon code could do all of your Inkscape steps internally. Ahhh so... does that mean the polygon code could be easily tweaked to produce the vector outlines of all the pads on the paste layer? That would be 95% of what I need for laser cutting solder stencils. The polygon code is fully generic. It can do what you describe (in fact, it does, it just probably doesn't output in the format you want). Hmmm well, point me at the code, and I'll have a look at seeing what it would take to sew in Ribbonsoft's dxflib as a writer. All I really want to do is convert the edges of pads into lines and arcs. This sounds like an exercise in pulling X's and Y's out of pcb and stuffing them into dxflib objects. Assuming I can get arcs for the ends of rounded pads But it can also do the things you did in Inkscape (union areas, etc) Not me, that was the *other* Dave who was using inkscape, the Dave that started this thread. I'm just thread-jacking to talk about paste stencils :) -dave n6nz (the other, other Dave) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit
Hmmm... interesting. I gave your post a quick skim, and will have to go back to read it in detail when I have more time. A while back I created a flow to convert the paste layer to laser cutter code for the creation of solder paste stencils. My path was: 1. print .ps from pcb 2. pstoedit to create a dxf file 3. minor adjustments in QCad, which has the side benefit of cleaning up pstoedit's cheezy .dxf file into something pretty clean. 4. my own code to convert .dxf to laser cutter vectors. For a .dxf reader, I use the GPL'd dxflib that is part of QCad. Note that the essential difference between your goal and my goal is which pcb layer we are starting with. We both want gerber strokes converted into dxf outlines. Re: your comments on strokes. In Postscript, you define a pen and and and end-cap style, and then stroke paths that have been created. Now, in some ways, this is similar to gerbers where you define an aperture and stroke it. In either case, you need to get the outline of the the path. What I've always wanted to do for my stencil program is read the gerbers directly. At the time I originally did my path, that wasn't practical, but the gerbv team has done a major rewrite since then, and in the process library-ified the gerber reader. So I believe the best method for getting gerber to dxf now is: 1. Read gerber using the gerbv library 2. insert magic here to create vector outlines of gerber strokes and flashes 3. Write dxf using QCad's dxflib. As to the magic part... perhaps the 2D constructive solid geometry (CSG) portions of the CGAL library or the OpenCascade library could be used to good effect. I haven't looked deeply at either of them, but I've been skimming over the 3D portion of CGAL, and there you can do CSG unions of various globs and then ask for a mesh back for the hull. I suspect if you poked around the 2D portion of the library you would find the equivalent functionality, ie: CSG unions of 2D shapes, and then ask for the outline back as vectors. It's worth a look. OpenCascade probably has something similar. -dave On Jan 19, 2010, at 8:56 PM, d...@umich.edu wrote: Hey everyone, I just created a thread on cnczone.com, which I want to bring to your attention. I titled it, Schematic Capture to dxf File - using gEDA, Inkscape, and pstoedit: http://www.cnczone.com/forums/showthread.php?t=97677 I think I have worked out a good software tool chain to create .dxf files for milling pcb's. It starts with the gEDA suite of software, uses Inkscape, and then pstoedit. Please, let me know what you think. Thanks, Dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Slots, Swaps and BSDL files
On Jan 8, 2010, at 8:57 AM, John Eaton wrote: Pinlabel is for humans, and for hierarchy. Pinseq is a unique numerical identifier for the pin, independent of the footprint if any (not all symbols correspond to parts with footprints). So slotting lets the PCB designer exchange one 2 input Nand gate for another in the same or different package. Among other things. I use it to split up complex parts into multiple symbols, for instance power and other infrastructure on its own symbol that can go on the relevant page. Swapping lets them swap the two inputs pins. How does the pinseq number do both at the same time? It doesn't. Swapping pins isn't really supported. DJ proposed a new mechanism in the Blue Sky document. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Jan 5, 2010, at 9:31 AM, DJ Delorie wrote: Can't wait to have that one implemented as it's the one point i tripped over with about every software i tried. Just to be clear - by writing down my ideas, I do not mean to imply that I (or anyone else) will actually implement them. But without being written down, it is guaranteed not to be implemented. Now there is a reference document, people can agree (or not), work can be scoped, transition methodologies/plans designed. At some point, someone might even code a patch or three. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Dec 28, 2009, at 9:21 AM, Dave McGuire wrote: Such repairs would be pretty much impossible without the full component- and gate-level schematics I have for these machines, of which this is an example of one page: http://www.neurotica.com/misc/kb11c-117.png You misunderstand me. That's a logical level schematic. Not a physical schematic, where the blocks on the page would be component packages. I don't see any component packages here. I think you would agree that a diagram that was all 14 and 16 pin boxes would me much harder to read than the shovels and shields style logic diagram that you have. Your schematic is exactly what I am advocating (well, except that I prefer ANSI symbols). What I think is useless is a diagram that is packages and pin-outs instead of function and logical flow. One or more high-level logical schematics, block diagrams really form a sort of table of contents for the rest of the schematic. That's a block diagram. The schematics are printed on 11x17 paper. The ones for the PDP-11/70 processor mentioned above are about 300 pages. Yes, PDP-11/70 is a lot of functionality in an impressively small package. 300 sheets is big enough to get lost in if it isn't well organized, but is still a small design. When I talk about making gEDA scale, I want the target to be designs 20x-50x larger. Not that I expect gEDA to take over as an enterprise-class EDA tool, but if people aim high it will lead to a more fundamentally sound design. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Dec 27, 2009, at 9:16 AM, DJ Delorie wrote: On the pin mapping subject I miss an example of the power pins of a rail-to-rail opamp, just to nail these troublemakers down as well (sometimes I get Vss hitched to ground instead of the negative voltage rail). Power pins are not special in my plan, they're just pins. If they're not connected to a symbol, they show up in the other pins table, by name, and you can connect them to whatever you want. I.e. there are NO MORE implied net connections. You just don't need the power symbols any more. OK, DJ, just so I understand what you are saying here... let's run a scenario: User creates a schematic with some op amps and some logic. It's a pretty crazy mix of technologies. User has chosen a methodology where infrastructure is not shown in the schematic. User creates a netlist. Now, someplace there is an other pins table -- where is this exactly? It contains (package,pin) duples of the form: U01 V+ U01 V- U01 GND U02 VCC U02 GND U03 VCC3v3 U03 GND U04 VCC1v8 U04 GND ... and so forth User now needs to somehow specify that U01 GND is connected to analog ground, U01 V+ and V- to analog power rails. U01 GND, U02 GND, U03 GND and U04 GND are connected to digital ground. U02 VCC is connected to 5V, U03 VCC3v3 is connected to 3v3 power, and U04 VCC1v8 s connected to 1v8 power. So is this in some attribute table or something? I'm not suggesting that the above methodology is wise -- IMHO it is a confusing methodology in the long run. But I think it should be supported. I'm unclear what you expect the above user to type and where, though. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Dec 27, 2009, at 2:08 PM, DJ Delorie wrote: User now needs to somehow specify that U01 GND is connected to analog ground, U01 V+ and V- to analog power rails. U01 GND, U02 GND, U03 GND and U04 GND are connected to digital ground. U02 VCC is connected to 5V, U03 VCC3v3 is connected to 3v3 power, and U04 VCC1v8 s connected to 1v8 power. So is this in some attribute table or something? I'm not exactly sure what's best here, but I know it doesn't belong in the *gate*. Minnesota accentYuppers/Minnesota accent My current methodology would have an infrastructure bubble on some back sheet that connects up the power and ground pins for each package. But now since package selection can be deferred, that doesn't work so hot, unless we extend the idea of back-annotation to include creation of schematic sheets. Which I'm OK with. My idea is to have a table object that shows up in the schematic, like in a corner or something, that lists all the power pins and what nets they connect to. I've seen other schematics with this, it seemed much cleaner than what we do. Yes, that makes sense. But again, the table can get populated at layout time. So I'm thinking the table is just a graphical place-holder to contain back-annotation information. The user can place the table(s) on some sheet, and it gets updated by down-stream tools for back-annotation. Actually this is starting to sound like embedding a gattrib grid on a sheet some place. Which might be a reasonable generalization of the functionality. How we populate the table, who is responsible for it, how the user edits it - if it's even in the schematic at all - is TBD. Heck, you don't even know what the power pins *are* until you've selected a package, and that's way down the line flow-wise. Also, consider that there are some things that will no doubt have to be set by the user, and some things that can't be set by the user but only by back-annotation, and somethings where the user will want the option to specify a locked override that a back-end tool can't scribble onto. But I think you want to see all the settings in one place. In the case of something like TTL, I could see there being two tables, one where each row is a symbol instance, and a second table where the rows are package instances, for stuff that goes with the package. I'm not sure how that maps to modern FPGA or gate-array design, my GA design experience is too stale. Now that I think about it once upon a time I worked with a system that did common signal matching. In that case, the infrastructure signals showed up on *every* bubble, and the tool that mapped to packages would match on shared signals (which clock, which clock-enable, mainly, but it could be any arbitrary signal). So there is a counter-example to the assertion that infrastructure does not belong on the bubble. I'm not convinced it's a killer methodology, though. As an aside, support for a table of pin mappings opens itself up to FPGA mappings, too - just supply a CSV instead of trying to map it to a schematic. Instead of a table in the schematic, there could be a see file foo.csv symbol that all the tools could be wise too. But I'd rather see the contents of the file sensibly displayed in the schematics. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Dec 27, 2009, at 6:00 PM, DJ Delorie wrote: Actually this is starting to sound like embedding a gattrib grid on a sheet some place. Can gattrib map pins to nets already? Well, not that I know of. But having a grid display of row-organized data that captures interesting stuff about instances is gattrib-ish. So I was just imagining a gschem symbol that behaved similarly to the gattrib tool. Editing attributes and editing infrastructure pin assignments seemed like a similar workflow. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Dec 27, 2009, at 6:12 PM, gene glick wrote: DJ Delorie wrote: I'm not exactly sure what's best here, but I know it doesn't belong in the *gate*. My idea is to have a table object that shows up in the schematic, like in a corner or something, that lists all the power pins and what nets they connect to. I've seen other schematics with this, it seemed much cleaner than what we do. I think you are advocating the logical view schematic (as opposed to a physical view). BTW, John Doty does this for his connectors - as I recall. A schematic represents different things to different people: The technician likes the symbols to closely resemble the physical parts. It makes working on the board easier since he doesn't need data sheets in addition to the schematic. Physical schematics don't scale. Only logical schematics scale. The tech, actually anybody that comes in contact with the physical hardware, needs pin/card/chassis information to navigate the hardware. That's why back-annotation of layout information is extremely important. But a physical schematic of over a few sheets is unreadable. Nobody can make sense of that. By 'scale' consider that in the 1980's I worked on a CPU where for the bring-up floor we had of the luxury of two complete sets of schematics printed out on paper. Each set of schematics was collected into a couple of dozen 3 inch thick binders, which lived in rolling carts. Good, automated, back-annotation of physical and cross-reference information is the only thing that made dealing with that mass of data practical. Mostly, I remember chasing things down with microfische versions of the schematics -- paper print outs were just too cumbersome to deal with. When sitting at a 'fische reader, Xref again is indispensable. And it has to be automated, there isn't enough man-power in the universe to keep it up to date for a design of any meaningful size. After than, CPU's got too big to ever print the entire set of schematics on paper again. Anybody that wants physical schematics has never worked on anything larger than a homework assignment. In general, gEDA hasn't faced up to its scalability issues. Which is OK for most current gEDA users, including me. But scalability is a necessary in the long term. Slot/pin mapping is a necessary precursor to scalability. Likewise, a live connection to the company parts database is necessary for a modern schematic editing package. There's a few other issues in the way of scalability, but I'll get off my soapbox and avoid splitting the thread into a discussion of those issues, too. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On Dec 27, 2009, at 8:22 PM, Dave N6NZ wrote: On Dec 27, 2009, at 6:00 PM, DJ Delorie wrote: Actually this is starting to sound like embedding a gattrib grid on a sheet some place. Can gattrib map pins to nets already? Well, not that I know of. But having a grid display of row-organized data that captures interesting stuff about instances is gattrib-ish. So I was just imagining a gschem symbol that behaved similarly to the gattrib tool. Editing attributes and editing infrastructure pin assignments seemed like a similar workflow. -dave Yes, I'm responding to myself -- another thought just occurred to me. Good schematic systems have the ability to keep the attributes (and I'm going to throw slot/pin mapping into that generalization) in separate files that are separately rev'ed. This is something that I could use right here and now with gEDA, even though my designs are tiny. I'm in the habit of doing certain boards as through-hole to get an easy to hack prototype, and come back later with an SMT version of the board. So I'd like to have one set of schematics, and be able to join it to a set of thru-hole attributes and mappings, or be able to join the same schematics to a set of SMT attributes and mappings. The SMT package usually has different pin numbers from the thru-hole package. In one very good system that I used, the process worked something like this: 1. Bring up a particular revision of a particular schematic file. This revision of the schematics could have multiple attribute files it could join with. Each of those attribute files could be separately rev'ed. 2. Join a particular rev of a particular attribute file. 3. Work 4. Save rev of attribute file if all you changed was attributes or... 4b. Fork a new attribute file base rev. 4c. If you changed schematics, save or fork schematics, and also the base rev of an attribute file that was automatically forked when you changed the schematics. So for slot/pin mapping, I'm pretty sure I'd like to have a similar mechanism. This kind of argues for a file on the side instead of embedding the data in the drawing file. OK, so I'm being inconsistent :) -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
On component databases: Not sure that I have a lot to add, except that when I read it I was looking specifically for the proposed database hookup and found the right answer :) I already have a SQL database for parts, so I'd like to be able to write a quick lib.so in C that hooks up to gschem providing the part lookup function, which results in sensible menus and drop-down lists generated on the fly from current database information. I suspect many people are in the same place. My database will probably need to be extended because it doesn't capture all the physical information at this point, but it would be worth updating my database to get the functionality. On pin def's: Yes, we've been missing that intermediate layer. Your proposal captures anything I've had to say about it in the past. Power/gnd pins, or to generalized: 'infrastructure pins shared across slots', are the knotty part of the problem. They break encapsulation for slots, or in nomenclature of your proposal, swappable groups. Aside from the 'infrastructure pin' problem, your syntax seems reasonable to me. I'm trying to picture how symbols for slotted parts are going to work. When I started with gEDA, I put implied power/ground connections into my symbols so that they would automagically appear in the net list. I've since concluded that is a Bad Idea, but I'm sure some people will want to do that for some things in the future just because they like that methodology, and if it works for them, it should be supported. My current methodology is to have a symbol for the slotted function, and a symbol for the infrastructure. So, for your example of the 74x00 part, I would have three symbols: a positive-logic NAND symbol that maps to 4 slots, a negative-logic NOR symbol that maps to 4 slots, and an infrastructure symbol that brings out power/ground. My current methodology is to put all the power/ground symbols on some sheet(s) in the back of the stack where they don't clutter up the rest of the design. So, it would be nice if there was some way a rule checker could say that 'package X is missing required infrastructure connections' if I forget to add the pwr/gnd symbol for package or h0rk up the package assignment attribute. Maybe this falls out of the netlister messages, but I suspect the messages will be pretty cryptic unless the netlister has some information to help it along. (*) And if you are going this far, I would want to be able to add two more symbols for my 74x00's, that being inverters in both representations. Those symbols would tie the two input pins together, and map the symbol to a slot in the 74x00. In this case, I would want both pin numbers to be back-annotated onto the input pin in the schematic. Of course, bubble-gum logic is little used any more, but I think some of these concepts would apply to gate-array and FPGA design. Your proposed enhancements would certainly move gEDA in the direction of scalability, and there is a potential to make it more turn-key as well. -dave (*) I'm imagining an attribute that is an assertion that can be checked by the netlister. The assertion should be able to provide it's own error message. At first blush, this sounds like a lot of work. On Dec 26, 2009, at 7:11 PM, DJ Delorie wrote: I took the time to document my ideas about heavy vs light symbols and the pin mapping problem: http://www.delorie.com/pcb/component-dbs.html http://www.delorie.com/pcb/pin-mapping.html I got tired of looking it up in the mail archives or referencing it as some time in the past If you remember me saying more about these than I wrote down, and can find it in the mail archives, let me know so I can add to them. DJ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: large (29 inch) boards?
On Dec 22, 2009, at 2:08 PM, phil wrote: I'm trying to find a shop that will make 29 long boards. They are simple 1/16 two layer boards and will have card edge connectors. Is there a known vendor for this type of work I suspect any of them can do any board that fits in a panel, and the panels they use are huge. It will cost you, though. Send e-mails for quotes and see what you get back. A lot will depend on how good the registration needs to be between layers. Back in the days when I was a CPU designer, we did backplane boards much larger than that. I once spec'ed out an impedance controlled (IOW: very thick) PCB that was 42 x 6. Yes, everybody thought I was nuts. I probably was/am, but let me tell you with an impedance controlled PCB, and passive pull-up/pull-down termination at both ends, the signal edges were text-book clean. I don't remember what it cost, but that was ages ago so it wouldn't be useful information today. For that matter, the box it went into sold for a cool $1M, and only used 6 of these boards, so it didn't matter then, either :) -dave ? Thank you, Phil Taylor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Reducing the amount of jumpers
Link wrote: I've designed a circuit that I'm planning to home-fab, and as such, I've had to design my board using only a single layer. After about a week or so of puzzling, I've managed to route it. Unfortunately, it looks like I'll need a metric craptonne of jumper wire, and I was hoping someone could help me get rid of a few of those jumpers. I didn't look at the picture, but a generic piece of advice is that a component lead (I'm assuming a through-hole board -- I told you I didn't look :) is as good as a jumper. You might make some looong footprints for two-lead components so that you can route more tracks under them. After all, DigiKey sends you all that wire that just gets clipped off... But... why not go two layers? Disclaimer: I send boards out these days, I'm of the life's too short school on that... but if you drill first then registration shouldn't be outrageously difficult. Put a fiducial on each of the four corners and drill them, that should help. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to deal with single/dual parts?
Bill Gatliff wrote: Now I'm beginning to see the problems with slotting and symbols the way we're doing them now: they unnecessarily tie the concept of a symbol to the concept of a component, because the pin numbers that we currently record in our symbols are also the pin numbers that the component maps to the pins of the component's package. We have munged together the concepts of symbol and component in our symbol files, but can't seem to admit to that. That's the breakage, methinks. Finally, another person gets it. -dave b.g. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to deal with single/dual parts?
My approach would be to use a NAND symbol, a power symbol, and slotting. I'm curious as to why you found slotting problematic? It's no more or less obtuse than the rest of gschem. -dave Bill Gatliff wrote: Guys: I can get TI's LittleLogic NAND gates in single (SN74LVC1G00) and dual (SN74LVC2G00) varieties. At the schematic level, however, I'd prefer to just have a NAND symbol and a separate symbol for the power pins. One way to solve this problem is to have a symbol named sn74lvc1g00.sym for the single-gate case, and sn74lvc2g00-1.sym and sn74lvc2g00-2.sym for the two gates of the dual-gate part. Then just pick--- and re-pick--- the right one as I sort things out at layout time. (Add one symbol each for the power pins). At the moment, I really don't want to deal with much back-end scripting to make selection more automated. And the slotting feature has left a bad taste in my mouth in the past due to errors in the symbol. Given all that, is the three-symbol approach described above the most straightforward way to deal with my situation? Or am I missing something obvious? b.g. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: symbol files
Peter Clifton wrote: On Thu, 2009-11-12 at 16:36 +, Kelvin Gardiner wrote: Hi, I'm trying to create some new AVR symbols. Can the footprint section of a symbol file have more than one footprint listed. If so how is each footprint separated, a tab or comma? snip You could make the symbols lighter - by _not_ including a footprint attribute. OR.. You could make the symbols heavier - by making one copy of the symbol for each type of footprint. That is usually the best option if the pinout changes at all between footprints. Which is what I do. Leave the footprint off the symbol and slap them all in later with gattarib. In the case of AVR's -- It's not clear how much it buys you. The pin #'s are different between DIP and TQFP packages. I suppose if you are going between TQFP and MLF it helps. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
