Re: gEDA-user: Heavy Symbols and such
Dave N6NZ [EMAIL PROTECTED] wrote: Dan McMahill wrote: Steve Meier wrote: There would be a ten million part library for resisters if you rrestrict yourself to a flat file format that limits the expression of the data so that it can't capture natural regularities of that universe of components well, the way I often times see this handled in big companies is there are internal part numbers. Big companies, small companies, and me myself in my garage. Having been pickled in that process over the years, I've come to see it's value. I made myself a small mySQL database that cross-references my part number to manufacturer part numbers, and manufacturer part numbers to Digi-Key and Mouser part numbers. It sounds like a lot of work, but it really does save time in the end. So I attach my part number as an attribute, and generate my kit lists using a dim-witted C program and mySQL. I did the same in the summer. Could you send me your code, maybe we could merge the two database system, and have just one better. Thanks. BTW.. my system can be found here: http://logonex.eu/phpmyadmin/index.php user: guest no password. After login, select the component database. -- Levente http://web.interware.hu/lekovacs ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
i see grouping of pins, not written in any syntax, but in conceptual data ignoring the concept of slots, as to include slots into pin grouping. example of 7430 group 1 inputs A, B, C, D, E, F, G, H input-swappale = yes output Y separate data structure to map pins to footprint pingroups package = DIP example of 7401 group 1 .. 4 inputs A, B inputs-swappable = yes output Y groups-swappable = yes pingroups group 1 Package = DIP, SO pins A:2,B:3,Y:1 Package = CS// chipscale BGA i faked the pins on this one just for example pins A:a1, B:a2, Y:b1 group 2 Package = DIP, SO pins A:5,B:6,Y:4 Package = CS pins A:b2, B:c1, Y:c2 example of some FPGA with 2 8 bit ports group 0 .. 7 bus= A[0:7] bus_re-order = A:yes bus-IO-Vcc = B bus-IO-GND = C group_swappable = yes FPGA_PIN_output_script = xilinx_FPGA_pindef_gen.script // script that gets run to auto generate a pin map for this part. group 8 diff-bus=A[0:7] bus_re-order = A:yes diff-bus_pair-re-order = A:yes diff-bus_pair-P-N-swap = B:no diff-bus-clock = D bus-IO-Vcc = B bus-IO-GND = C group_swappable = yes FPGA_PIN_output_script = xilinx_FPGA_pindef_gen.script // script that gets run to auto generate a pin map for this part. imagine a fanout plugin that connects to a bus in PCB to a BGA and would choose a route that fit to the bus, thus allowing the layout decide the pin mapping :-) pingroups group 0 package = BGAfoo pins = A[0]:D1, A[1]:D2, A[2]:D3, A[4]:E2, ..., B:C2F2, C:F3F4F5 group1 continued.. group 8 package = BGAfoo pins = AP[0]:Z1,AN[0]:Z2, AN[1]:, B:. P and N signify the diff-bus positive and negative sides of the pins This can get really hairy to implement in full but I think that it would be good. by keeping pins simple in gschem the hairiness can be kept in the external scripts used to handle these situations. the pin would have an attribute that would map it to a group say group = A or group = AP[0] just some thoughts Steve On Dec 13, 2007 2:22 PM, Dave N6NZ [EMAIL PROTECTED] wrote: DJ Delorie wrote: Not directly. I've built parts with slots for various input pin permutations. I just realized a few days ago how that trick could be used for pin swapping something like a two-input NAND. And then just last night I was doing pin swapping to get better routability on a 32kx8 SRAM. Let's see... 8 data lines, 15 address lines... 2^23 slots u... The phrase doesn't scale comes to mind. There is a level of abstraction missing. Something like a permutable attribute. So a 74as30 might have: permute=a:1,b:2,c:3,d:4,e:5,f:6,g:11,h:12 as a default, mapping pin names to pin numbers. The net list tool could munge the attribute to a new mapping and then back-annotation is simply replacing the attribute with the new mapping. gschem needs some smarts similar to slotting to put the right pins on the schematics. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
The phrase doesn't scale comes to mind. For memory I manually re-route connections in gschem after figuring out what makes sense in pcb; then load the new netlist and let pcb complain about whatever needs moving to make it so. There is a level of abstraction missing. Something like a permutable attribute. So a 74as30 might have: permute=a:1,b:2,c:3,d:4,e:5,f:6,g:11,h:12 as a default, mapping pin names to pin numbers. The net list tool could munge the attribute to a new mapping and then back-annotation is simply replacing the attribute with the new mapping. gschem needs some smarts similar to slotting to put the right pins on the schematics. In my examples, I've been using sub-slotting for my pin maps. That syntax isn't properly parseable, but perhaps something like this would be... Example 7410: ([1,2,13],12),([3,4,5],6),([9,10,11],8) Where () groups a slot, and [] groups permutable pins? So a dual 2-bit latch might be: ([(1,2),(3,4)],5,6),([(13,12),(11,10)],9,8) Meaning: Two latches: [(1,2),(3,4)],5,6 [(13,12),(11,10)],9,8 Each latch has two permutable cells: [(1,2),(3,4)] Within each cell, there are two sub-slots: 1,2 3,4 The advantage of this is that we can tell gschem to ignore the [] characters and start accepting this syntax *now*, at least for simple parts without sub-slots. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Hmmm well it would be nice if design rule checking had information about the pins. Hooking an lvpecl output up to ttl input isn't going to work very well. Even worse is switching the power and ground on an active device. Is or should drc be part of gschem? Well to me gschem is just one application that uses libgeda. Another application such as gnetlist can run a drc set of rules against a design and it would be nice if libgeda had access to more details about pin expectations (in, out, in/out, logic family, max voltage, part of a differential pair?, if yes to diff pair then is this the compliment of the pair or the standard?) and on and on and on. I am in agreement with the concept of a database conating all of this and more and then the database application could generate symbols that gschem could use and it could also be queeried for the additional info that the drc or netlister could use. In general I am in favior of of automated methods since they can get smarter every year while I am very capable of making the same dumb mistake over and over. Steve Meier DJ Delorie wrote: Does gschem really has to know it's a 2-in AND ? Well, to be pedantic, all it really needs to know is it uses a specific graphical symbol with pins at specific locations. But it wouldn't be much of a SCHEMATIC editor if it couldn't tell *us* that it's a 2-in AND gate. More specific: does gschem has a notion of the and function ? No, but that completely missed my point. *If* the user puts a 2-in and symbol in gschem, all gschem needs to know is that it's that symbol, with a given refdes. Something else can correlate that symbol with a field in a database, mapping in part numbers, pinouts, and footprints, etc. The MEANING of the symbol is irrelevent to gschem, but the IDENTIFICATION as that symbol is relevent. The symbol is to the class of part as the refdes is to the instance of the part. The BOM maps an instance of a part to a member of the class of the part. And another one: does gschem fully grasp the 2-in concept with swapable pins ? Not directly. I've built parts with slots for various input pin permutations. All gschem and pcb have in common is the refdes, pin info and connectivity. Yup. But they, as tools, wouldn't be useful to us if that was all they *could* deal with. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
example of 7430 group 1 inputs A, B, C, D, E, F, G, H input-swappale = yes output Y In my dream universe where pin/slot swapping and a central heavy database exist, that would be: nand8 : [A=1,B=2,C=3,D=4,E=5,F=6,G=11,H=12],Y=8,Vcc=14,GND=7 : TI : SN74ALS30N : DIP-14-300.fp example of 7401 nand2 : ([A=2,B=3],Y=1),([A=5,B=6],Y=4),([A=8,B=9],Y=10),([A=11,B=12],Y=13),Vcc=14,GND=7 : TI : SN74ALS01N : DIP-14-300.fp Longer example of 7400: nand3 : ([A=1,B=2],Y=3),([A=4,B=5],Y=6),([A=9,B=10],Y=8),([A=12,B=13],Y=11),Vcc=14,Gnd=8 : TI : SN74ALS00N : DIP-14-300.fp nand3 : [A=1,B=2],Y=4,Vcc=5,GND=3 : TI : SN64AHC1G00 : SOT-23-t.fp and elsewhere: nand3 : NAND-2-1.sym nand3 : NAND-2-E.sym nand3 : ORN-2-1.sym nand3 : ORN-2-E.sym and elsewhere: TI : SN64AHC1G00 : Digikey : 296-1087-1-ND and elsewhere: Digikey : 296-1087-1-ND : 1 : 0.4000 Digikey : 296-1087-1-ND : 25 : 0.3124 Digikey : 296-1087-1-ND : 100 : 0.2200 Digikey : 296-1087-1-ND : 250 : 0.1500 We still have the problem of hidden power nets, though. I suppose we could have a separate database for those, per part: SN74ALS00N : Vcc : 4.75 : 5.25 SN74ALS00N : GND : 0 : 0 SN74LV00N : Vcc : 1 : 5.5 SN74LV00N : GND : 0 : 0 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Thu, 2007-12-13 at 09:49 -0500, DJ Delorie wrote: Longer example of 7400: nand3 : ([A=1,B=2],Y=3),([A=4,B=5],Y=6),([A=9,B=10],Y=8),([A=12,B=13],Y=11),Vcc=14,Gnd=8 : TI : SN74ALS00N : DIP-14-300.fp nand3 : [A=1,B=2],Y=4,Vcc=5,GND=3 : TI : SN64AHC1G00 : SOT-23-t.fp I'm not sure... is this consistent syntax for all layers of permutation? Shouldn't it be: [([A=1,B=2],Y=3),([A=4,B=5],Y=6),([A=9,B=10],Y=8),([A=12,B=13],Y=11)],Vcc=14,Gnd=8 (Note extra [] around our slot groups). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
I wish it would be that easy. The problem is that the number of io pins that needed for some section of a design is dependent upon how you group board functions together and the number / type of pin on the other devices. But If I could have a program where I could say please mr wizard break that nasty fpga up into the following symbols and here are the rquirements for each symbol. Logic Family, number of differential i/o pins, do the clocks need to be from the same pll, do we need to make use of slight delays from i/o pin to i/o pin etc etc and every year the list gets longer. Yes an autogeneration of symbols would be best and reduce over all headackes. is that pin really on that i/o bank and did i really hook the reference voltage up to the right voltage source. The level of this detail can be hair pulling and then you are frought with fear. waht if I blew it and I mixed my power, ground pins costing a turn of the board and the disposal of a lot of expensive parts. But one of the nice things about fpga's is that when you flip the two differential pins... you just put an inverter into the logic and un-flip them. Steve Meier John Griessen wrote: DJ Delorie wrote: And another one: does gschem fully grasp the 2-in concept with swapable pins ? Not directly. I've built parts with slots for various input pin permutations. All gschem and pcb have in common is the refdes, pin info and connectivity. Yup. But they, as tools, wouldn't be useful to us if that was all they *could* deal with. So, commanding slot changes could be all that is needed for pin swapping. For a FPGA, there wold be so many slots, one might do best just running a search for the other slot with the same two pin numbers in it. Creating a working FPGA slotted symbol would be a job for a program, not a person... Steve? John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
DJ Delorie wrote: The phrase doesn't scale comes to mind. For memory I manually re-route connections in gschem after figuring out what makes sense in pcb; then load the new netlist and let pcb complain about whatever needs moving to make it so. My solution was to run through a bus, even where it wasn't needed for readability. Then the pin swapping is easily accomplished using net names on the bus rippers. For memories, this is actually a pretty good solution. In my examples, I've been using sub-slotting for my pin maps. That syntax isn't properly parseable, but perhaps something like this would be... Example 7410: ([1,2,13],12),([3,4,5],6),([9,10,11],8) Yeah, I obviously didn't think through for the interaction between slots, pin swapping, and share power pins. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
I'm not sure... is this consistent syntax for all layers of permutation? I think the addition of power nets and pin names vs numbers warrants the extra syntax, yes. In summary: [...] means these are permutable and (...) means this is a group. Our current pin swapping only uses (...) to group the slots, with an implied [] around the whole list. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Steven Ball wrote: If we decide that heavy symbols are really needed, it would be nice to have a footprint browser in gschem or something that helps specify when you place the symbol on the schematic that I want this footprint, and here's a preview of what it would look like. Would save a lot of flipping back and forth. -hamster Careful. After all that agreeing with Steve, you're saying heavy symbols as if they drove it. He's saying they should only be generated by it. I don't think we'll find it on ebay. John Griessen PS Why doesn't Steve use spells checkers? Because he knows we know what he's talking about, and time is precious. -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
If the schematic at least initialy uses a generic set of pins then there could exist an application that interfaces to a db that would allow you to select the actual device giving you both the footprint and the symbol with the real pins. Change your mind during layout then have pcb go back reselct the package then using back annotation you would correct the schematic. This would allow designing with a generic set of components and then switching components at simulation time until you get the model working then picking the real package thus finalizing the BOM and generating your initial pcb files and an eco schematic file. Having, an application build fpga symbols and being given options as to how to make legal use of io pins would be very sweet. Being able to take a schematic and build a complex simulation netlist that includes hdl as well as analog and being able to simulate the whole enchalada down to drc rule checking would reduce the number of design flaws. I do like the vission now If iI can figure out the bug that I introduced in my netlister while switching from c code to scripts for inporting schematics. Ohh I don't use spell checkers for most emails especially when talking with engineers is in honor of Ken Thompson and the creat system call. OK if you don't buy that answer then its because I am lazzy and feal that I shouldn't have to standardize my spelling for a language which froze its spelling before the pronounciation froze. But then if I had been required to learn a foreign language in collage I was going to argue c as my native language and english as my second language. Steve Meier its a poor mind that can think of only one way to spell a word John Griessen wrote: Steven Ball wrote: If we decide that heavy symbols are really needed, it would be nice to have a footprint browser in gschem or something that helps specify when you place the symbol on the schematic that I want this footprint, and here's a preview of what it would look like. Would save a lot of flipping back and forth. -hamster Careful. After all that agreeing with Steve, you're saying heavy symbols as if they drove it. He's saying they should only be generated by it. I don't think we'll find it on ebay. John Griessen PS Why doesn't Steve use spells checkers? Because he knows we know what he's talking about, and time is precious. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Steven Ball wrote:
I've been thinking about this a bit, and here's my 2 cents:
gschem and pcb both really just want light symbols/footprints. It
would never really be a good idea to expect to stick one into the
other, I mean, what if you change packages or something? I guess you
could up rev the schematic or whatnot, but I'd prefer that bit of
things to be divorced.
this is where I really disagree. If you change the package, then you
are changing the part. The vendor part number is different, the package
is different, it is not uncommon for the pinout to be different. The
new package has different thermal characterstics. In short, you have
changed the design and I'm a strong believer in the schematic being the
controlling source for a board design.
So, in order to go from gschem to pcb, we have the step of gsch2pcb,
or the 'new' xgsch2pcb. What if the gui was extended such that you
get a list of parts, maybe even a window with a zoomed in part of the
schematic highlighting the part you currently have selected, with
another part of the screen showing possible footprints for this
device? Maybe even tie it into a database off gedasymbols to make use
of all the good work happening there? So, you pick a footprint, maybe
get a preview of what it looks like and a little text box with
details. Then, you could step through and pick footprints for pcb.
If you explicitly specify a footprint the 'old' way via footprint= in
gschem, you could have it skip this pick step. Once you are done,
there ya go, footprints populated for pcb to pull in with a netlist.
You could even go back and change footprints, just like if you were to
change the schematic footprint= and re-gsch2pcb.
Then, you'd just need to maintain a mapping of symbol - footprint
somewhere. I'd love to see this be able to tie into a filesystem, a
database, and even gedasymbols as sources.
its not just that. You'd need to maintain a list that deals with part
number differences, pinout differences, etc.
But the good thing about the current system is it does not preclude you
from using heavy symbols which I pretty much exclusively do.
Of course, that all sounds like work and whatnot, but I'd be willing
to help out.
-Steve
On Dec 5, 2007, at 3:03 PM, Dave N6NZ wrote:
Steve Meier wrote:
Dave,
I have been thinking that the way to do back annotation is to add a
schematic level attribute that is attached to a symbol. Something
like
C 8500 9600 1 180 0 big_fpga-1.sym
{
T 8300 9100 5 10 1 1 180 0 1
refdes=U1
T -100 -100 5 10 1 1 180 0 1
pinswap=a12,g13
}
This could then be used when viewing the schematic or generating a
netlist to swap the two pins.
This seems like a good idea. In fact, it strikes me as very similar
to
the slots concept. With slots, we have numslots, slot, and
slotdef. Perhaps pin swapping has an orthogonal set of attributes.
Of course, pin swapping interacts with slot swapping -- think of our
old
friend the 74xx00 -- four slots, each with swappable inputs within
the slot.
I suppose today one could define 8 slots for a 7400, sounds a little
odd, but the point is you would only use 4 of them at a time. Each
slot
would be defined twice -- once for each possible swap. Obviously, this
leads to combinatorial explosion, but for practical parts it might be
OK. I think the right answer is that slots map pinseq #'s onto
logical
pins, and swaps map the logical pins onto physical pins, which
requires an extra layer of symbolic pin names in between slots and
swaps
that does not currently exist.
I like the idea of the netlister being able to read a file of slot=N
and
swap=N attributes and generate the netlist accordingly. Then after
the
layout is done, gschem could import the same file to update the
attributes to accomplish back-annotation.
And let's not forget my desire to target multiple package pin-outs --
but I think that can be handled by creative use of slots, although
its a
bit of a hack.
-dave
Steve Meier
On Wed, 2007-12-05 at 10:13 -0800, Dave N6NZ wrote:
Steve Meier wrote:
Eventually, I would also like to see being able to define the logic
level for a group of pins, can the pins be used differentialy? if
so
which pins are paired? Can we swap pins if so which ones?
The pin swapping question brings up another of my pet peeves --
when the
same part comes in packages with different pin outs, it needs
different
symbols. Although -- last night it occurred to me that I could use
slots to fake that out. Even if the part isn't slotted, I could
define
a slot for each package pin out.
But it really points out the fact that there is a level of
abstraction
missing in the current symbol definition, and that interacts with
back
annotation from what ever PCB layout tool you are using. Maybe the
netlister needs to be enhanced to be a more interactive
Re: gEDA-user: Heavy Symbols and such
gschem and pcb both really just want light symbols/footprints. this is where I really disagree. If you change the package, then you are changing the part. Do either gschem or pcb need to know that? We think of a project as being controlled by two files: the schematics, and the board. Why not three? Schematics, board, BOM. Does pcb really need to know the vendor part number? Does gschem? All gschem needs to know is, for example, 2-in NAND, and all PCB needs to know is that pin 7 of U2, a TSOP-32, needs to be connected to ... etc. Knowing which combinations of light symbol and light footprint, and the pin mappings thereof, correspond to physical purchasable parts, can be the job of the BOM. its not just that. You'd need to maintain a list that deals with part number differences, pinout differences, etc. I've documented an example of such a database, including the pin mapping problem. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Steve Meier wrote: There would be a ten million part library for resisters if you rrestrict yourself to a flat file format that limits the expression of the data so that it can't capture natural regularities of that universe of components well, the way I often times see this handled in big companies is there are internal part numbers. 123982 = 10k, 5%, 1206, 1/8 W, lead free 123983 = 12k, 5%, 1206, 1/8 W, lead free 123894 = ... then the components group has a list that says here are the approved vendors and their part numbers for 123982. Lets buyers negotiate on price. Designers for the most part probably don't care if that resistor came from vishay, murata, or whoever. Now you've dropped your library size considerably. And for resistors, it can easily be generated by a fairly simple script. From my point of view, when it comes to small run things, it is not that hard to do the translation between spec (package, tolerance, resistance) while I'm ordering parts. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Having the schematic be a generic light symbol is a nice idea with having a BOM/database translate the part. I can see that having one symbol be a micro-controller, and having a part choice stage. either in a BOM or by an attribute added to the schematic. I currently use heavy symbols in gEDA because it is simple to have a BOM generated from the schematics. on the other hand, if i had a robust database driven solution that allowed me to use light symbols and choose parts as I placed or choose in a separate UI for BOM management (gBOMer :-P ), This way if i want to use a AT mega 8, i have a list of variants; the slow part, the fast parts, the parts that have different foot prints. now from PCB lets say we get back annotation through some form of IPC if i get the info on a resistor i specified that in my schematic that i wanted 1/10th watt 1% 330 Ohm resistor, in PCB I could then choose anything from the 0603 variant to the 1206, even a through hole variant because it lets me cross 5 traces and simplify layout. This way my engineering project managers could have a nice interface to the design process, get updates of new parts added, parts removed, this would make our tools even more attractive to commercial users. just some thoughts ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Dan McMahill wrote: Steve Meier wrote: There would be a ten million part library for resisters if you rrestrict yourself to a flat file format that limits the expression of the data so that it can't capture natural regularities of that universe of components well, the way I often times see this handled in big companies is there are internal part numbers. Big companies, small companies, and me myself in my garage. Having been pickled in that process over the years, I've come to see it's value. I made myself a small mySQL database that cross-references my part number to manufacturer part numbers, and manufacturer part numbers to Digi-Key and Mouser part numbers. It sounds like a lot of work, but it really does save time in the end. So I attach my part number as an attribute, and generate my kit lists using a dim-witted C program and mySQL. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Dan McMahill wrote: Steven Ball wrote: I'm a strong believer in the schematic being the controlling source for a board design. That's one approach, and perfectly valid. It works well for simple designs. It communicates all aspects of a design compactly with minimal ambiguity. But: 1) It doesn't scale, and 2) It limits the useful lifetime of a design file. gEDA users need to have a choice of methodologies. The tools should conform to the methodology, not dictate the methodology. For some types of designs, having the schematics control logical function *only*, with underlying technology specified in other ways is what works best. An example would be where the logic design is very complex and outlives the implementation technology. The same design might be re-implemented (probably with small tweaks) in several different processes -- there is a good chance you are reading this e-mail using an example of just that. Keeping physical design out of the schematic is also a valid methodology, and gEDA can't preclude it. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Does gschem really has to know it's a 2-in AND ? Well, to be pedantic, all it really needs to know is it uses a specific graphical symbol with pins at specific locations. But it wouldn't be much of a SCHEMATIC editor if it couldn't tell *us* that it's a 2-in AND gate. More specific: does gschem has a notion of the and function ? No, but that completely missed my point. *If* the user puts a 2-in and symbol in gschem, all gschem needs to know is that it's that symbol, with a given refdes. Something else can correlate that symbol with a field in a database, mapping in part numbers, pinouts, and footprints, etc. The MEANING of the symbol is irrelevent to gschem, but the IDENTIFICATION as that symbol is relevent. The symbol is to the class of part as the refdes is to the instance of the part. The BOM maps an instance of a part to a member of the class of the part. And another one: does gschem fully grasp the 2-in concept with swapable pins ? Not directly. I've built parts with slots for various input pin permutations. All gschem and pcb have in common is the refdes, pin info and connectivity. Yup. But they, as tools, wouldn't be useful to us if that was all they *could* deal with. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Hi DJ and all on the list, On Wed, 2007-12-12 at 20:43 -0500, DJ Delorie wrote: gschem and pcb both really just want light symbols/footprints. this is where I really disagree. If you change the package, then you are changing the part. Do either gschem or pcb need to know that? We think of a project as being controlled by two files: the schematics, and the board. Why not three? Schematics, board, BOM. Does pcb really need to know the vendor part number? Does gschem? All gschem needs to know is, for example, 2-in NAND, and all PCB needs to know is that pin 7 of U2, a TSOP-32, needs to be connected to ... etc. Does gschem really has to know it's a 2-in AND ? More specific: does gschem has a notion of the and function ? And another one: does gschem fully grasp the 2-in concept with swapable pins ? All gschem and pcb have in common is the refdes, pin info and connectivity. Kind regards, Bert Timmerman. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
DJ Delorie wrote: Not directly. I've built parts with slots for various input pin permutations. I just realized a few days ago how that trick could be used for pin swapping something like a two-input NAND. And then just last night I was doing pin swapping to get better routability on a 32kx8 SRAM. Let's see... 8 data lines, 15 address lines... 2^23 slots u... The phrase doesn't scale comes to mind. There is a level of abstraction missing. Something like a permutable attribute. So a 74as30 might have: permute=a:1,b:2,c:3,d:4,e:5,f:6,g:11,h:12 as a default, mapping pin names to pin numbers. The net list tool could munge the attribute to a new mapping and then back-annotation is simply replacing the attribute with the new mapping. gschem needs some smarts similar to slotting to put the right pins on the schematics. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Sat, 2007-12-08 at 07:37 +, Peter TB Brett wrote: I'd be happy to see an obvious extension of this concept: An attribute that lists a number of preselected footprints for this symbol. E.g. the list for a resistor could be 0805, 0402, RES_RM10, VISHAY_S101. The attribute editor would convert this list into a chooser widget. I like that idea. gschem's attribute dialog could use that to be smarter -- it could give you a drop-down combo box for pre-defined choices, and of course let you type in something different as well. That would probably be useful for many attributes with a few sensible defaults. I believe that Peter C was working on this but there were implementation difficulties. I did some work on UI stuff, but the main blocker was not being able to think of a good way to get the knowledge into the system. I don't much like defining file-formats / API, and I couldn't see a neat way to associate possible choices with different attributes. Peter B did help me write some scheme functions which identified a preferred resistor value, and this was going to be a test example for suggestion / validation. It wasn't obvious to me how / where you should configure gschem / libgeda to know that you want attributes attached to something with device=resistor to be validated against the E24 set, or the E12 set etc.. Another (hack) I tried, was footprint selection. I patched PCB to allow running PCB without bringing up its main GUI, but just the library window (via a command line option). The idea was that pcb --choose-component (or whatever) would open up a library chooser, and print names of footprints on stdout / stderr, until the user clicks close. The last printed footprint would be fed into gschem. This helps _list_ footprints available to PCB.. what it doesn't do so well was help you choose them. (PCB needs a graphical footprint preview as part of the library window before that will work well). There appears to be a tracker item for it: [ 1723653 ] Intelligent helper interface for attributes I can't recall why it has priority 9.. but never mind. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Peter Clifton wrote: On Sat, 2007-12-08 at 07:37 +, Peter TB Brett wrote: It wasn't obvious to me how / where you should configure gschem / libgeda to know that you want attributes attached to something with device=resistor to be validated against the E24 set, or the E12 set etc.. Well, for setting up default choices, I was thinking of something pretty dumb and not to different from the way gschem attributes work now. For instance: dropdown = attrname : choice [ , choice ] example: dropdown=footprint:0603.fp,0804.fp,1206.fp So if the gschem attribute editor dialog sees a dropdown attribute, it can associate a dropdown list with the named attribute, and of course allow you to type in something different as well. Also, I think this allows backwards compatible symbols, since a symbol that contains a dropdown attribute won't break anything in older revisions of gschem. Of course, you'd like multiple dropdown attributes and I don't know of gschem is OK with multiple attributes of the same name. Ummm... how this relates to validating against Exx set... I'm not sure what you are referring to. Maybe we are talking about different things. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Wednesday 05 December 2007 21:40:49 Dave N6NZ wrote: Kai-Martin Knaak wrote: On Wed, 05 Dec 2007 11:11:35 -0800, Steve Meier wrote: I tend to create symbols that have a predefined foot print and then only override it at the schemtic level when I need to. Me too. Me three. I'd be happy to see an obvious extension of this concept: An attribute that lists a number of preselected footprints for this symbol. E.g. the list for a resistor could be 0805, 0402, RES_RM10, VISHAY_S101. The attribute editor would convert this list into a chooser widget. I like that idea. gschem's attribute dialog could use that to be smarter -- it could give you a drop-down combo box for pre-defined choices, and of course let you type in something different as well. That would probably be useful for many attributes with a few sensible defaults. I believe that Peter C was working on this but there were implementation difficulties. There appears to be a tracker item for it: [ 1723653 ] Intelligent helper interface for attributes Peter -- Peter Brett Electronic Systems Engineer Integral Informatics Ltd signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Thursday 06 December 2007 00:02:11 Peter Clifton wrote: On Wed, 2007-12-05 at 12:43 -0800, Ben Jackson wrote: On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote: One way you can do this today is to at the schematic level add a footprint attribute to each symbol as you place them. The pain is that if you have a thousand resisters you have to do each one individualy. I basically do this. I place one resistor, mark it 0603, 10k and then I try to only cut'n'paste it from then on. Sometimes I royally screw up my refdes's as a result... Maybe gschem needs a 'copy without refdes' option. I have a vague memory of seeing an auto-increment refdes thing somewhere. In gschem: Attributes - Autonumber text... If it doesn't exist (and I just made it up), would it be useful? It's very useful. Peter -- Peter Brett Electronic Systems Engineer Integral Informatics Ltd signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Wed, 207-12-05 at 17:31 -0800, Dave N6NZ wrote:
I think it would simply annoy me. I have adopted the convention of
including the sheet number in the refdes, e.g.: C22 is a cap somewhere
on sheet 2. Perhaps if I could plug in a script that ran on component
insert events, but no what should it do if I delete one? Should it
try to fill in the hole with the next one?
This is what I was remembering. I've not used it personally, so can't
attest to whether it works still...
From http://www.geda.seul.org/wiki/geda:hse_howto:
Hooks
-
Hooks are a way to define functions that will be called during different
part of a programs execution. In gschem there are (currently) three
different hooks available:
* add-component-hook
* copy-component-hook
* move-component-hook
As their name indicate, they are called at different occasions. When
you add a component add-component-hook is called, etc.
To add a function to be called you simply use the Guile funtion add-hook!.
An example; to run the function auto-uref when you add a component you
simply add the following line, preferrably in ${HOME}/.gEDA/gschemrc:
(add-hook! add-component-hook auto-uref)
So you can potentially hook in a script to do what you want on component
update. Its probably not possible to teach it what the sheet number is,
but how it chooses a new number (whether it fills gaps) should be
reasonably easy to code in the guile script.
I get a vision of gschem having an animated paper clip pop up and say:
I see you are trying to rename a component instance... would you like
me to randomly scramble all your refdes attributes?.
I'm sure that bug would be easy enough to introduce... I could make you
a patch... I'm sure I had code which randomly scrambled _all_ attributes
at one point! ;)
As to the paper clip, I'll leave that job to a bigger sadist than I.
You seem to have shorted GND and \_ENABLE. Would you like me to fix
that for you?
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
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Re: gEDA-user: Heavy Symbols and such
I think it would simply annoy me. I have adopted the convention of including the sheet number in the refdes, e.g.: C22 is a cap somewhere on sheet 2. Perhaps if I could plug in a script that ran on component insert events, but no what should it do if I delete one? Should it try to fill in the hole with the next one? FWIW, this kind of problem was more or less attached in refdes_renum. Take a look at what was done there. I don't recall if it plugs holes, but it *does* start renumbering from the top of the list on each page. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
One way you can do this today is to at the schematic level add a footprint attribute to each symbol as you place them. The pain is that if you have a thousand resisters you have to do each one individualy. I tend to create symbols that have a predefined foot print and then only override it at the schemtic level when I need to. For example I have all my surface mount resisters default to a 402 package. Then, since even these are quasie virtual as in they go ping and are lost for ever when I hand solder them I switch the resistors to an 805 package in place I know I am going to be playing with values. I should note that pcb is very forgiving about not requiring footprint info in the netlists while I think or it has been my experience that pads requires the footprint information. Steve Meier On Wed, 2007-12-05 at 17:02 -0200, Alain M. wrote: Hi, I am new to gEDA, but I used orcad+tango for many years. I would like to suggest something in this light versus heavy library thread: Could it be that when the user inserts a light symbol in the schematic, he also adds a light footprint (in the schematic editor) and from then on, it behaves just as a heavy component? It could be the ideal for many situations... Alain DJ Delorie escreveu: How? My initial thought is something that builds a heavy library from a light one: Input: light/*.sym light/*.fp mapping table: sym | value | device | pinmap | newsym | other-attrs fp | value | device | pinmap | newfp | other-attrs Output: heavy/*.sym heavy/*.fp We need to be able to not only decide which light symbols/footprints to use, but also how to map the light pin numbers to the heavy ones. Ideally, the light/heavy symbols could co-exist, allowing parts to be enlightened (converted from heavy back to light) in order to switch parts, assuming the entities know what they are. This should also allow footprint switches without messing up pin numbers. The tricky part is coming up with a clever database schema so that we can share lots of commonality among part families, while allowing the special cases. Some sort of multi-field wildcard system, I suppose, using manufacturer part numbers (either some family name like 7404, or common name like 1N4001) for device, and including manufacturer/partno columns. The dull boring part is filling in all that information. So, one clever perl script, and one giant SQL database, and we're done! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Hi, I am new to gEDA, but I used orcad+tango for many years. I would like to suggest something in this light versus heavy library thread: Could it be that when the user inserts a light symbol in the schematic, he also adds a light footprint (in the schematic editor) and from then on, it behaves just as a heavy component? It could be the ideal for many situations... Alain DJ Delorie escreveu: How? My initial thought is something that builds a heavy library from a light one: Input: light/*.sym light/*.fp mapping table: sym | value | device | pinmap | newsym | other-attrs fp | value | device | pinmap | newfp | other-attrs Output: heavy/*.sym heavy/*.fp We need to be able to not only decide which light symbols/footprints to use, but also how to map the light pin numbers to the heavy ones. Ideally, the light/heavy symbols could co-exist, allowing parts to be enlightened (converted from heavy back to light) in order to switch parts, assuming the entities know what they are. This should also allow footprint switches without messing up pin numbers. The tricky part is coming up with a clever database schema so that we can share lots of commonality among part families, while allowing the special cases. Some sort of multi-field wildcard system, I suppose, using manufacturer part numbers (either some family name like 7404, or common name like 1N4001) for device, and including manufacturer/partno columns. The dull boring part is filling in all that information. So, one clever perl script, and one giant SQL database, and we're done! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Dave,
Well the netlister needs to be able to read in the schematic files and
eco file and then modify the schematic files. I have a version of a
netlister that generates a netlist the traditional flat netlist way and
then reads in an eco file which it uses to modify the netlist. It isn't
100% so I have had to do some hand modifications but it looks promissing
and has helped me reduce mistakes. Ohh the board was layed out using a
modern version of pads.
I have been thinking that the way to do back annotation is to add a
schematic level attribute that is attached to a symbol. Something like
C 8500 9600 1 180 0 big_fpga-1.sym
{
T 8300 9100 5 10 1 1 180 0 1
refdes=U1
T -100 -100 5 10 1 1 180 0 1
pinswap=a12,g13
}
This could then be used when viewing the schematic or generating a
netlist to swap the two pins.
Steve Meier
On Wed, 2007-12-05 at 10:13 -0800, Dave N6NZ wrote:
Steve Meier wrote:
Eventually, I would also like to see being able to define the logic
level for a group of pins, can the pins be used differentialy? if so
which pins are paired? Can we swap pins if so which ones?
The pin swapping question brings up another of my pet peeves -- when the
same part comes in packages with different pin outs, it needs different
symbols. Although -- last night it occurred to me that I could use
slots to fake that out. Even if the part isn't slotted, I could define
a slot for each package pin out.
But it really points out the fact that there is a level of abstraction
missing in the current symbol definition, and that interacts with back
annotation from what ever PCB layout tool you are using. Maybe the
netlister needs to be enhanced to be a more interactive tool instead of
a one-way translator to make all the work well.
-dave
What are the
power requirements (max and min) use this for drc checking. How about an
attribute that tells if a pin must be connected to a net?
I also agree that flat files really arn't a good way to capture a lot of
relevent information. I shudder thinking about a library of 10 million
resistors one for each manufacturor each package, each value etc.
So a real database that can make symbols heavier at run time is a really
good idea.
Steve Meier
On Tue, 2007-12-04 at 21:25 -0700, Andy Peters wrote:
On Dec 4, 2007, at 8:23 PM, Steve Meier wrote:
What is the deffinition of a heavy symbol? And secondly why put a data
base behind one? I have been pondering this from several levels.
To me, a heavy symbol (or, in the parlance of other EDA packages, a
component) is one that includes footprint information and either a
vendor part number or a company-internal one (which gets mapped to a
vendor part number for ordering). A heavy symbol may also contain a
pointer to a Spice library but I don't use that.
Why is this good?
Simply put: the schematic becomes the master drawing. From the
schematic, one can generate a netlist including package information
for layout and a BOM for parts ordering.
The former is very important. We've seen examples of different flavors
of transistors with different TO-92 pinouts. Things like opamps can
have different pinouts when in different packages.
So one can avoid all sorts of confusion by placing an AD8138ARZ on my
schematic, knowing that it will automatically pull in the expected
footprint (SOIC) and populate the BOM with a valid orderable part
number. We have added the AD8138ARM to the library because we need the
smaller footprint, and this part also has a different internal part
number.
One level is about how heavy large components have become and the
tasks
that are used in building a working programed printed circuit board.
Take a large fpga that has a large number of io pins that can have
many
different functions. these are typically broken up into groups other
wise called banks.
On a bank by bank basis it is possible to sellect the following logic
families
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
LVPECL
Differential 1.5-V HSTL Class I and II
Differential 1.8-V HSTL Class I and II
Differential SSTL-18 Class I and II
Differential SSTL-2 Class I and II
Within a bank a pair of io pins can be used differentialy or as single
ended inputs. At lay out time pin swapping to detangle the netlist
becomes very attractive. Which pins can be swapped?
It's even worse than that, as (certainly with Xilinx) there are plenty
of limitations to pin placement. Some pins are inputs only. You need
to make sure you get your differential polarity correct. You need to
specify particular clock input pins. Differential inputs on Spartan 3E
don't have built-in terminations (but differential I/O does). You need
to avoid using the configuration control pins for most general I/O.
But this, in my
Re: gEDA-user: Heavy Symbols and such
Steve Meier wrote: Eventually, I would also like to see being able to define the logic level for a group of pins, can the pins be used differentialy? if so which pins are paired? Can we swap pins if so which ones? The pin swapping question brings up another of my pet peeves -- when the same part comes in packages with different pin outs, it needs different symbols. Although -- last night it occurred to me that I could use slots to fake that out. Even if the part isn't slotted, I could define a slot for each package pin out. But it really points out the fact that there is a level of abstraction missing in the current symbol definition, and that interacts with back annotation from what ever PCB layout tool you are using. Maybe the netlister needs to be enhanced to be a more interactive tool instead of a one-way translator to make all the work well. -dave What are the power requirements (max and min) use this for drc checking. How about an attribute that tells if a pin must be connected to a net? I also agree that flat files really arn't a good way to capture a lot of relevent information. I shudder thinking about a library of 10 million resistors one for each manufacturor each package, each value etc. So a real database that can make symbols heavier at run time is a really good idea. Steve Meier On Tue, 2007-12-04 at 21:25 -0700, Andy Peters wrote: On Dec 4, 2007, at 8:23 PM, Steve Meier wrote: What is the deffinition of a heavy symbol? And secondly why put a data base behind one? I have been pondering this from several levels. To me, a heavy symbol (or, in the parlance of other EDA packages, a component) is one that includes footprint information and either a vendor part number or a company-internal one (which gets mapped to a vendor part number for ordering). A heavy symbol may also contain a pointer to a Spice library but I don't use that. Why is this good? Simply put: the schematic becomes the master drawing. From the schematic, one can generate a netlist including package information for layout and a BOM for parts ordering. The former is very important. We've seen examples of different flavors of transistors with different TO-92 pinouts. Things like opamps can have different pinouts when in different packages. So one can avoid all sorts of confusion by placing an AD8138ARZ on my schematic, knowing that it will automatically pull in the expected footprint (SOIC) and populate the BOM with a valid orderable part number. We have added the AD8138ARM to the library because we need the smaller footprint, and this part also has a different internal part number. One level is about how heavy large components have become and the tasks that are used in building a working programed printed circuit board. Take a large fpga that has a large number of io pins that can have many different functions. these are typically broken up into groups other wise called banks. On a bank by bank basis it is possible to sellect the following logic families 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL Differential 1.5-V HSTL Class I and II Differential 1.8-V HSTL Class I and II Differential SSTL-18 Class I and II Differential SSTL-2 Class I and II Within a bank a pair of io pins can be used differentialy or as single ended inputs. At lay out time pin swapping to detangle the netlist becomes very attractive. Which pins can be swapped? It's even worse than that, as (certainly with Xilinx) there are plenty of limitations to pin placement. Some pins are inputs only. You need to make sure you get your differential polarity correct. You need to specify particular clock input pins. Differential inputs on Spartan 3E don't have built-in terminations (but differential I/O does). You need to avoid using the configuration control pins for most general I/O. But this, in my estimation, doesn't have anything to do with the heavy vs light symbol debate. We like to break up FPGA symbols into banks. For example, XC3S250E-FT256 has four banks so our symbol is really five parts, one for configuration connections and core power and ground, and four symbols, one for each bank which include VCCIO connectors for that bank. Pin names are as noted in the Xilinx data sheet. This allows for some reasonable options for pin swapping. The other FPGA school-of-thought involves making a logic symbol (or set of symbols) for each design (which of course includes footprint and part number info) with particular FPGA design pins on the correct location in each symbol. By logical symbol I mean that you have, say, one symbol for CPU interface, another for DDR SDRAM interface, a third for Ethernet PHY, a fourth with config/power, etc. The downside of this is pretty obvious: make a change that requires adding pins and it gets
Re: gEDA-user: Heavy Symbols and such
Eventually, I would also like to see being able to define the logic level for a group of pins, can the pins be used differentialy? if so which pins are paired? Can we swap pins if so which ones? What are the power requirements (max and min) use this for drc checking. How about an attribute that tells if a pin must be connected to a net? I also agree that flat files really arn't a good way to capture a lot of relevent information. I shudder thinking about a library of 10 million resistors one for each manufacturor each package, each value etc. So a real database that can make symbols heavier at run time is a really good idea. Steve Meier On Tue, 2007-12-04 at 21:25 -0700, Andy Peters wrote: On Dec 4, 2007, at 8:23 PM, Steve Meier wrote: What is the deffinition of a heavy symbol? And secondly why put a data base behind one? I have been pondering this from several levels. To me, a heavy symbol (or, in the parlance of other EDA packages, a component) is one that includes footprint information and either a vendor part number or a company-internal one (which gets mapped to a vendor part number for ordering). A heavy symbol may also contain a pointer to a Spice library but I don't use that. Why is this good? Simply put: the schematic becomes the master drawing. From the schematic, one can generate a netlist including package information for layout and a BOM for parts ordering. The former is very important. We've seen examples of different flavors of transistors with different TO-92 pinouts. Things like opamps can have different pinouts when in different packages. So one can avoid all sorts of confusion by placing an AD8138ARZ on my schematic, knowing that it will automatically pull in the expected footprint (SOIC) and populate the BOM with a valid orderable part number. We have added the AD8138ARM to the library because we need the smaller footprint, and this part also has a different internal part number. One level is about how heavy large components have become and the tasks that are used in building a working programed printed circuit board. Take a large fpga that has a large number of io pins that can have many different functions. these are typically broken up into groups other wise called banks. On a bank by bank basis it is possible to sellect the following logic families 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL Differential 1.5-V HSTL Class I and II Differential 1.8-V HSTL Class I and II Differential SSTL-18 Class I and II Differential SSTL-2 Class I and II Within a bank a pair of io pins can be used differentialy or as single ended inputs. At lay out time pin swapping to detangle the netlist becomes very attractive. Which pins can be swapped? It's even worse than that, as (certainly with Xilinx) there are plenty of limitations to pin placement. Some pins are inputs only. You need to make sure you get your differential polarity correct. You need to specify particular clock input pins. Differential inputs on Spartan 3E don't have built-in terminations (but differential I/O does). You need to avoid using the configuration control pins for most general I/O. But this, in my estimation, doesn't have anything to do with the heavy vs light symbol debate. We like to break up FPGA symbols into banks. For example, XC3S250E-FT256 has four banks so our symbol is really five parts, one for configuration connections and core power and ground, and four symbols, one for each bank which include VCCIO connectors for that bank. Pin names are as noted in the Xilinx data sheet. This allows for some reasonable options for pin swapping. The other FPGA school-of-thought involves making a logic symbol (or set of symbols) for each design (which of course includes footprint and part number info) with particular FPGA design pins on the correct location in each symbol. By logical symbol I mean that you have, say, one symbol for CPU interface, another for DDR SDRAM interface, a third for Ethernet PHY, a fourth with config/power, etc. The downside of this is pretty obvious: make a change that requires adding pins and it gets ugly. On a second level, even a resistor has limitations. For a given manufacturor of a given product line there exists only a finite number of resistance values? To support manufacturing I would like to know what are the options for a particular package? Can I expect the package to survive the expected power levels? The obvious solution to this is to have heavy symbols for each and every resistor value, package size and tolerance. Of course your resistor library can grow quite large in a hurry, although creating a new symbol is a simple as copying an older one and changing the relevant fields. On a third level, I would
Re: gEDA-user: Heavy Symbols and such
On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote: One way you can do this today is to at the schematic level add a footprint attribute to each symbol as you place them. The pain is that if you have a thousand resisters you have to do each one individualy. I basically do this. I place one resistor, mark it 0603, 10k and then I try to only cut'n'paste it from then on. Sometimes I royally screw up my refdes's as a result... Maybe gschem needs a 'copy without refdes' option. -- Ben Jackson AD7GD [EMAIL PROTECTED] http://www.ben.com/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Steve Meier wrote:
Dave,
I have been thinking that the way to do back annotation is to add a
schematic level attribute that is attached to a symbol. Something like
C 8500 9600 1 180 0 big_fpga-1.sym
{
T 8300 9100 5 10 1 1 180 0 1
refdes=U1
T -100 -100 5 10 1 1 180 0 1
pinswap=a12,g13
}
This could then be used when viewing the schematic or generating a
netlist to swap the two pins.
This seems like a good idea. In fact, it strikes me as very similar to
the slots concept. With slots, we have numslots, slot, and
slotdef. Perhaps pin swapping has an orthogonal set of attributes.
Of course, pin swapping interacts with slot swapping -- think of our old
friend the 74xx00 -- four slots, each with swappable inputs within the slot.
I suppose today one could define 8 slots for a 7400, sounds a little
odd, but the point is you would only use 4 of them at a time. Each slot
would be defined twice -- once for each possible swap. Obviously, this
leads to combinatorial explosion, but for practical parts it might be
OK. I think the right answer is that slots map pinseq #'s onto logical
pins, and swaps map the logical pins onto physical pins, which
requires an extra layer of symbolic pin names in between slots and swaps
that does not currently exist.
I like the idea of the netlister being able to read a file of slot=N and
swap=N attributes and generate the netlist accordingly. Then after the
layout is done, gschem could import the same file to update the
attributes to accomplish back-annotation.
And let's not forget my desire to target multiple package pin-outs --
but I think that can be handled by creative use of slots, although its a
bit of a hack.
-dave
Steve Meier
On Wed, 2007-12-05 at 10:13 -0800, Dave N6NZ wrote:
Steve Meier wrote:
Eventually, I would also like to see being able to define the logic
level for a group of pins, can the pins be used differentialy? if so
which pins are paired? Can we swap pins if so which ones?
The pin swapping question brings up another of my pet peeves -- when the
same part comes in packages with different pin outs, it needs different
symbols. Although -- last night it occurred to me that I could use
slots to fake that out. Even if the part isn't slotted, I could define
a slot for each package pin out.
But it really points out the fact that there is a level of abstraction
missing in the current symbol definition, and that interacts with back
annotation from what ever PCB layout tool you are using. Maybe the
netlister needs to be enhanced to be a more interactive tool instead of
a one-way translator to make all the work well.
-dave
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Re: gEDA-user: Heavy Symbols and such
Ben Jackson wrote: On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote: One way you can do this today is to at the schematic level add a footprint attribute to each symbol as you place them. The pain is that if you have a thousand resisters you have to do each one individualy. I basically do this. I place one resistor, mark it 0603, 10k and then I try to only cut'n'paste it from then on. Sometimes I royally screw up my refdes's as a result... Maybe gschem needs a 'copy without refdes' option. This is where I use gattrib. I set one in gschem, and then do all my attribute copy/pasting in a gattrib pass later on. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
I've been thinking about this a bit, and here's my 2 cents:
gschem and pcb both really just want light symbols/footprints. It
would never really be a good idea to expect to stick one into the
other, I mean, what if you change packages or something? I guess you
could up rev the schematic or whatnot, but I'd prefer that bit of
things to be divorced.
So, in order to go from gschem to pcb, we have the step of gsch2pcb,
or the 'new' xgsch2pcb. What if the gui was extended such that you
get a list of parts, maybe even a window with a zoomed in part of the
schematic highlighting the part you currently have selected, with
another part of the screen showing possible footprints for this
device? Maybe even tie it into a database off gedasymbols to make use
of all the good work happening there? So, you pick a footprint, maybe
get a preview of what it looks like and a little text box with
details. Then, you could step through and pick footprints for pcb.
If you explicitly specify a footprint the 'old' way via footprint= in
gschem, you could have it skip this pick step. Once you are done,
there ya go, footprints populated for pcb to pull in with a netlist.
You could even go back and change footprints, just like if you were to
change the schematic footprint= and re-gsch2pcb.
Then, you'd just need to maintain a mapping of symbol - footprint
somewhere. I'd love to see this be able to tie into a filesystem, a
database, and even gedasymbols as sources.
Of course, that all sounds like work and whatnot, but I'd be willing
to help out.
-Steve
On Dec 5, 2007, at 3:03 PM, Dave N6NZ wrote:
Steve Meier wrote:
Dave,
I have been thinking that the way to do back annotation is to add a
schematic level attribute that is attached to a symbol. Something
like
C 8500 9600 1 180 0 big_fpga-1.sym
{
T 8300 9100 5 10 1 1 180 0 1
refdes=U1
T -100 -100 5 10 1 1 180 0 1
pinswap=a12,g13
}
This could then be used when viewing the schematic or generating a
netlist to swap the two pins.
This seems like a good idea. In fact, it strikes me as very similar
to
the slots concept. With slots, we have numslots, slot, and
slotdef. Perhaps pin swapping has an orthogonal set of attributes.
Of course, pin swapping interacts with slot swapping -- think of our
old
friend the 74xx00 -- four slots, each with swappable inputs within
the slot.
I suppose today one could define 8 slots for a 7400, sounds a little
odd, but the point is you would only use 4 of them at a time. Each
slot
would be defined twice -- once for each possible swap. Obviously, this
leads to combinatorial explosion, but for practical parts it might be
OK. I think the right answer is that slots map pinseq #'s onto
logical
pins, and swaps map the logical pins onto physical pins, which
requires an extra layer of symbolic pin names in between slots and
swaps
that does not currently exist.
I like the idea of the netlister being able to read a file of slot=N
and
swap=N attributes and generate the netlist accordingly. Then after
the
layout is done, gschem could import the same file to update the
attributes to accomplish back-annotation.
And let's not forget my desire to target multiple package pin-outs --
but I think that can be handled by creative use of slots, although
its a
bit of a hack.
-dave
Steve Meier
On Wed, 2007-12-05 at 10:13 -0800, Dave N6NZ wrote:
Steve Meier wrote:
Eventually, I would also like to see being able to define the logic
level for a group of pins, can the pins be used differentialy? if
so
which pins are paired? Can we swap pins if so which ones?
The pin swapping question brings up another of my pet peeves --
when the
same part comes in packages with different pin outs, it needs
different
symbols. Although -- last night it occurred to me that I could use
slots to fake that out. Even if the part isn't slotted, I could
define
a slot for each package pin out.
But it really points out the fact that there is a level of
abstraction
missing in the current symbol definition, and that interacts with
back
annotation from what ever PCB layout tool you are using. Maybe the
netlister needs to be enhanced to be a more interactive tool
instead of
a one-way translator to make all the work well.
-dave
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Re: gEDA-user: Heavy Symbols and such
On Wed, 05 Dec 2007 11:11:35 -0800, Steve Meier wrote: I tend to create symbols that have a predefined foot print and then only override it at the schemtic level when I need to. Me too. (see my combined symbol and footprint lib in gedasymbols.org) I'd be happy to see an obvious extension of this concept: An attribute that lists a number of preselected footprints for this symbol. E.g. the list for a resistor could be 0805, 0402, RES_RM10, VISHAY_S101. The attribute editor would convert this list into a chooser widget. I found the corresponding feature in protel very handy. Only thing I would gripe about was that the maximum number of preselected footprints in protel was four. ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Dave N6NZ wrote: Ben Jackson wrote: On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote: One way you can do this today is to at the schematic level add a footprint attribute to each symbol as you place them. The pain is that if you have a thousand resisters you have to do each one individualy. I basically do this. I place one resistor, mark it 0603, 10k and then I try to only cut'n'paste it from then on. Sometimes I royally screw up my refdes's as a result... Maybe gschem needs a 'copy without refdes' option. This is where I use gattrib. I set one in gschem, and then do all my attribute copy/pasting in a gattrib pass later on. If you use gsch2pcb, then if gattrib could sort on several terms, you could update a thousand resistors in one spreadsheet command in gattrib. JOhn G -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Wed, 2007-12-05 at 12:43 -0800, Ben Jackson wrote: On Wed, Dec 05, 2007 at 11:11:35AM -0800, Steve Meier wrote: One way you can do this today is to at the schematic level add a footprint attribute to each symbol as you place them. The pain is that if you have a thousand resisters you have to do each one individualy. I basically do this. I place one resistor, mark it 0603, 10k and then I try to only cut'n'paste it from then on. Sometimes I royally screw up my refdes's as a result... Maybe gschem needs a 'copy without refdes' option. I have a vague memory of seeing an auto-increment refdes thing somewhere. If it doesn't exist (and I just made it up), would it be useful? -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Peter Clifton wrote: I have a vague memory of seeing an auto-increment refdes thing somewhere. If it doesn't exist (and I just made it up), would it be useful? I think it would simply annoy me. I have adopted the convention of including the sheet number in the refdes, e.g.: C22 is a cap somewhere on sheet 2. Perhaps if I could plug in a script that ran on component insert events, but no what should it do if I delete one? Should it try to fill in the hole with the next one? I get a vision of gschem having an animated paper clip pop up and say: I see you are trying to rename a component instance... would you like me to randomly scramble all your refdes attributes?. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Steve Meier wrote: An argument for the marriage of pcb and gschem at least in the file processing is in being able to have a simulation that includes the layout. And when the marriage stays at the file processing level, you can interoperate with other tools, OSS or store-bought. John G -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Wednesday 05 December 2007 06:33:43 pm Steven Ball wrote: I've been thinking about this a bit, and here's my 2 cents: gschem and pcb both really just want light symbols/footprints. It would never really be a good idea to expect to stick one into the other, I mean, what if you change packages or something? I guess you could up rev the schematic or whatnot, but I'd prefer that bit of things to be divorced. The BOM should be the master document that populates everything. If you have to deal with ISO9000 et.al. you don't want to be changing your schematic because a vendor decided to stick a K on the end of a part number to represent that it is Lead Free (and why a K?). Obviously people on this list are dealing with schematics and PCBs, so we tend to think of the schematic as the master, but in the contracting environment the BOM is what rules everything. Then, you'd just need to maintain a mapping of symbol - footprint somewhere. I'd love to see this be able to tie into a filesystem, a database, and even gedasymbols as sources. This might be of interest to the Lite vs Heavy group: The Mumps Compiler and Multi-Dimensional and Hierarchical Toolkit http://cns2.uni.edu/~okane/source/MUMPS-MDH/compiler.html This drawings there explain it better, but this is what people have been referring to, without realizing there was a specific language for it for textual hierarchies. Think of something like this: set ^project(^bom(^schematic(revision,refdes,footprint)))=0603 Quoting from the above URI: Here, the tree is named patient which is also the name of the global array (notice that global arrays always have a circumflex (^) preceding their name). The Mumps code to populate the above might look like: set ^patient(123-45-6789)=Jones, John, J set ^patient(123-45-6789,Demographics,Street)=123 Elm St set ^patient(123-45-6789,Demographics,City)=Anytown set ^patient(123-45-6789,Demographics,State)=IA set ^patient(123-45-6789,Demographics,ZIP)=50613 set ^patient(123-45-6789,Dx,789.00,6/23/2005)=Dr Smith set ^patient(123-45-6789,Dx,789.00,6/23/2005,lab,HCT,6/23/2005,10:45,45.2)= set ^patient(123-45-6789,Dx,789.00,6/23/2005,lab,HCT,6/23/2005,20:45,43.2)= set ^patient(123-45-6789,Dx,789.00,6/23/2005,lab,HCT,6/24/2005,21:10,44.2)= set ^patient(123-45-6789,Dx,789.00,6/23/2005,lab,HCT,6/25/2005,14:10,44.2)= Global arrays are unique to Mumps ['Global' has a unique meaning in MUMPS]. As a programmer, you will work with them as though they were arrays. [They are spars arrays.] The system, however, interprets them as tree path descriptions for the system's external data files. A global array is distinguished by beginning with the circumflex character (^). The remainder of the specification is the same as an internal array. global arrays are not dimensioned and they may appear anywhere an ordinary variable may appear (except in certain forms of the kill command). A typical global array specification consists of the array name followed by some number of indices (indices may be constants, variables [including internal or global arrays] or expressions of string, numeric or mixed type). For example: set ^a(1,43,5,99)=TEST set ^ship(1ST FLEET,BOSTON,FLAG)=CONSTITUTION set ^captain(^ship(1ST FLEET,BOSTON,FLAG))=JONES set ^home(^captain(^ship(1ST FLEET,BOSTON,FLAG)))=PORTSMOUTH write ^ship(1ST FLEET,BOSTON,FLAG) ... CONSTITUTION write ^captain(CONSTITUTION) ... JONES write ^home(JONES) ... PORTSMOUTH write ^home(^captain(CONSTITUTION)) ... PORTSMOUTH write ^home(^captain(^ship(1ST FLEET,BOSTON,FLAG))) ... PORTSMOUTH The system files are viewed as trees. Each global array name (A, SHIP, CAPTAIN, and HOME in the above) is the root of a tree. The indices are thought of as path descriptions to leaves. For example, out of the root ^a there may be many branches, the above specifies to take the branch labeled 1 (note: this does not mean the first branch out of the node - it means the branch with label 1). At the second level the specification says to take the branch labeled 43 (note: this does not imply that branches 1 through 42 necessarily exist). The path description is followed (or, possibly, created if the global array specification appears on the left hand side of an assignment statement or in a read command) to a final node. The value at the node is either retrieved or a new value stored depending upon the context in which the global array specification was used. The indices of global arrays may be numeric or character strings. The second sequence of examples above illustrates this usage. This MUMPS compiler converts MUMPS to C++. http://judy.sf.net might also be of interest as it is in C, as it is an other spars array system. -- http://www.wearablesmartsensors.com/
Re: gEDA-user: Heavy Symbols and such
A common danger in a divorced system is that you pick one package in
gschem and opps a different package for PCB and now your land pattern
wires are wrong for the schematic.
So unless the translator program is checking package to symbol
correctness then be prepared to dead bug. Or else re-fab.
Plus this whole issue is much larger then just footprints and symbols.
Just off the top of my head it includes back annotation, simulation,
design rule checking, bom generation with vendor part numbers and
correct legal value selection.
An argument for the marriage of pcb and gschem at least in the file
processing is in being able to have a simulation that includes the
layout.
Steve Meier
On Wed, 2007-12-05 at 16:33 -0700, Steven Ball wrote:
I've been thinking about this a bit, and here's my 2 cents:
gschem and pcb both really just want light symbols/footprints. It
would never really be a good idea to expect to stick one into the
other, I mean, what if you change packages or something? I guess you
could up rev the schematic or whatnot, but I'd prefer that bit of
things to be divorced.
So, in order to go from gschem to pcb, we have the step of gsch2pcb,
or the 'new' xgsch2pcb. What if the gui was extended such that you
get a list of parts, maybe even a window with a zoomed in part of the
schematic highlighting the part you currently have selected, with
another part of the screen showing possible footprints for this
device? Maybe even tie it into a database off gedasymbols to make use
of all the good work happening there? So, you pick a footprint, maybe
get a preview of what it looks like and a little text box with
details. Then, you could step through and pick footprints for pcb.
If you explicitly specify a footprint the 'old' way via footprint= in
gschem, you could have it skip this pick step. Once you are done,
there ya go, footprints populated for pcb to pull in with a netlist.
You could even go back and change footprints, just like if you were to
change the schematic footprint= and re-gsch2pcb.
Then, you'd just need to maintain a mapping of symbol - footprint
somewhere. I'd love to see this be able to tie into a filesystem, a
database, and even gedasymbols as sources.
Of course, that all sounds like work and whatnot, but I'd be willing
to help out.
-Steve
On Dec 5, 2007, at 3:03 PM, Dave N6NZ wrote:
Steve Meier wrote:
Dave,
I have been thinking that the way to do back annotation is to add a
schematic level attribute that is attached to a symbol. Something
like
C 8500 9600 1 180 0 big_fpga-1.sym
{
T 8300 9100 5 10 1 1 180 0 1
refdes=U1
T -100 -100 5 10 1 1 180 0 1
pinswap=a12,g13
}
This could then be used when viewing the schematic or generating a
netlist to swap the two pins.
This seems like a good idea. In fact, it strikes me as very similar
to
the slots concept. With slots, we have numslots, slot, and
slotdef. Perhaps pin swapping has an orthogonal set of attributes.
Of course, pin swapping interacts with slot swapping -- think of our
old
friend the 74xx00 -- four slots, each with swappable inputs within
the slot.
I suppose today one could define 8 slots for a 7400, sounds a little
odd, but the point is you would only use 4 of them at a time. Each
slot
would be defined twice -- once for each possible swap. Obviously, this
leads to combinatorial explosion, but for practical parts it might be
OK. I think the right answer is that slots map pinseq #'s onto
logical
pins, and swaps map the logical pins onto physical pins, which
requires an extra layer of symbolic pin names in between slots and
swaps
that does not currently exist.
I like the idea of the netlister being able to read a file of slot=N
and
swap=N attributes and generate the netlist accordingly. Then after
the
layout is done, gschem could import the same file to update the
attributes to accomplish back-annotation.
And let's not forget my desire to target multiple package pin-outs --
but I think that can be handled by creative use of slots, although
its a
bit of a hack.
-dave
Steve Meier
On Wed, 2007-12-05 at 10:13 -0800, Dave N6NZ wrote:
Steve Meier wrote:
Eventually, I would also like to see being able to define the logic
level for a group of pins, can the pins be used differentialy? if
so
which pins are paired? Can we swap pins if so which ones?
The pin swapping question brings up another of my pet peeves --
when the
same part comes in packages with different pin outs, it needs
different
symbols. Although -- last night it occurred to me that I could use
slots to fake that out. Even if the part isn't slotted, I could
define
a slot for each package pin out.
But it really points out the fact that there is a level of
abstraction
missing in the current symbol definition, and
Re: gEDA-user: Heavy Symbols and such
Bob Paddock [EMAIL PROTECTED] wrote: The BOM should be the master document that populates everything. [...] Obviously people on this list are dealing with schematics and PCBs, so we tend to think of the schematic as the master, but in the contracting environment the BOM is what rules everything. Yes, you've hit the nail right on the head! That's exactly how I do it in uEDA, gEDA's evil twin. In uEDA the master source code for a board is an ASCII text file named MCL, which stands for Master Component List. It is not a generated file and it isn't edited by any GUI, instead you create and edit it in vi and source-control it with SCCS/RCS/CVS/pick-your-favourite. The MCL is where you enter footprints, cap resistor values, orderable part numbers, etc. uEDA has no GUI though, *all* design entry is done in vi. When the uEDA suite is complete, you'll be able to enter your design in vi, then run 'make' and get: * A bundle of M4-generated PCB footprints to hand over to your PCB layout contractor; * Various BOM forms (the MCL is a BOM in itself, but there are other BOM forms too that can be generated from it); * Printable schematics in PostScript; * Netlist file to be loaded into PCB (by you or your layout contractor). The first 2 bullet points are there already, the last 2 aren't there yet. I plan to implement the latter by designing a gschem-like ASCII-based schematic source code format, but with one critical difference from the gschem one: instead of attributes in the schematic source file itself, all that information will be taken from the MCL. The complete source code for a board will thus consist of the MCL, the *.usch schematic source files (one per page just like gschem's *.sch) and the Makefile. The MCL and the Makefile form the top-level notion of project which some people complain the gEDA suite lacks. MS ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Wed, Dec 05, 2007 at 08:07:45AM +0100, Bert Timmerman wrote: I think we should not create heavy symbols on build time but during run time (when the part is needed). +1 What's the difference between a light symbol and a heavy one? It's just that the heavy symbol has more attributes that specify it for a particular component in various ways, no? And so it's really just about what you begin with when you add a new symbol to the schematic, unless you expect that a heavy were resistant to being edited (those heavy attributes nailed down as it were) or... other things? Levente Kovacs has set up a database concept which could be expanded on (the bookmarked link I have does not seem to work anymore). In this way we could have both: generic light symbols and single purpose heavy symbols. My thinking so far - and it's certainly not complete! - has been that with a bit of care light and heavy symbols should play nicely together. It may not be this simple when all's done - the discussion about FPGAs suggests there may be inherent complications I'm not thinking of yet. It's certainly not so simple to the extent that the schematic editor needs to do stuff (beyond editing and maybe displaying) with the attributes... See also: http://www.seul.org/pipermail/geda-dev/2007-September/003665.html Might be copies of the files at http://web.interware.hu/lekovacs/ - try poking in the Public files section. I'm not sure what's going on there - clicking on things seems to cause unexpected changes, and some intriguing filenames vanished and I couldn't get them back again... -- You arguably have quite a few inalienable rights, but being taken seriously isn't one of them. Neither is being respected. -- Rick Moen linuxmafia.com/~rick/faq/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
What's the difference between a light symbol and a heavy one? It's just that the heavy symbol has more attributes that specify it for a particular component in various ways, no? No. You also need to adjust pin numbers to match the symbol's pins to the footprint's pins, one of our current sore spots. That includes such things as slotting. For instance, a 2-in NAND could be (1,4,9,12), (2,5,10,13), (3,6,8,11) for SN74ALVC00NSR, but 1,2,4 for NC7S00M5X in SOT23 (but the micropak numbers Vcc as pin 6, not pin 5) or (1,7), (2,6), (3,5) for CD40107BE. Plus, different vendors might number the pins on a SOT23-5 differently. Some use 1,2,3,4,5; others use 1,2,3,4,6 (leaving '5' for the missing pin). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Wed, Dec 05, 2007 at 09:56:41AM -0800, Steve Meier wrote: I also agree that flat files really arn't a good way to capture a lot of relevent information. I shudder thinking about a library of 10 million resistors one for each manufacturor each package, each value etc. This reminds a little of something I stole for the sig-quote database (which is just a bunch of flat files, as it happens, but nowhere near a million of them grin): This is like making a car shorter by cutting off a few inches from each end with a Sawzall. Of course there's little benefit, because that's a dumb way to do it. There would be ten million resistor symbols only if you ignore the natural regularities of that universe of components. This does require a little more logic, to apply the reduced volume of tabular data appropriately. And, yeah, those things are a little ad-hoc. And some things will be so much their own weird thing that they do need a totally unique description per part. blinkSo it goes./blink -- And in the end, reality always tends to hit theory hard in the face when you least expect it. - Linus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
There would be a ten million part library for resisters if you rrestrict yourself to a flat file format that limits the expression of the data so that it can't capture natural regularities of that universe of components Which was my point and why DJ got a bingo for the db reasoning. Yes heavy and flat is reminicent of a particular character from the movie animal house. being fat dumb and drunk is no way to go through life. But engaging in anorexic behavior to avoid the preceeding idea is also no way to go through a design cycle. Or one of my favorite Alaskan climbing quotes is from a conversation I once had with a character named Carl Tobin I said, the common idea from alpine climbing is to go fast and light. Carl responded in Alaska we say... Go fast and heavy. Steve Meier Martin Maney wrote: On Wed, Dec 05, 2007 at 09:56:41AM -0800, Steve Meier wrote: I also agree that flat files really arn't a good way to capture a lot of relevent information. I shudder thinking about a library of 10 million resistors one for each manufacturor each package, each value etc. This reminds a little of something I stole for the sig-quote database (which is just a bunch of flat files, as it happens, but nowhere near a million of them grin): This is like making a car shorter by cutting off a few inches from each end with a Sawzall. Of course there's little benefit, because that's a dumb way to do it. There would be ten million resistor symbols only if you ignore the natural regularities of that universe of components. This does require a little more logic, to apply the reduced volume of tabular data appropriately. And, yeah, those things are a little ad-hoc. And some things will be so much their own weird thing that they do need a totally unique description per part. blinkSo it goes./blink ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
It is an animated inductor, it gets very depressed when you call it a paperclip! It wishes that it had a iron core, but alas it is air core. :-) On Dec 6, 2007 9:31 AM, Dave N6NZ [EMAIL PROTECTED] wrote: Peter Clifton wrote: I have a vague memory of seeing an auto-increment refdes thing somewhere. If it doesn't exist (and I just made it up), would it be useful? I think it would simply annoy me. I have adopted the convention of including the sheet number in the refdes, e.g.: C22 is a cap somewhere on sheet 2. Perhaps if I could plug in a script that ran on component insert events, but no what should it do if I delete one? Should it try to fill in the hole with the next one? I get a vision of gschem having an animated paper clip pop up and say: I see you are trying to rename a component instance... would you like me to randomly scramble all your refdes attributes?. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Dave, That left me sputtering. May I suggest an upgrade. First that paper clip should mearly pop up, wink and say I got ya! Then the hunt is on and you need to figure out did a refdes change? A foot print? a value? hey any attribute is fair game. Steve Meier Steven Michalske wrote: It is an animated inductor, it gets very depressed when you call it a paperclip! It wishes that it had a iron core, but alas it is air core. :-) On Dec 6, 2007 9:31 AM, Dave N6NZ [EMAIL PROTECTED] wrote: Peter Clifton wrote: I have a vague memory of seeing an auto-increment refdes thing somewhere. If it doesn't exist (and I just made it up), would it be useful? I think it would simply annoy me. I have adopted the convention of including the sheet number in the refdes, e.g.: C22 is a cap somewhere on sheet 2. Perhaps if I could plug in a script that ran on component insert events, but no what should it do if I delete one? Should it try to fill in the hole with the next one? I get a vision of gschem having an animated paper clip pop up and say: I see you are trying to rename a component instance... would you like me to randomly scramble all your refdes attributes?. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Heavy Symbols and such
I am becomming more and more a proponent of heavy symbols or even a data base then can generate heavy symbols. One of the really nice things about geda is its tollerent or flexible and that heavy symbols could easily be implemented. So the question is... is there enough support in the geda community to create a heavy symbol library? Steve Meier ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Part of the reason I ask this is that as I complete my work on a new library, netlister et al. I am thinking that beyond having a hierarchical schematic I would like to have symbols that can have files such as verilog, vhdl spice etc includded and that if the netleister could translate a schematic into say verilog and then include embeded verilof code it would feed streight into a verilof simulator. So this implies a desire/need for symbols which are used only for simulation such as signal generators and measurement nodes. Steve Meier Steve Meier wrote: I am becomming more and more a proponent of heavy symbols or even a data base then can generate heavy symbols. One of the really nice things about geda is its tollerent or flexible and that heavy symbols could easily be implemented. So the question is... is there enough support in the geda community to create a heavy symbol library? Steve Meier ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
How? My initial thought is something that builds a heavy library from a light one: Input: light/*.sym light/*.fp mapping table: sym | value | device | pinmap | newsym | other-attrs fp | value | device | pinmap | newfp | other-attrs Output: heavy/*.sym heavy/*.fp We need to be able to not only decide which light symbols/footprints to use, but also how to map the light pin numbers to the heavy ones. Ideally, the light/heavy symbols could co-exist, allowing parts to be enlightened (converted from heavy back to light) in order to switch parts, assuming the entities know what they are. This should also allow footprint switches without messing up pin numbers. The tricky part is coming up with a clever database schema so that we can share lots of commonality among part families, while allowing the special cases. Some sort of multi-field wildcard system, I suppose, using manufacturer part numbers (either some family name like 7404, or common name like 1N4001) for device, and including manufacturer/partno columns. The dull boring part is filling in all that information. So, one clever perl script, and one giant SQL database, and we're done! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
What is the deffinition of a heavy symbol? And secondly why put a data base behind one? I have been pondering this from several levels. One level is about how heavy large components have become and the tasks that are used in building a working programed printed circuit board. Take a large fpga that has a large number of io pins that can have many different functions. these are typically broken up into groups other wise called banks. On a bank by bank basis it is possible to sellect the following logic families 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL Differential 1.5-V HSTL Class I and II Differential 1.8-V HSTL Class I and II Differential SSTL-18 Class I and II Differential SSTL-2 Class I and II Within a bank a pair of io pins can be used differentialy or as single ended inputs. At lay out time pin swapping to detangle the netlist becomes very attractive. Which pins can be swapped? On a second level, even a resistor has limitations. For a given manufacturor of a given product line there exists only a finite number of resistance values? To support manufacturing I would like to know what are the options for a particular package? Can I expect the package to survive the expected power levels? On a third level, I would like to tie models and/or code (verilog, vhdl, spice) to a symbol and have the ability to generate simulatable netlists. So packages, must have correct pin numbers and available land patterns, part numbers must be correct to generate boms and thus purchase orders. To support layout the netlist needs to tell the layout program what can be swapped with what and the layout program needs to tell the schematic program what was swapped so that the schematic can be corrected for reality. Idealy the layout needs to be back-integrated into the simulation models for looking for tdr effects, paracitic capacitance etc. The schematic output needs to be capable of generating pin to signal descriptions for importing into proprietary software to support fpga or asic development. Why do we need to have heavier symbols... well in my opinion because the world of elcetronics is getting more complicated not less and light symbols presume a simple world and heavy symbols support the real world. But best of all is a comprimise where a data base generates or at least supports the symbols and simulations needed. Steve Meier P.S. If you were looking for a deffinition, well so am I. Please write your ideas... If there is one truely beautifull idea behind open knowledge it is the idea of sharing ideas. Randall Nortman wrote: On Tue, Dec 04, 2007 at 06:36:45PM -0800, Steve Meier wrote: I am becomming more and more a proponent of heavy symbols or even a data base then can generate heavy symbols. One of the really nice things about geda is its tollerent or flexible and that heavy symbols could easily be implemented. So the question is... is there enough support in the geda community to create a heavy symbol library? I've been noticing this whole heavy vs. light debate for a while, but not really following it. A heavy symbol is something that is fully specified, including footprint, right? Does that go all the way to particular manufacturer part numbers? A light symbol would be what the majority of the included library is right now -- generic symbols with no footprint specified, using generic pin assignments (which sometimes do not agree with reality for certain parts), right? Personally, when I need a heavy symbol, djboxsym does the job in a jiffy. (Thanks, DJ!) I use resistor, capacitor, diode, etc. symbols from the included library, and pretty much everything else comes from djboxsym. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Steve Meier wrote: I am becomming more and more a proponent of heavy symbols or even a data base then can generate heavy symbols. One of the really nice things about geda is its tollerent or flexible and that heavy symbols could easily be implemented. So the question is... is there enough support in the geda community to create a heavy symbol library? what I put together was a short awk script and a text database. The database had 1 line per part. Each line had a field specifying the part type (npn vs pnp), the footprint, and the mapping from E, B, C to the footprint pin. The awk script read that and took a template npn and pnp symbol and creates a bunch of heavy symbols that have the right pinout. Works pretty well, its very easy to add more transistors, and it would be easy enough to extend that idea to more than just bipolars. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
On Dec 4, 2007, at 8:23 PM, Steve Meier wrote: What is the deffinition of a heavy symbol? And secondly why put a data base behind one? I have been pondering this from several levels. To me, a heavy symbol (or, in the parlance of other EDA packages, a component) is one that includes footprint information and either a vendor part number or a company-internal one (which gets mapped to a vendor part number for ordering). A heavy symbol may also contain a pointer to a Spice library but I don't use that. Why is this good? Simply put: the schematic becomes the master drawing. From the schematic, one can generate a netlist including package information for layout and a BOM for parts ordering. The former is very important. We've seen examples of different flavors of transistors with different TO-92 pinouts. Things like opamps can have different pinouts when in different packages. So one can avoid all sorts of confusion by placing an AD8138ARZ on my schematic, knowing that it will automatically pull in the expected footprint (SOIC) and populate the BOM with a valid orderable part number. We have added the AD8138ARM to the library because we need the smaller footprint, and this part also has a different internal part number. One level is about how heavy large components have become and the tasks that are used in building a working programed printed circuit board. Take a large fpga that has a large number of io pins that can have many different functions. these are typically broken up into groups other wise called banks. On a bank by bank basis it is possible to sellect the following logic families 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL Differential 1.5-V HSTL Class I and II Differential 1.8-V HSTL Class I and II Differential SSTL-18 Class I and II Differential SSTL-2 Class I and II Within a bank a pair of io pins can be used differentialy or as single ended inputs. At lay out time pin swapping to detangle the netlist becomes very attractive. Which pins can be swapped? It's even worse than that, as (certainly with Xilinx) there are plenty of limitations to pin placement. Some pins are inputs only. You need to make sure you get your differential polarity correct. You need to specify particular clock input pins. Differential inputs on Spartan 3E don't have built-in terminations (but differential I/O does). You need to avoid using the configuration control pins for most general I/O. But this, in my estimation, doesn't have anything to do with the heavy vs light symbol debate. We like to break up FPGA symbols into banks. For example, XC3S250E-FT256 has four banks so our symbol is really five parts, one for configuration connections and core power and ground, and four symbols, one for each bank which include VCCIO connectors for that bank. Pin names are as noted in the Xilinx data sheet. This allows for some reasonable options for pin swapping. The other FPGA school-of-thought involves making a logic symbol (or set of symbols) for each design (which of course includes footprint and part number info) with particular FPGA design pins on the correct location in each symbol. By logical symbol I mean that you have, say, one symbol for CPU interface, another for DDR SDRAM interface, a third for Ethernet PHY, a fourth with config/power, etc. The downside of this is pretty obvious: make a change that requires adding pins and it gets ugly. On a second level, even a resistor has limitations. For a given manufacturor of a given product line there exists only a finite number of resistance values? To support manufacturing I would like to know what are the options for a particular package? Can I expect the package to survive the expected power levels? The obvious solution to this is to have heavy symbols for each and every resistor value, package size and tolerance. Of course your resistor library can grow quite large in a hurry, although creating a new symbol is a simple as copying an older one and changing the relevant fields. On a third level, I would like to tie models and/or code (verilog, vhdl, spice) to a symbol and have the ability to generate simulatable netlists. The problem with having schematics that support simulation (either HDL or Spice) and layout is that there are things on a layout that don't have models (connectors etc) and Spice-specific things don't translate to layout. -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Heavy Symbols and such
Hi Andy, Steve, Dan and all, Some time ago I gave Dan's transistor symbol generator a try and IMHO this is the way to go. For other parts such as opamps, triacs, diodes, caps and resistors this will work too (the bulk of small parts up to 3 or 4 pins). For looking up the right part I think we need more than a plain ASCII table to generate heavy symbols from on build time (usability and not to forget the size of the tarball or other packaged form). I think we should not create heavy symbols on build time but during run time (when the part is needed). Levente Kovacs has set up a database concept which could be expanded on (the bookmarked link I have does not seem to work anymore). In this way we could have both: generic light symbols and single purpose heavy symbols. See also: http://www.seul.org/pipermail/geda-dev/2007-September/003665.html Kind regards, Bert Timmerman On Tue, 2007-12-04 at 21:25 -0700, Andy Peters wrote: On Dec 4, 2007, at 8:23 PM, Steve Meier wrote: What is the deffinition of a heavy symbol? And secondly why put a data base behind one? I have been pondering this from several levels. To me, a heavy symbol (or, in the parlance of other EDA packages, a component) is one that includes footprint information and either a vendor part number or a company-internal one (which gets mapped to a vendor part number for ordering). A heavy symbol may also contain a pointer to a Spice library but I don't use that. Why is this good? Simply put: the schematic becomes the master drawing. From the schematic, one can generate a netlist including package information for layout and a BOM for parts ordering. The former is very important. We've seen examples of different flavors of transistors with different TO-92 pinouts. Things like opamps can have different pinouts when in different packages. So one can avoid all sorts of confusion by placing an AD8138ARZ on my schematic, knowing that it will automatically pull in the expected footprint (SOIC) and populate the BOM with a valid orderable part number. We have added the AD8138ARM to the library because we need the smaller footprint, and this part also has a different internal part number. One level is about how heavy large components have become and the tasks that are used in building a working programed printed circuit board. Take a large fpga that has a large number of io pins that can have many different functions. these are typically broken up into groups other wise called banks. On a bank by bank basis it is possible to sellect the following logic families 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL Differential 1.5-V HSTL Class I and II Differential 1.8-V HSTL Class I and II Differential SSTL-18 Class I and II Differential SSTL-2 Class I and II Within a bank a pair of io pins can be used differentialy or as single ended inputs. At lay out time pin swapping to detangle the netlist becomes very attractive. Which pins can be swapped? It's even worse than that, as (certainly with Xilinx) there are plenty of limitations to pin placement. Some pins are inputs only. You need to make sure you get your differential polarity correct. You need to specify particular clock input pins. Differential inputs on Spartan 3E don't have built-in terminations (but differential I/O does). You need to avoid using the configuration control pins for most general I/O. But this, in my estimation, doesn't have anything to do with the heavy vs light symbol debate. We like to break up FPGA symbols into banks. For example, XC3S250E-FT256 has four banks so our symbol is really five parts, one for configuration connections and core power and ground, and four symbols, one for each bank which include VCCIO connectors for that bank. Pin names are as noted in the Xilinx data sheet. This allows for some reasonable options for pin swapping. The other FPGA school-of-thought involves making a logic symbol (or set of symbols) for each design (which of course includes footprint and part number info) with particular FPGA design pins on the correct location in each symbol. By logical symbol I mean that you have, say, one symbol for CPU interface, another for DDR SDRAM interface, a third for Ethernet PHY, a fourth with config/power, etc. The downside of this is pretty obvious: make a change that requires adding pins and it gets ugly. On a second level, even a resistor has limitations. For a given manufacturor of a given product line there exists only a finite number of resistance values? To support manufacturing I would like to know what are the options for a particular package? Can I expect the package to survive the expected power levels? The obvious solution to this is to have heavy symbols for each and every resistor
