[gem5-users] Re: Core Communication Latency

[Mahyar Samani via gem5-users]

Hello Kazi,

If by core to core communication latency, you are referring to the latency
imposed by read sharing a cache block, you can use TrafficGenerator from
gem5 stdlib. The example below is most probably not the best way to do
this, but I could successfully measure the latency of moving the cache
block with address "addr' from core "src" to core "dst". After simulation
you should search for "generator.avgReadLatency". Note: This script
includes specific details about my use case (e.g. you should replace
CohrenetMeshNetwork with your cache hierarchy).

Best,

```
import argparse

import m5

from m5.debug import flags
from m5.objects import Root, DDR4_2400_8x8

from gem5.components.boards.test_board import TestBoard
from gem5.components.memory.memory import ChanneledMemory
from gem5.components.processors.traffic_generator import TrafficGenerator

from components.cmn import CoherentMeshNetwork
def get_inputs():
parser = argparse.ArgumentParser()
parser.add_argument(
"num_cores", type=int, help="Number of generator cores to simulate."
)
parser.add_argument(
"addr",
type=int,
help="Address to move",
)
parser.add_argument("src_id", type=int, help="Number of source core.")
parser.add_argument("dst_id", type=int, help="Number of destination core.")
args = parser.parse_args()
assert args.src_id < args.num_cores
assert args.dst_id < args.num_cores
assert args.src_id != args.dst_id
return args.num_cores, args.addr, args.src_id, args.dst_id
def generate_config_files(num_cores, addr, src_id, dst_id):
ret = []
for i in range(num_cores):
with open(f"/tmp/core_{i}.cfg", "w") as config:
lines = [
f"STATE 0 0 LINEAR 100 {i*2048} {(i+1)*2048} 64 500 500 2048\n",
]
transition_lines = ["INIT 0\n"]

if not i in [src_id, dst_id]:
lines += [f"STATE 1 1000 IDLE\n", f"STATE 2 0 EXIT\n"]
transition_lines += [
"TRANSITION 0 1 1\n",
"TRANSITION 1 2 1\n",
"TRANSITION 2 2 1\n",
]
elif i == src_id:
lines += [
f"STATE 1 0 LINEAR 100 {addr} {addr} 64 500 500 64\n",
f"STATE 2 0 EXIT\n",
f"STATE 3 1000 IDLE\n",
f"STATE 4 0 EXIT\n",
]
transition_lines += [
"TRANSITION 0 1 1\n",
"TRANSITION 1 2 1\n",
"TRANSITION 2 3 1\n",
"TRANSITION 3 4 1\n",
"TRANSITION 4 4 1\n",
]
elif i == dst_id:
lines += [
f"STATE 1 50 IDLE\n",
f"STATE 2 0 EXIT\n",
f"STATE 3 0 LINEAR 100 {addr} {addr} 64 500 500 64\n",
f"STATE 4 50 IDLE\n",
f"STATE 5 0 EXIT\n",
f"STATE 6 1000 IDLE\n",
]
transition_lines += [
"TRANSITION 0 1 1\n",
"TRANSITION 1 2 1\n",
"TRANSITION 2 3 1\n",
"TRANSITION 3 4 1\n",
"TRANSITION 4 5 1\n",
"TRANSITION 5 6 1\n",
"TRANSITION 6 6 1\n",
]
else:
raise ValueError
config.writelines(lines + transition_lines)
ret.append(f"/tmp/core_{i}.cfg")
return ret


def MultiChannelDDR4(num_channels):
return ChanneledMemory(DDR4_2400_8x8, num_channels, 128, size="16GiB")


if __name__ == "__m5_main__":
num_cores, addr, src_id, dst_id = get_inputs()
generator = TrafficGenerator(
generate_config_files(num_cores, addr, src_id, dst_id)
)
cache = CoherentMeshNetwork()
memory = MultiChannelDDR4(8)
board = TestBoard(
clk_freq="4GHz",
generator=generator,
cache_hierarchy=cache,
memory=memory,
)

root = Root(full_system=False, system=board)

board._pre_instantiate()
m5.instantiate()

generator.start_traffic()
print("Beginning simulation!")
exit_events_countered = 0
while True:
exit_event = m5.simulate()
exit_events_countered += 1
print(
f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}."
)
print(f"Received {exit_events_countered} exit events.")
if exit_events_countered == 1:
print("Source core done reading.")
if exit_events_countered == 2:
print("Resetting stats.")
m5.stats.reset()
if exit_events_countered == 3:
print("Exiting while loop.")
break
print("Simulation over.")
```
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[gem5-users] Re: Gem5/DRAMSim3

[Mahyar Samani via gem5-users]

Hello Kazi,

Can you direct me on how I can reproduce the error you are getting? Can you
please answer the following questions?

- What script are you running?
- What command are you using?
- What version of gem5 are you using (which commit/branch)?
- Did you build gem5 with DRAMSim3?

Best Regards,

On Tue, Mar 15, 2022 at 3:34 PM Kazi Asifuzzaman 
wrote:

> Hi Mahyar,
>
> Thanks for the suggestions. I applied them as well as updating the
> directory paths for the config files. Now it throws the exception from this
> segment. how should we define the range of the memory? Any ideas?
>
> @overrides(AbstractMemorySystem)
> def set_memory_range(self, ranges: List[AddrRange]) -> None:
>  if len(ranges) != 1 or ranges[0].size != self._size:
> raise Exception(
>   "Single channel DRAMSim memory controller requires a
> single "
>"range which matches the memory's size."
> )
> self.mem_ctrl.range = ranges[0]
>
> Thanks,
>
> Kazi
>
> On Mon, Mar 14, 2022 at 5:27 PM Mahyar Samani  wrote:
>
>> Hello Kazi,
>>
>> I looked at the script and you should make the following changes:
>>
>> from gem5.components.memory import SingleChannelDDR3_1600 --> from
>> gem5.components.memory.dramsim_3 import SingleChannelDDR3_1600
>> requires(isa_required=ISA.ARM) --> requires(isa_required=ISA.X86), if it
>> does not work comment out for now
>> memory = SingleChannelDDR3_1600(size="32MB") --> No Change needed
>> from gem5.resources.resource import Resource (line 49 in the original
>> file) --> from gem5.resources.resource import CustomResource
>> Resource("arm-hello64-static") --> CustomResource(local_path=[the path
>> to your binary])
>>
>> Best Regards,
>>
>>
>> On Mon, Mar 14, 2022 at 1:54 PM Kazi Asifuzzaman <
>> kazi.asifuzza...@gmail.com> wrote:
>>
>>> Hi Mahyar,
>>>
>>> I am trying to prepare a SE mode for x86. To replicate the ARM config
>>> for this, could you please clarify how do I replace the parts in RED:
>>>
>>> from gem5.components.memory import SingleChannelDDR3_1600  //For using
>>> DRAMsim3. How do I specify the memory config *from* DRAMsim3 (e.g.
>>> DDR3-1600)
>>> requires(isa_required=ISA.ARM)  //Any check
>>> for x86 ISA ?
>>> memory = SingleChannelDDR3_1600(size="32MB")//Again,
>>> how do I specify a specific memory protocol to be used *from* DRAMsim3
>>> Resource("arm-hello64-static") //if I want
>>> to use a binary from a directory
>>>
>>> Thanks,
>>>
>>> *Kazi*
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> On Mon, Mar 7, 2022 at 4:57 PM Mahyar Samani 
>>> wrote:
>>>
 Hello Kazi,

 Take a look at configs/example/gem5_library/arm-hello.py. It is a good
 example of SE mode for ARM ISA. If you are interested in instantiating a
 memory module look at lines 47, and 62 from the same file.
 P.S. I'm checking out the stable branch on the gem5 repo
 (Hash: 141cc37c2d4b93959d4c249b8f7e6a8b2ef75338).

 Best Regards,

 On Mon, Mar 7, 2022 at 1:17 PM Kazi Asifuzzaman <
 kazi.asifuzza...@gmail.com> wrote:

> Hi Mahyar,
>
> Thanks for your mail and suggestions. Could you please give examples
> of:
> 1. How to use gem5 standard library to configure a system, instead of
> using se.py?
> 2. How to use standard library API to instantiate a memory?
>
> Thanks,
>
> Kazi
>
> On Fri, Mar 4, 2022 at 1:43 PM Mahyar Samani 
> wrote:
>
>> Hello Kazi,
>>
>> Thanks for reaching out. Yes, I am aware of the problem. Fortunately,
>> the issue is not with gem5/DRAMSim3 integration. Rather, it's just caused
>> by some of the differences between gem5 and DRAMSim3 memory controller. I
>> assume you are using either of the se.py or fs.py in src/config/example. 
>> I
>> can propose a quick solution to your problem. However, we believe using
>> se.py/fs.py to do your simulation is not the best solution. We have
>> recently added the gem5 standard library that makes it easier for you to
>> configure the system you want to simulate. Back to the solution, fs.py 
>> and
>> se.py use api from src/config/common/MemConfig.py to configure the memory
>> components in the system (this does not include caches). What you'll need
>> to do (reminder: this a quick solution) is to find calls to api from
>> MemConfig.py in se.py/fs.py (whichever one you are using) and remove
>> those calls and instantiate the memory yourself. The standard library 
>> has a
>> really easy api to instantiate a memory. Please look at
>> src/python/gem5/components/memory/dramsim_3.py for memories from 
>> DRAMSim3.
>> I hope this is helpfull, if you needed further help, please feel free to
>> reach out to me (I have a deadline today at 11:59 pm PST and will respond
>> asap after that). I would appreciate it if you 

[gem5-users] Re: Gem5/DRAMSim3

[Mahyar Samani via gem5-users]

Hello Kazi,

I looked at the script and you should make the following changes:

from gem5.components.memory import SingleChannelDDR3_1600 --> from
gem5.components.memory.dramsim_3 import SingleChannelDDR3_1600
requires(isa_required=ISA.ARM) --> requires(isa_required=ISA.X86), if it
does not work comment out for now
memory = SingleChannelDDR3_1600(size="32MB") --> No Change needed
from gem5.resources.resource import Resource (line 49 in the original file)
--> from gem5.resources.resource import CustomResource
Resource("arm-hello64-static") --> CustomResource(local_path=[the path to
your binary])

Best Regards,


On Mon, Mar 14, 2022 at 1:54 PM Kazi Asifuzzaman 
wrote:

> Hi Mahyar,
>
> I am trying to prepare a SE mode for x86. To replicate the ARM config for
> this, could you please clarify how do I replace the parts in RED:
>
> from gem5.components.memory import SingleChannelDDR3_1600  //For using
> DRAMsim3. How do I specify the memory config *from* DRAMsim3 (e.g.
> DDR3-1600)
> requires(isa_required=ISA.ARM)  //Any check
> for x86 ISA ?
> memory = SingleChannelDDR3_1600(size="32MB")//Again, how
> do I specify a specific memory protocol to be used *from* DRAMsim3
> Resource("arm-hello64-static") //if I want to
> use a binary from a directory
>
> Thanks,
>
> *Kazi*
>
>
>
>
>
>
>
>
>
>
>
> On Mon, Mar 7, 2022 at 4:57 PM Mahyar Samani  wrote:
>
>> Hello Kazi,
>>
>> Take a look at configs/example/gem5_library/arm-hello.py. It is a good
>> example of SE mode for ARM ISA. If you are interested in instantiating a
>> memory module look at lines 47, and 62 from the same file.
>> P.S. I'm checking out the stable branch on the gem5 repo
>> (Hash: 141cc37c2d4b93959d4c249b8f7e6a8b2ef75338).
>>
>> Best Regards,
>>
>> On Mon, Mar 7, 2022 at 1:17 PM Kazi Asifuzzaman <
>> kazi.asifuzza...@gmail.com> wrote:
>>
>>> Hi Mahyar,
>>>
>>> Thanks for your mail and suggestions. Could you please give examples of:
>>> 1. How to use gem5 standard library to configure a system, instead of
>>> using se.py?
>>> 2. How to use standard library API to instantiate a memory?
>>>
>>> Thanks,
>>>
>>> Kazi
>>>
>>> On Fri, Mar 4, 2022 at 1:43 PM Mahyar Samani 
>>> wrote:
>>>
 Hello Kazi,

 Thanks for reaching out. Yes, I am aware of the problem. Fortunately,
 the issue is not with gem5/DRAMSim3 integration. Rather, it's just caused
 by some of the differences between gem5 and DRAMSim3 memory controller. I
 assume you are using either of the se.py or fs.py in src/config/example. I
 can propose a quick solution to your problem. However, we believe using
 se.py/fs.py to do your simulation is not the best solution. We have
 recently added the gem5 standard library that makes it easier for you to
 configure the system you want to simulate. Back to the solution, fs.py and
 se.py use api from src/config/common/MemConfig.py to configure the memory
 components in the system (this does not include caches). What you'll need
 to do (reminder: this a quick solution) is to find calls to api from
 MemConfig.py in se.py/fs.py (whichever one you are using) and remove
 those calls and instantiate the memory yourself. The standard library has a
 really easy api to instantiate a memory. Please look at
 src/python/gem5/components/memory/dramsim_3.py for memories from DRAMSim3.
 I hope this is helpfull, if you needed further help, please feel free to
 reach out to me (I have a deadline today at 11:59 pm PST and will respond
 asap after that). I would appreciate it if you could send your questions to
 the gem5 mailing list. This way, other people would also be aware of the
 bugs and inconsistencies in the repo and it definitely makes it a bigger
 priority to be solved. Feel free to cc me so I make sure to respond as
 quickly as possible.

 Best Regards,

 On Fri, Mar 4, 2022 at 10:23 AM Kazi Asifuzzaman <
 kazi.asifuzza...@gmail.com> wrote:

> Good Afternoon Mahyar,
>
> From a gem5 discussion group, it appears that you are managing (a part
> of) the gem5 project. I am trying to integrate Gem5 with DRAMSim3 (the way
> it explains in ext/dramsim3/README), but when the try to use
> --mem-type=DRAMsim3 to run the simulation it says: AttributeError:
> object 'DRAMsim3' has no attribute 'controller'
>
> Could you please shed some light on it? In a mail thread I see that
> you were working on a fix for this, could you resolve this issue?
>
> Many thanks for your time,
>
> *Kazi *
>


 --
 Mahyar Samani
 PhD Student
 Research Assistant at *DArchR *
 University of California, Davis
 May the Force be with you.

>>>
>>
>> --
>> Mahyar Samani
>> PhD Student
>> Research Assistant at *DArchR *
>> University of California, Davis
>> May the 

[gem5-users] Re: Gem5/DRAMSim3

[Mahyar Samani via gem5-users]

Hello Kazi,

Take a look at configs/example/gem5_library/arm-hello.py. It is a good
example of SE mode for ARM ISA. If you are interested in instantiating a
memory module look at lines 47, and 62 from the same file.
P.S. I'm checking out the stable branch on the gem5 repo
(Hash: 141cc37c2d4b93959d4c249b8f7e6a8b2ef75338).

Best Regards,

On Mon, Mar 7, 2022 at 1:17 PM Kazi Asifuzzaman 
wrote:

> Hi Mahyar,
>
> Thanks for your mail and suggestions. Could you please give examples of:
> 1. How to use gem5 standard library to configure a system, instead of
> using se.py?
> 2. How to use standard library API to instantiate a memory?
>
> Thanks,
>
> Kazi
>
> On Fri, Mar 4, 2022 at 1:43 PM Mahyar Samani  wrote:
>
>> Hello Kazi,
>>
>> Thanks for reaching out. Yes, I am aware of the problem. Fortunately, the
>> issue is not with gem5/DRAMSim3 integration. Rather, it's just caused by
>> some of the differences between gem5 and DRAMSim3 memory controller. I
>> assume you are using either of the se.py or fs.py in src/config/example. I
>> can propose a quick solution to your problem. However, we believe using
>> se.py/fs.py to do your simulation is not the best solution. We have
>> recently added the gem5 standard library that makes it easier for you to
>> configure the system you want to simulate. Back to the solution, fs.py and
>> se.py use api from src/config/common/MemConfig.py to configure the memory
>> components in the system (this does not include caches). What you'll need
>> to do (reminder: this a quick solution) is to find calls to api from
>> MemConfig.py in se.py/fs.py (whichever one you are using) and remove
>> those calls and instantiate the memory yourself. The standard library has a
>> really easy api to instantiate a memory. Please look at
>> src/python/gem5/components/memory/dramsim_3.py for memories from DRAMSim3.
>> I hope this is helpfull, if you needed further help, please feel free to
>> reach out to me (I have a deadline today at 11:59 pm PST and will respond
>> asap after that). I would appreciate it if you could send your questions to
>> the gem5 mailing list. This way, other people would also be aware of the
>> bugs and inconsistencies in the repo and it definitely makes it a bigger
>> priority to be solved. Feel free to cc me so I make sure to respond as
>> quickly as possible.
>>
>> Best Regards,
>>
>> On Fri, Mar 4, 2022 at 10:23 AM Kazi Asifuzzaman <
>> kazi.asifuzza...@gmail.com> wrote:
>>
>>> Good Afternoon Mahyar,
>>>
>>> From a gem5 discussion group, it appears that you are managing (a part
>>> of) the gem5 project. I am trying to integrate Gem5 with DRAMSim3 (the way
>>> it explains in ext/dramsim3/README), but when the try to use
>>> --mem-type=DRAMsim3 to run the simulation it says: AttributeError:
>>> object 'DRAMsim3' has no attribute 'controller'
>>>
>>> Could you please shed some light on it? In a mail thread I see that you
>>> were working on a fix for this, could you resolve this issue?
>>>
>>> Many thanks for your time,
>>>
>>> *Kazi *
>>>
>>
>>
>> --
>> Mahyar Samani
>> PhD Student
>> Research Assistant at *DArchR *
>> University of California, Davis
>> May the Force be with you.
>>
>

-- 
Mahyar Samani
PhD Student
Research Assistant at *DArchR *
University of California, Davis
May the Force be with you.
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[gem5-users] Re: Generate traffic/trace and feed it to Garnet standalone mode

[Mahyar Samani via gem5-users]

Hello Travis,

You need to write a script that describes the system you want to test with
synthetic traffic, then you can add a PyTrafficGen to your system. The
PyTrafficGen object has several functions that generate the traffic you
want such as createLinear, createRandom, createDram, createIdle,
createExit. Then you can call the start function from PyTrafficGen on the
traffic you have created. I think there is a script in
configs/dram/sweep.py that has an example of using PyTrafficGen. Please let
me know if you have any questions.

Best Regards

On Wed, May 26, 2021 at 7:23 PM Travis Dai via gem5-users <
gem5-users@gem5.org> wrote:

> Dear all users,
>
>
>
> I have been working on how to generate traffic by using TrafficGen.py and
> related files in gem5/src/cpu/testers/traffic_gen these days but without
> success.
>
>
>
> I have tried to run TrafficGen.py by command “python TrafficGen.py” but
> receiving error “ImportError: No module named m5.params”. I also tried
> compile traffic_gen.cc by command “g++ traffic_gen.cc -o traffic_gen” but
> fail again with message “traffic_gen.cc:37:10: fatal error:
> cpu/testers/traffic_gen/traffic_gen.hh: No such file or directory
>
>37 | #include "cpu/testers/traffic_gen/traffic_gen.hh"”. Then I change
> the relative path to absolute path of header but the dependency of other
> files trigger other errors again, such as “traffic_gen/base.hh:45:10: fatal
> error: base/statistics.hh: No such file or directory45 | #include
> "base/statistics.hh"”.
>
>
>
> Then, I switch to read  gem5 description for Tracing and traffic
> generation in
> http://www.m5sim.org/General_Memory_System#Tracing_and_traffic_generation
> and
> http://pages.cs.wisc.edu/~swilson/gem5-docs/classTrafficGen.html#a53b678d216bdfcf5097c0f0436c16e30.
> The former website says traffic generator is controlled by a text-based
> configuration file, as can be seen in 
> tests/quick/se/70.tgen/tgen-simple-mem.cfg
> .
>
> But when I go to the directory gem5/tests, there is no such kind of file.
> The latter website tells functions of related code but it seems outdated.
>
>
>
> My expectation is that using TrafficGen.py manually define which cpus send
> packets, how big they are, and which cpus receives packets and generate
> traffic. Then feed them to Garnet standalone debug mode to test network
> performance.
>
>
>
> Does anyone know how to solve this problem or give me some
> pointers/tutorials. I appreciate it very much!
>
>
>
> Best wishes,
>
> Travis
>
>
>
>
>
>
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-- 
Mahyar Samani
Electrical and Computer Engineering Department
Research Assistant at *DArchR  (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: ISSUES FACING WHILE INTEGRATING GEM5 AND DRAMSIM3

[Mahyar Samani via gem5-users]

Hello,

I would say overall DRAMSim3 is more accurate and to be honest it is much
easier to use than DRAMSim2. I am also doing an evaluation on memory models
between DRAMSim3 and gem5, based on the current results I would suggest you
use either DRAMSim3 (using the temporary solution I proposed) or gem5
models.

Best Regards,

On Sun, Mar 28, 2021 at 7:23 AM haurunis--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Mahyar,
>
> Sorry to bother but I would like to ask a related question:
> So for better DRAM power/timing simulation, will DRAMSim3 be the best
> among DRAMCtrl (gem5-prebuilt) and DRAMSim2? The reason I am asking is that
> I also tried to get DRAMSim2 to work in gem5. However, following the
> /ext/DRAMSim2/readme, I kept running into
> ```command line: build/X86/gem5.opt configs/example/se.py -c
> tests/test-progs/hello/bin/x86/linux/hello --cpu-type=TraceCPU --caches
> --l2cache --mem-type=dramsim2
>
> Usage: se.py [options]
>
> se.py: error: option --mem-type: invalid choice:
> ```
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>


-- 
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at *DArchR  (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: ISSUES FACING WHILE INTEGRATING GEM5 AND DRAMSIM3

[Mahyar Samani via gem5-users]

Btw, the controller from DRAMSim3 does not need an interface connected to
itself (the timings for those models come from DRAMSim3).

Best,

On Wed, Mar 24, 2021 at 6:31 PM Mahyar Samani  wrote:

> Hello Monica, Aravind, and Ipshita
>
> Currently the script in configs/common/MemConfig.py does not work with
> DRAMSim3 models. You can create a DRAMSim3 controller using the following
> piece of code (ini_path should point the ini file for the DRAMSim3 model
> you would like to use):
> class DS3MemCtrl(DRAMsim3):
> def __init__(self, ini_path):
> super(DS3MemCtrl, self).__init__()
> self.configFile = ini_path
> You can find all these ini files in the ext/dramsim3/DRAMsim3/configs/
>
> Also, I will add support for DRAMSim3 models in MemConfig.py soon. Please
> let me know if you have any questions and if I could be of further
> assistance.
>
> Best Regards,
>
> On Fri, Mar 19, 2021 at 1:57 PM Kodali, Monica Bhargavi via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Dear gem5 support community,
>> Our team is trying to integrate DRAMsim3 with the latest version of Gem5 (
>> https://github.com/gem5/gem5). We were able to successfully build Gem5
>> with DRAMsim3 by following the steps in the README file under ext/dramsim3,
>> but on executing any test script (such as se.py or low_power_sweep.py) with
>> the option --mem-type=DRAMsim3, we get the following error -
>>
>>
>> *Traceback (most recent call last):*
>> *  File "", line 1, in *
>> *  File "build/ARM/python/m5/main.py", line 457, in main*
>> *exec(filecode, scope)*
>> *  File "configs/example/se.py", line 275, in *
>> *MemConfig.config_mem(options, system)*
>> * File
>> "/home/UFAD/ipshita.aggarwal/packages/gem5/configs/common/MemConfig.py",
>> line 257, in config_mem*
>> *mem_ctrl.dram = dram_intf*
>> *  File "build/ARM/python/m5/SimObject.py", line 1337, in __setattr__*
>> *hr_value = value*
>> *  File "build/ARM/python/m5/params.py", line 215, in convert*
>> *if isNullPointer(value) and isSimObjectClass(self.ptype):*
>> *TypeError: __init__() takes 1 positional argument but 2 were given*
>> *Error setting param MemCtrl.dram to *
>>
>>
>>
>>
>> Could you point us to any resources or provide directions on how the
>> DRAMsim3 memory option can be used with the latest version of Gem5 such
>> that any ini file configured in src/mem/DRAMsim3.py is picked when the
>> option --mem-type=DRAMsim3 is used.
>>
>>
>> Thanks and Regards,
>> Monica Bhargavi Kodali.
>> Aravind Neelakantan.
>> Ipshita Aggarwal.
>> ___
>> gem5-users mailing list -- gem5-users@gem5.org
>> To unsubscribe send an email to gem5-users-le...@gem5.org
>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
>
>
> --
> Mahyar Samani (he/him/his)
> Electrical and Computer Engineering Department
> Research Assistant at *DArchR  (*2235
> Kemper Hall)
> Secretary
> ECE-GSA
> Vice President
> Iranian Student Association at UC Davis
> University of California, Davis
>


-- 
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at *DArchR  (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: ISSUES FACING WHILE INTEGRATING GEM5 AND DRAMSIM3

[Mahyar Samani via gem5-users]

Hello Monica, Aravind, and Ipshita

Currently the script in configs/common/MemConfig.py does not work with
DRAMSim3 models. You can create a DRAMSim3 controller using the following
piece of code (ini_path should point the ini file for the DRAMSim3 model
you would like to use):
class DS3MemCtrl(DRAMsim3):
def __init__(self, ini_path):
super(DS3MemCtrl, self).__init__()
self.configFile = ini_path
You can find all these ini files in the ext/dramsim3/DRAMsim3/configs/

Also, I will add support for DRAMSim3 models in MemConfig.py soon. Please
let me know if you have any questions and if I could be of further
assistance.

Best Regards,

On Fri, Mar 19, 2021 at 1:57 PM Kodali, Monica Bhargavi via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 support community,
> Our team is trying to integrate DRAMsim3 with the latest version of Gem5 (
> https://github.com/gem5/gem5). We were able to successfully build Gem5
> with DRAMsim3 by following the steps in the README file under ext/dramsim3,
> but on executing any test script (such as se.py or low_power_sweep.py) with
> the option --mem-type=DRAMsim3, we get the following error -
>
>
> *Traceback (most recent call last):*
> *  File "", line 1, in *
> *  File "build/ARM/python/m5/main.py", line 457, in main*
> *exec(filecode, scope)*
> *  File "configs/example/se.py", line 275, in *
> *MemConfig.config_mem(options, system)*
> * File
> "/home/UFAD/ipshita.aggarwal/packages/gem5/configs/common/MemConfig.py",
> line 257, in config_mem*
> *mem_ctrl.dram = dram_intf*
> *  File "build/ARM/python/m5/SimObject.py", line 1337, in __setattr__*
> *hr_value = value*
> *  File "build/ARM/python/m5/params.py", line 215, in convert*
> *if isNullPointer(value) and isSimObjectClass(self.ptype):*
> *TypeError: __init__() takes 1 positional argument but 2 were given*
> *Error setting param MemCtrl.dram to *
>
>
>
>
> Could you point us to any resources or provide directions on how the
> DRAMsim3 memory option can be used with the latest version of Gem5 such
> that any ini file configured in src/mem/DRAMsim3.py is picked when the
> option --mem-type=DRAMsim3 is used.
>
>
> Thanks and Regards,
> Monica Bhargavi Kodali.
> Aravind Neelakantan.
> Ipshita Aggarwal.
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
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-- 
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at *DArchR  (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: AttributeError: Class DDR3_1600_8x8 has no parameter port

[Mahyar Samani via gem5-users]

Hey Anthony,

Can you send more information to reproduce this error?

Best Regrads

On Sat, Dec 5, 2020 at 2:40 AM anthonyabeo--- via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Everyone,
>
> I am new here and just started playing with gem5. I run into an error (as
> specified in the subject) when I tried running the first simple CPU
> example.
>
> system.mem_ctrl = DDR3_1600_8x8()
> system.mem_ctrl.range = system.mem_ranges[0]
> system.mem_ctrl.port = system.membus.master
>
> Looking at the source code, DDR3_1600_8x8 actually doesn't seem to have a
> field "port."
>
> How can I resolve this?
>
> Thanks.
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>


-- 
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at *DArchR  (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: Running gem5 with DRAMsim3

[Mahyar Samani via gem5-users]

Hey Yogeshwaran,

Since the gem5-20.1 release, it now supports DRAMSim3 integration so there
is no need for you to follow the instructions there. There is a readme file
in ext/dramsim3 that you can follow and build gem5 with DRAMSim3, also,
class DRAMSim3 inherits from AbstractMemory which will allow you to swap
any memory with DRAMSim3 models. To change the model you want to use in
DRAMSim3 you can just change the path to the .ini file you are  using by
changing param configFile.

Best Regards

On Tue, Nov 24, 2020 at 5:30 AM Yogeshwaran L via gem5-users <
gem5-users@gem5.org> wrote:

> Dear gem5 community,
>
> I am trying to integrate DRAMsim3 with gem5, and I was able to
> successfully build gem5 with DRAmsim3, following the instructions from
> https://github.com/umd-memsys/gem5/tree/dramsim3/ext/dramsim3.
>
> However, in the last step it is mentioned "Use --mem-type=dramsim3 and set
> the device and system configuration". But when I looked at the
> configuration script (simple.py) in part1 of learning_gem5 directory, there
> are many fields to be configured for memory.
>
> Can anyone point me to resources or offer any advice on how to use a
> different memory system(like DRAMsim3) with gem5 and configure the
> parameters in configuration script. Is it as straightforward as configuring
> the config script or should I do additional modifications?
>
> Thank you,
> Yogeshwaran
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-- 
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at *DArchR  (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: XBar on dcache port impacting BW?

[Mahyar Samani via gem5-users]

Hey Fisher,

I'm not sure if that is correct as every packet spends at least one cycle
on the XBar (even in real hardware), however, I would say one limiting
factor in gem5 about the XBar is the fact that you can't effectively
increase the width of the XBar as much as you want (you can say
system.membus = SystemXBar(width = 8192), but the XBar is not gonna send
more than one packet per cycle which has a size of 512 bits) and that's due
to how it is designed, I think the correct way of doing this is redesigning
your specific XBar by implementing a new SimObject/ClockedObject that will
transfer more than one packet per cycle.

Best Regards,

On Thu, Nov 12, 2020 at 11:52 AM Xue, Fisher via gem5-users <
gem5-users@gem5.org> wrote:

> Hey Mahyar,
>
> Thanks for the response! I’m actually not seeing the 1 packet per cycle
> expectation…
>
> I think I have root-caused the issue to the timing calculation in the
> XBar, however, I’m not sure if this is an intentional design choice or
> something else:
>
> It calculates the time for a packet as
>
> packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
>
> however, I think this will require any packet of size to spend 2 cycles in
> the XBar, limiting bandwidth. I fixed this by taking the max of 1 cycle and
> the payloadDelay instead, however, I’m unsure if this is correct.
>
>
>
> *From:* Mahyar Samani via gem5-users 
> *Sent:* October 20, 2020 8:59 AM
> *To:* gem5 users mailing list 
> *Cc:* Mahyar Samani 
> *Subject:* [gem5-users] Re: XBar on dcache port impacting BW?
>
>
>
> Hey Fisher,
>
> The XBar can at maximum deliver a bandwidth equivalent to 1 packet size
> (which I believe is 64 bytes) per cycle (e.g. if the clk_freq is set to
> 1GHz, it will at max deliver 64GBps). Does this information comply with the
> results you are seeing?
>
>
>
> Best Regards,
>
>
>
> On Tue, Oct 13, 2020 at 10:50 AM fisher.xue--- via gem5-users <
> gem5-users@gem5.org> wrote:
>
> I am trying to connect the L1D to the CPU dcache port over an XBar (I
> intend to connect another memory to this XBar), however, when making this
> connection, I observe that the bandwidth to my L1 halves due  to XBar
> contention, however, I am modelling this as a 0-latency XBar with
> effectively infinite width. Does anyone have any idea what I could be doing
> wrong?
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>
>
>
>
> --
>
> Mahyar Samani (he/him/his)
>
> Electrical and Computer Engineering Department
>
> Research Assistant at *DArchR <https://arch.cs.ucdavis.edu/> (*2235
> Kemper Hall)
>
> Secretary
>
> ECE-GSA
>
> Vice President
>
> Iranian Student Association at UC Davis
>
> University of California, Davis
> ___
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-- 
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at *DArchR <https://arch.cs.ucdavis.edu/> (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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[gem5-users] Re: XBar on dcache port impacting BW?

[Mahyar Samani via gem5-users]

Hey Fisher,

The XBar can at maximum deliver a bandwidth equivalent to 1 packet size
(which I believe is 64 bytes) per cycle (e.g. if the clk_freq is set to
1GHz, it will at max deliver 64GBps). Does this information comply with the
results you are seeing?

Best Regards,

On Tue, Oct 13, 2020 at 10:50 AM fisher.xue--- via gem5-users <
gem5-users@gem5.org> wrote:

> I am trying to connect the L1D to the CPU dcache port over an XBar (I
> intend to connect another memory to this XBar), however, when making this
> connection, I observe that the bandwidth to my L1 halves due  to XBar
> contention, however, I am modelling this as a 0-latency XBar with
> effectively infinite width. Does anyone have any idea what I could be doing
> wrong?
> ___
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> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>


-- 
Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at *DArchR  (*2235 Kemper
Hall)
Secretary
ECE-GSA
Vice President
Iranian Student Association at UC Davis
University of California, Davis
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