Access on ALESERV

[Micheal Butz]

Hi,

 

 Can anyone explain to me the significance of the ACCESS parameter on the
ALESERV MACRO

 

THANKS  


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Re: ALESEERV AL=PASN

[Micheal Butz]

Thanks

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Dave Day
Sent: Tuesday, June 12, 2012 8:26 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: ALESEERV AL=PASN

Michael,

 If you re executing an AESERV to add an alet, it means the alet is 
available to all units of work in the pasn address space.

 --Dave

On 6/12/2012 7:09 AM, Micheal Butz wrote:
> Hi,
>
>
>
>   Does AL=PASN on the ALESERV macro mean that the ALET is available to all
> address spaces
>
>
>
> Which is the same concept LXRES with SYSTEM=YES
>
>
>
> Correct ??
>
>
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ALESEERV AL=PASN

[Micheal Butz]

Hi, 

 

 Does AL=PASN on the ALESERV macro mean that the ALET is available to all
address spaces

 

Which is the same concept LXRES with SYSTEM=YES

 

Correct ??


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Re: SRB mode question

[Micheal Butz]

Thank you

I was trying to see what load modules are in core in different address
spaces

Requirements for CSVQUERY callers are: 




   Minimum authorization: Problem state and any PSW key
   Dispatchable unit mode:Task or SRB

 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Rob Scott
Sent: Sunday, June 10, 2012 1:57 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRB mode question

All IBM services, whether branch entry, PC or SVC have their supported modes
(TCB and/or SRB)  and cross-memory environments documented in the manuals.

I would strongly advise that you refer to the manuals than use any sort of
generalizations.

Rob Scott
Lead Developer
Rocket Software
77 Fourth Avenue . Suite 100 . Waltham . MA 02451-1468 . USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 10 June 2012 16:30
To: IBM-MAIN@bama.ua.edu
Subject: SRB mode question

Hi,

 

It's been a while since I scheduled an SRB If I use any IBM services in a
SRB I use the branch entry from but I just looked at some documentation
"Cross memory for beginners"

 

And it seems PC rtns are also okay in SRB mode didn't specify SSWITH (space
switch or not)

 

 

Just wanted to verify this

 

 

thanks 


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SRB mode question

[Micheal Butz]

Hi,

 

It's been a while since I scheduled an SRB If I use any IBM services in a
SRB I use the branch entry from but I just looked at some documentation
"Cross memory for beginners"

 

And it seems PC rtns are also okay in SRB mode didn't specify SSWITH (space
switch or not)

 

 

Just wanted to verify this

 

 

thanks 


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Re: EXTRACT,QEDIT macro

[Micheal Butz]

Thank you

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Gerhard Postpischil
Sent: Monday, April 23, 2012 8:49 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: EXTRACT,QEDIT macro

On 4/23/2012 5:30 PM, Micheal Butz wrote:
> If after issuing the EXTRACT to get the address of the communication
> parameter list (com) and the communication input buffer (cib)
> I attach 4 subtasks are the com/cib address obtaining by the originating
> tasks valid for the subtask that I have now attached

The CIB is one element in a chain of 0 to a maximum count, 
depending on how you initialized processing. I usually set the 
maximum to 1 because that makes the logic a little simpler.

When your program starts, there may or may not be a START CIB. 
You should see one in an STC, but not usually when running under 
an initiator.

After you set the maximum CIB count to non-zero, the CommECB is 
posted when a STOP or MODify adds a CIB to the chain. After you 
process that CIB, you would normally free it.

Once you understand the processing, the QEDIT description should 
make more sense.

Also note that a STOP command posts the ECB with an X'50', 
whereas all others post with X'40'.

Gerhard Postpischil
Bradford, VT

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Re: EXTRACT,QEDIT macro

[Micheal Butz]

Thank you

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Tony Harminc
Sent: Monday, April 23, 2012 6:25 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: EXTRACT,QEDIT macro

On 23 April 2012 17:30, Micheal Butz  wrote:

>  I have a question regarding the usage of the Extract Qedit macros for
> operator communication

> I have started task looking to process a Flush Or Modify command via the
> com/cib the pointer to the CIB is just for the current task

> If after issuing the EXTRACT to get the address of the communication
> parameter list (com) and the communication input buffer (cib)

> I attach 4 subtasks are the com/cib address obtaining by the originating
> tasks valid for the subtask that I have now attached

I believe you asked and received answers to the same question on Feb
10 of this year. To repeat, there is only one CIB and communications
ECB per address space, and any task can wait on it (there is special
code to allow this without running onto the key mismatch problems you
have encountered with other ECBs).

But you still cannot wait more than once at a time on a single ECB, so
you must coordinate that somehow.

Tony H.

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EXTRACT,QEDIT macro

[Micheal Butz]

Hi,

 

 I have a question regarding the usage of the Extract Qedit macros for
operator communication

 

I have started task looking to process a Flush Or Modify command via the
com/cib the pointer to the CIB is just for the current task

 

If after issuing the EXTRACT to get the address of the communication
parameter list (com) and the communication input buffer (cib)

 

I attach 4 subtasks are the com/cib address obtaining by the originating
tasks valid for the subtask that I have now attached 

 

 

Thanks   


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Re: Explination of S0C4 reason code 4 and related data areas

[Micheal Butz]

Thank you 

Seems that for sp 0 - 127 it is TCBPKF

 SUBPOOL Location TypeOwner
Storage Key
  
  0-127Private low   Pageable Task TCB
Same as TCB 
key
at time 
 of
first
 
storage 
 
request.
 
Same as TCB 
 

  
  
  
  Other wise table 10 - 3  IN-  10.3.1.4 Selecting the Storage Key
describes what the virtual storage key will be

 
 
 
 
  
   
  
 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Saturday, April 21, 2012 6:34 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Explination of S0C4 reason code 4 and related data areas

On Fri, 20 Apr 2012 17:19:25 -0400 Micheal Butz 
wrote:

:>Was wondering If someone could clear up some things for me

:>A S0C4 reason code 4 means the storage key and the PSW key don't match
:>typically trying to access storage key 0 when the PSW key is key 8

Usually update, but on occasion fetch.

:>Two questions arise from this

:>. Does it matter what the PSW key at the time of the STORAGE
OBTAIN
:>was e.g.  

:>1.   Obtaining storage from subpool 0 where the storage key is 8 and
PSW
:>key at the time for what ever reason was in KEY 0.

What does "Obtaining storage from subpool 0 where the storage key is 8"
mean?
TCB key?

:> Would I have to set the PSW Key to 0 if I were trying to access that
:>storage later on say while running in some other task because when I did
the
:>STORAGE OBTAIN the PSW KEY 8 - 11 was 0

SP=0 when Supervisor/key=0 is special in that it is converted to subpool 252
which is in key 0.

:>2.   The same situation would be then true if access CSA storage
subpool
:>241 with Key=8 ( Iknow a no no) but the PSW KEY was 0. Later on when
trying
:>to access/modify the storage would I have to set PSW key 8 - 11 have to be
0

:>. Of what significance does is the key the TCB (TCBPKF) since it
:>seems only PSW KEY 8 - 11 and the key the page of the storage is seems to
be
:>relevant

Look at the "Selecting the Right Subpool for Your Virtual Storage Request"
section  in "MVS Programming: Authorized Assembler Services Guide"

--
Binyamin Dissen 
http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


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Explination of S0C4 reason code 4 and related data areas

[Micheal Butz]

Hi,

 

Was wondering If someone could clear up some things for me

 

 

A S0C4 reason code 4 means the storage key and the PSW key don't match
typically trying to access storage key 0 when the PSW key is key 8

 

Two questions arise from this

 

. Does it matter what the PSW key at the time of the STORAGE OBTAIN
was e.g.  

 

 

1.   Obtaining storage from subpool 0 where the storage key is 8 and PSW
key at the time for what ever reason was in KEY 0.
 Would I have to set the PSW Key to 0 if I were trying to access that
storage later on say while running in some other task because when I did the
STORAGE OBTAIN the PSW KEY 8 - 11 was 0

 

2.   The same situation would be then true if access CSA storage subpool
241 with Key=8 ( Iknow a no no) but the PSW KEY was 0. Later on when trying
to access/modify the storage would I have to set PSW key 8 - 11 have to be 0
 

 

 

. Of what significance does is the key the TCB (TCBPKF) since it
seems only PSW KEY 8 - 11 and the key the page of the storage is seems to be
relevant

 

 

Thanks


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Re: 0C4 pic 4

[Micheal Butz]

Being in PSW Key 0 is good for any storage 0 - 16 



-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Sunday, April 15, 2012 1:42 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: 0C4 pic 4

No, because if you arbitrarily use the key as determined by IVSK, why not
simply do it in Key 0?

On Sun, 15 Apr 2012 13:29:55 -0400 Micheal Butz 
wrote:

:>Hi,
:>
:> 
:>
:> 
:>
:> I am getting S0C4 04 within a wait which leads me to believe that the
:>storage key of the ECB storage key is not the same as the PSW STORAGE KEY
:>8- 11
:>
:> 
:>
:> 
:>
:>Does the following code make sense to resolve this address
:>
:> 
:>
:> 
:>
:>TESTAUTH FCTN=1  TEST APF AUTORIZATION 
:>
:>LTR   R15,R5 CHECK R15 
:>
:>BNZ   NAPF&SYSNDXNOT APF   
:>
:>MODESET MODE=SUP,KEY=NZERO  TURN ON BIT 15 IN PSW  
:>
:>LAR0,REPLY_ECB  GET ECB ADDRESS
:>
:>IVSK  R1,R0 GET STORAGE KEY
:>
:>MODESET KEYREG=R1,SAVEKEY=OLDKEY SET STORAGE KEY IN PSW 
:>
:>
:>
:>  WAIT=REPLY_ECB
:>
:> 
:>
:>   MODESET MODE=PROB,KEY=NZERO   back to current TCB key   

--
Binyamin Dissen 
http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


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0C4 pic 4

[Micheal Butz]

Hi,

 

 

 I am getting S0C4 04 within a wait which leads me to believe that the
storage key of the ECB storage key is not the same as the PSW STORAGE KEY
8- 11

 

 

Does the following code make sense to resolve this address

 

 

TESTAUTH FCTN=1  TEST APF AUTORIZATION 

LTR   R15,R5 CHECK R15 

BNZ   NAPF&SYSNDXNOT APF   

MODESET MODE=SUP,KEY=NZERO  TURN ON BIT 15 IN PSW  

LAR0,REPLY_ECB  GET ECB ADDRESS

IVSK  R1,R0 GET STORAGE KEY

MODESET KEYREG=R1,SAVEKEY=OLDKEY SET STORAGE KEY IN PSW 



  WAIT=REPLY_ECB

 

   MODESET MODE=PROB,KEY=NZERO   back to current TCB key


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Re: System completion code 201

[Micheal Butz]

There is a reason I have CSA in KEY 8

Was just wondering If I have to do an explicit modeset to key=8

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Walt Farrell
Sent: Tuesday, April 10, 2012 7:02 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: System completion code 201

On Tue, 10 Apr 2012 18:07:28 -0400, Micheal Butz 
wrote:

>Hi
>
>I have a piece of CSA storage sp 241
>That I am obtaining in key 8
>(I know this is a no no)
>
>When go to supervisor state should i code KEY=NZERO on the modeset I am
assuming
>NZERO is 8 or should I specifically set the storage key to 8

What you -should- do is use a system key for your CSA storage (as you know).
Why not start by doing a proper design and architecture rather than doing
something you know from the outset is wrong?

-- 
Walt

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System completion code 201

[Micheal Butz]

Hi

I have a piece of CSA storage sp 241
That I am obtaining in key 8
(I know this is a no no)

When go to supervisor state should i code KEY=NZERO on the modeset I am assuming
NZERO is 8 or should I specifically set the storage key to 8


As I am getting a system 201 durning a post/wait of an ECB from this storage

Thanks

Sent from my iPhone

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Re: SLIP PER Sotroage Alteration SVC dump

[Micheal Butz]

THANKS

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Wayne Driscoll
Sent: Friday, April 06, 2012 4:55 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SLIP PER Sotroage Alteration SVC dump

Either use STATUS REGS which shows the PSW and REGS when the slip trapped, 
or look at the contents of the SDUMP CSA resident buffer (CVTSDBUF) which 
has data on the state of the system when the slip trap hit.

===
Wayne Driscoll
OMEGAMON DB2 L3 Support/Development
wdrisco(AT)us.ibm.com
===



From:
Micheal Butz 
To:
IBM-MAIN@bama.ua.edu
Date:
04/06/2012 03:42 PM
Subject:
SLIP PER Sotroage Alteration SVC dump
Sent by:
IBM Mainframe Discussion List 



Hi,

 

I just got a hit and generated an SVC dump from a SLIP Storage Alteration 

 

 

My memory sort of escapes me on what IPCS option I would find the culprit
that  caused the storage overlay

 

>From memory I do believe it would be one of the IPCS traces if someone 
could
help

 

I would appreciate it

 

Thanks

 

 


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SLIP PER Sotroage Alteration SVC dump

[Micheal Butz]

Hi,

 

I just got a hit and generated an SVC dump from a SLIP Storage Alteration 

 

 

My memory sort of escapes me on what IPCS option I would find the culprit
that  caused the storage overlay

 

>From memory I do believe it would be one of the IPCS traces if someone could
help

 

I would appreciate it

 

Thanks

 

 


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Re: tcp/ip EZASMI concurrent server problem GIVE/TAKESOCET

[Micheal Butz]

Regarding the Client id Structure is its value important or  as long as The 
Clientid of the GiveSocket matches the takesocket I should be OK 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of 
Scott Ford
Sent: Wednesday, April 04, 2012 12:06 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: tcp/ip EZASMI concurrent server problem GIVE/TAKESOCET

Alan,

I write sockets all the time the sys1.samplib examples are excellent and work 
with just a tiny bit of tweaking..

Hth
Regards,

Sent from my iPad
Scott Ford
Senior Systems Engineer
www.identityforge.com



On Apr 4, 2012, at 12:35 AM, Alan Altmark  wrote:

> On Tue, 3 Apr 2012 12:01:47 -0400, Micheal Butz  
> wrote:
>> When I get incoming connection via SELECT/ACCEPT I move the low order ½ from
>> retocde from the accept call which is the new socket I will be communicating
>> to SERV_SOCK so far so good
>> 
>> (it happens to be a 4). I then do a GIVESOCKET using the SERV_SOCK (4)
>> getting a return code 0, 
>> 
>> I then POST the subtask to execute the TAKESOCKET using the SERV_SOCK  were
>> I get errno of X’71’
>> 
>>   113  EBADF  TAKESOCKET  the socket has already been
>> taken   
>> 
>> Am I doing anything wrong in this scenario
> 
> Did you remember to wait for the TAKESOCKET to complete before you CLOSE the 
> socket in the main task?  And are you specifying the correct clientid 
> structure?  I didn't see you passing any clientid information in your 
> parameter list.
> 
> Alan Altmark
> IBM
> 
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tcp/ip EZASMI concurrent server problem GIVE/TAKESOCET

[Micheal Butz]

Hi,

 

I have an assembler concurrent server using the EZASMI interface, I am using
4 ports from my IP address 192.168.1.111 I do a socket,bind listen using
ip,port,socket

I create four subtasks (ATTACH) to process connection on these 4 ports, I
pass these task a parameter list of KEY 8 subpool 1 storage by which I will
communication with them e.g. ECB and socket info

This is a layout of that storage 

 

THREAD_DSECT DSECT  

ECB_ADDR DS  XL4  FOR SUBTASK TO WAIT FOR WORK

TASK_ADDR_1  DS  XL4  TCB ADDRESS   

SOCKET   DS  XL2  ORIGNAL SOCKET OF SERVER  

SERV_SOCKDS  XL2  SOCKET CREATE VIA accept API 

FIN_ECB  DS  XL4

END_ECB  DS  XL4

TIE_DSECTDS  XL(TIELENTH)  TASK WORK AREA   

 

 

Then I wait…….

 

When I get incoming connection via SELECT/ACCEPT I move the low order ½ from
retocde from the accept call which is the new socket I will be communicating
to SERV_SOCK so far so good

(it happens to be a 4). I then do a GIVESOCKET using the SERV_SOCK (4)
getting a return code 0, 

 

I then POST the subtask to execute the TAKESOCKET using the SERV_SOCK  were
I get errno of X’71’

 

113  EBADF  TAKESOCKET  the socket has already been
taken   

 

Am I doing anything wrong in this scenario

 

 

   Thanks

  

 


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Debugging EZASMI

[Micheal Butz]

Hi,

 

I am trying to debug a TCP/IP server as a template I am using the following
flow chart from a document by Tony Thigpen

 

http://dinomasters.com/coolstuff/2004EZA.pdf

 

My Client is a Windows MFC C++ program

 

I have multiple connections going as per the document

 

The accept macro I have coded to accept the connection 

 

Does not have any value for the second parameter to the socket name, the doc
says this a input parameter  ">>__EZASMI__TYPE=ACCEPT__,S__=__ _number___
__,NAME__=__ _address__ _>

S 

Input parameter. A value or the address of a halfword binary number
specifying the descriptor of the socket from which the connection is
accepted"

 

 

 

 

For the first connection Select and subsequent Accept work and I am able to
have a subtask do the work read/write

 

On the second connection the Accept hangs TCP/IP does not post the ECB 

 

I have been debugging the Assembler started task under TSO TESTAUTH

 

I have also coded a STIMERM exit to POST the TCP/IP ecb however when code
reaches the STIMERM exit I get abend 138 which according to the doc is
totally off base (having to do with global resource serialization 

 

So in summation I have 2 questions

 

. Using the document flow below for action 4 would the accept macro
in this case need a value for the socket

 

. Would anyone have a idea would I would be getting a abend code 138
at entry to the STIMERM exit

 

thanks



 

 


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EZASMI debugging and stimer routine

[Micheal Butz]

Hi,

 

I have a two folded question First on debugging a TCP/IP program using the
EZASMI interface. Second a question about the EZASMI ACCEPT service

 



 

. I have been writing TCP/IP started task to communicate with
Windows MFC C++ The Assembler started task uses the EZASMI interface posting
an ECB when the service is complete.

 

This is well and good when the EZASMI service has  no debugs however when it
does the ECB is never posted and my program hangs

 

Robb Scott suggested waiting on a multiple ECB list and having one ECB
posted when a certain time interval expired 

 

The question is how to go about this as the STIMER exit routine and program
do not share addressability nor does the stimer exit routine accept
parameters

 

 

. Second the EZASMI service that hangs the ACCEPT service  the
second parameters is the port 

>>__EZASMI__TYPE=ACCEPT__,S__=__ _number___ __,NAME__=__ _address__ _>

 

|_address__||_*indaddr_|

   |_*indaddr_||_(reg)|

   |_(reg)|

 

   >__,ERRNO__=__ _address__ __,RETCODE__=__ _address__
>

 |_*indaddr_|   |_*indaddr_|

 |_(reg)|   |_(reg)|

 

   >__ __ __ _
_>

  |_,NS__=__ _number___ _|  |_,ECB=_ _address__ __|

|_address__||   |_*indaddr_|  |

|_*indaddr_||   |_(reg)|  |

|_(reg)||_,REQAREA=_ _address__ __|

|_*indaddr_|

|_(reg)|

 

   >__ _ __ 
__><

  |_,ERROR__=__ _address__ _|  |_,TASK__=__ _address__ _|

   |_*indaddr_||_*indaddr_|

   |_(reg)||_(reg)|

 

   S 

Input parameter. A value or the address of a halfword binary number
specifying the descriptor of the socket from which the connection is
accepted. 

NAME 

 

 

The doc say this is a input parameter meaning I have to specify one the
sockets the I have bound for listening right ???

 

However the only time the ACCEPT service works is when I do not populate
this field

 

 

 

Any help on any of these 2 questions is appreciated 

 

Thanks


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Re: WTOR problem

[Micheal Butz]

Thanks

worked

WTO_D_CON WTOR TEXT=(,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=L  model
statement
WTO_D_CON_LEN  EQU  *-WTO_D_CON

Followed by

 WTOR   TEXT=D_MSG,MF=(E,WTO_D_LST) 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Rob Scott
Sent: Monday, March 19, 2012 10:17 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem

I do not think so.

There could well be parameter list contents that are not set during MF=E
logic that are primed by MF=L. 

Just because you specify all possible parameters does not mean that WTOR/WTO
MF=E will generate a fully constructed parameter list.

It is a historical thing - and developers just have to put up with it and
use the "move the model in" technique.

Be warned - there are other macros like this around.

Rob Scott
Lead Developer
Rocket Software
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 19 March 2012 14:07
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem

Rob,

I understand that however moving the model *statement* would be sufficient
if I coded WTOR MF=(E,WTOR_LIST) By coding 

WTOR   TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_LX
   ST)  

With the parameters the macro should populate the parameter list

 
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Rob Scott
Sent: Monday, March 19, 2012 8:52 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem

WTOR and WTO are macros that require a model parameter list to be
constructed and populated *before* you issue the MF=E form.

Zeroing the parameter list is NOT sufficient - you must move in a model MF=L
form just before the MF=E invocation.

More modern macros have the ",COMPLETE" option on the MF=E specification,
unfortunately some of the older macros do not have this functionality.  

Rob Scott
Lead Developer
Rocket Software
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 19 March 2012 12:45
To: IBM-MAIN@bama.ua.edu
Subject: WTOR problem

Hi,

 

I am having problems with following coding generating a re-entrable version
of the WTOR below is the relvant code

 

  LTORG

 DEBUG_MESS DC  C'THE BASE ADDRESS IS  '

 TBL  DC240X'00'   

  DCC'0123456789ABCDEF'

 

 

WS_DSECT   DSECT

D_MSG  DS   AL2 

   DS   CL29

WORKFLDDS   CL9

BASE_ADDR  DS   XL5

REPLY_AREA DS   X

REPLY_LEN  EQU  1

REPLY_ECB  DS   F   

WTO_D_LST WTOR TEXT=(,,,),MF=L 

WTO_D_LST_LEN  EQU  *-WTO_D_LST

 

 

  STR3,BASE_ADDR

  UNPK  WORK_FLD,BASE_ADDR  

  TRWORK_FLD,TBL

  MVC   D_MSG+2(L'DEBUG_MESS),DEBUG_MESS

  MVC   D_MSG+22(8),WORK_FLD

  MVC   D_MSG(2),=AL2(L'DEBUG_MESS) 

  XCWTO_D_LST(WTO_D_LST_LEN),WTO_D_LST  

 WTOR   TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_L

ST) 



  WAIT ECB=REPLY_ECB



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Re: WTOR problem

[Micheal Butz]

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Rob Scott
Sent: Monday, March 19, 2012 10:17 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem

I do not think so.

There could well be parameter list contents that are not set during MF=E
logic that are primed by MF=L. 

Just because you specify all possible parameters does not mean that WTOR/WTO
MF=E will generate a fully constructed parameter list.

It is a historical thing - and developers just have to put up with it and
use the "move the model in" technique.

Be warned - there are other macros like this around.

Rob Scott
Lead Developer
Rocket Software
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 19 March 2012 14:07
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem

Rob,

I understand that however moving the model *statement* would be sufficient
if I coded WTOR MF=(E,WTOR_LIST) By coding 

WTOR   TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_LX
   ST)  

With the parameters the macro should populate the parameter list

 
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Rob Scott
Sent: Monday, March 19, 2012 8:52 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem

WTOR and WTO are macros that require a model parameter list to be
constructed and populated *before* you issue the MF=E form.

Zeroing the parameter list is NOT sufficient - you must move in a model MF=L
form just before the MF=E invocation.

More modern macros have the ",COMPLETE" option on the MF=E specification,
unfortunately some of the older macros do not have this functionality.  

Rob Scott
Lead Developer
Rocket Software
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 19 March 2012 12:45
To: IBM-MAIN@bama.ua.edu
Subject: WTOR problem

Hi,

 

I am having problems with following coding generating a re-entrable version
of the WTOR below is the relvant code

 

  LTORG

 DEBUG_MESS DC  C'THE BASE ADDRESS IS  '

 TBL  DC240X'00'   

  DCC'0123456789ABCDEF'

 

 

WS_DSECT   DSECT

D_MSG  DS   AL2 

   DS   CL29

WORKFLDDS   CL9

BASE_ADDR  DS   XL5

REPLY_AREA DS   X

REPLY_LEN  EQU  1

REPLY_ECB  DS   F   

WTO_D_LST WTOR TEXT=(,,,),MF=L 

WTO_D_LST_LEN  EQU  *-WTO_D_LST

 

 

  STR3,BASE_ADDR

  UNPK  WORK_FLD,BASE_ADDR  

  TRWORK_FLD,TBL

  MVC   D_MSG+2(L'DEBUG_MESS),DEBUG_MESS

  MVC   D_MSG+22(8),WORK_FLD

  MVC   D_MSG(2),=AL2(L'DEBUG_MESS) 

  XCWTO_D_LST(WTO_D_LST_LEN),WTO_D_LST  

 WTOR   TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_L

ST) 



  WAIT ECB=REPLY_ECB



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Re: WTOR problem

[Micheal Butz]

Rob,

I understand that however moving the model *statement* would be sufficient
if I coded WTOR MF=(E,WTOR_LIST)
By coding 

WTOR   TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_LX
   ST)  

With the parameters the macro should populate the parameter list

 
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Rob Scott
Sent: Monday, March 19, 2012 8:52 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem

WTOR and WTO are macros that require a model parameter list to be
constructed and populated *before* you issue the MF=E form.

Zeroing the parameter list is NOT sufficient - you must move in a model MF=L
form just before the MF=E invocation.

More modern macros have the ",COMPLETE" option on the MF=E specification,
unfortunately some of the older macros do not have this functionality.  

Rob Scott
Lead Developer
Rocket Software
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 19 March 2012 12:45
To: IBM-MAIN@bama.ua.edu
Subject: WTOR problem

Hi,

 

I am having problems with following coding generating a re-entrable version
of the WTOR below is the relvant code

 

  LTORG

 DEBUG_MESS DC  C'THE BASE ADDRESS IS  '

 TBL  DC240X'00'   

  DCC'0123456789ABCDEF'

 

 

WS_DSECT   DSECT

D_MSG  DS   AL2 

   DS   CL29

WORKFLDDS   CL9

BASE_ADDR  DS   XL5

REPLY_AREA DS   X

REPLY_LEN  EQU  1

REPLY_ECB  DS   F   

WTO_D_LST WTOR TEXT=(,,,),MF=L 

WTO_D_LST_LEN  EQU  *-WTO_D_LST

 

 

  STR3,BASE_ADDR

  UNPK  WORK_FLD,BASE_ADDR  

  TRWORK_FLD,TBL

  MVC   D_MSG+2(L'DEBUG_MESS),DEBUG_MESS

  MVC   D_MSG+22(8),WORK_FLD

  MVC   D_MSG(2),=AL2(L'DEBUG_MESS) 

  XCWTO_D_LST(WTO_D_LST_LEN),WTO_D_LST  

 WTOR   TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_L

ST) 



  WAIT ECB=REPLY_ECB



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WTOR problem

[Micheal Butz]

Hi,

 

I am having problems with following coding generating a re-entrable version
of the WTOR below is the relvant code

 

  LTORG

 DEBUG_MESS DC  C'THE BASE ADDRESS IS  '

 TBL  DC240X'00'   

  DCC'0123456789ABCDEF'

 

 

WS_DSECT   DSECT

D_MSG  DS   AL2 

   DS   CL29

WORKFLDDS   CL9

BASE_ADDR  DS   XL5

REPLY_AREA DS   X

REPLY_LEN  EQU  1

REPLY_ECB  DS   F   

WTO_D_LST WTOR TEXT=(,,,),MF=L 

WTO_D_LST_LEN  EQU  *-WTO_D_LST

 

 

  STR3,BASE_ADDR

  UNPK  WORK_FLD,BASE_ADDR  

  TRWORK_FLD,TBL

  MVC   D_MSG+2(L'DEBUG_MESS),DEBUG_MESS

  MVC   D_MSG+22(8),WORK_FLD

  MVC   D_MSG(2),=AL2(L'DEBUG_MESS) 

  XCWTO_D_LST(WTO_D_LST_LEN),WTO_D_LST  

 WTOR   TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_L

ST) 



  WAIT ECB=REPLY_ECB



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Re: Enclave SRB's

[Micheal Butz]

thanks

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Rob Scott
Sent: Friday, March 16, 2012 11:46 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Enclave SRB's

Have a look in the following manuals :

"Authorized Assembler Services Guide" 
"Authorized Assembler Services Reference"
"Workload Management Services"

Hints : IEAMSCHD and  IWM4ECRE 

Rob Scott
Lead Developer
Rocket Software
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 16 March 2012 15:35
To: IBM-MAIN@bama.ua.edu
Subject: Enclave SRB's

Hi,

 

I am looking for information on the use of enclave SRB/TCB's maybe an
example of the usage

 

 

Thanks 


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Enclave SRB's

[Micheal Butz]

Hi,

 

I am looking for information on the use of enclave SRB/TCB's maybe an
example of the usage

 

 

Thanks 


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Re: LAE instruction

[Micheal Butz]

You are right about LAE vs L.  

As far as being on my dual/pasn list


If Saar then load Arx with 1 will go to secondary with out being on my list
Sent from my iPhone

On Mar 6, 2012, at 9:52 PM, Ngafei Huang  wrote:

> Chaining these control blocks requires supporting environment and setups as 
> follow:
> 
> AR register basing ASNALET needs to be setup.
> 
> AR register basing ASXBFTCB needs to be setup.
> 
> Instead of "LAE R4,TCBRBP", it should be "L R4,TCBRBP".
> 
> Target address space needs to be on your access-list.
> 
> Target address space must be non-swappable.
> 
> 
> Raymond Wong
> 
> 
> 
> -Original Message-
> From: Micheal Butz 
> To: IBM-MAIN 
> Sent: Tue, Mar 6, 2012 8:30 pm
> Subject: Re: LAE instruction
> 
> 
> Or a more practical use of LAE
> 
> s chaing thru control blocks from another address space 
> AC. 512
> AM   R3,R3,ASNALET
> .   R3,ASXBFTCB
> SING TCB,R3
> AE.   R4,TCBRBP
> SING R4,RB
> 
> 
> ent from my iPhone
> On Mar 6, 2012, at 5:53 PM, Rob Scott  wrote:
>> Micheal, 
> 
> Putting a bit of "meat on the bones" to create an example piece of code with 
> omments and notes :
> 
> (o) We are going to process a linked list of "FOO" elements in a dataspace 
> and 
> alculate some random hash value based on a subset of bytes in the FOO_NAME 
> ield.
> (o) This code has been just typed into my e-mail - they may be typos/errors
> (o) "WA" is the working storage structure/DSECT
> 
> 
> DO,
>ALESERV ADD,STOKEN=WA_FOO_STOKEN,  Add dataspace containing linked 
> list 
> f FOOs
>ALET=WA_FOO_ALET,  
>AL=WORKUNIT,
>   MF=(E,WA_ALESERV_LIST)
>DOEXIT (LTR,R15,R15,NZ)Failed - quick exit
>SAC512AR-Mode (1)
>SYSSTATE ASCENV=ARInform assembler of AR-mode
>LR6,WA_FOO_HEADGet head of list
>LAMAR6,AR6,WA_FOO_ALETGet dataspace ALET (2) 
>USING FOO,R6
>DO UNTIL=(ICM,R6,B'',FOO_NEXT,Z)Traverse list (3)
>LAER7,FOO_NAMEPoint to FOO_NAME (4)
>LAER1,8(,R7)Use R1 for temp pointer (5)
>XCWA_HASH,WA_HASHZero hash value
>DO FROM=(R14,=AL4(L'FOO_NAME-8))
>XRR0,R0
>ICR0,0(,R1)Get 1-byte (6)
>ALR0,WA_HASHAdd to hash value
>STR0,WA_HASHStore new value
>LAER1,1(,R1)Next byte of name (6)
>ENDDO
>NCWA_HASH,=X'00FF'0-255 range for hash
>ENDDO
>SAC0Inform assembler (7)
>SYSSTATE ASCENV=P
> ENDDO(8)
> 
> rest of code (9)
> 
> Notes :
> 
> (1) I think it is always worth having a macro to do both the SAC and the 
> YSSTATE for you in one hit (not shown)- stops you forgetting the SYSSTATE and 
> hat can confuse any macros that follow.
> (2) Loading the ALET in to the AR for the first time - R6 will be able to 
> ddress data in the dataspace
> (3) AR-mode makes traversing data structures in dataspaces easy as you can 
> ust use normal instructions (if you play by the rules)
> (4) Because LAE used and FOO dsect covers R6+AR6 - AR7 will contain ALET for 
> ataspace after instruction executed
> (5) This time we are using R1 to point at 8 bytes into FOO_NAME (for whatever 
> eason) - note that AR1 will get the dataspace ALET
> (6) Loading and using a byte from the dataspace 
> (7) See (1) 
> (8) Assuming all ARs are zero before we start, if the code goes thru 
> uccessfully, then AR1, AR6 and AR7 will contain the ALET of the dataspace 
> here 
> you may wish to consider zeroing the ARs at this point if they are no longer 
> eeded.
> (9) Prudent use of "LAM   AR14,AR1,=4A(0)" will protect you from 
> unintentional 
> R values in "working" regs after calling certain system services - you can 
> ever be sure how in-house macros expand.  
> 
> Hope this helps
> 
> 
> Rob Scott
> Lead Developer
> Rocket Software
> 275 Grove Street * Newton, MA 02466-2272 * USA
> Tel: +1.781.684.2305
> Email: rsc...@rs.com
> Web: www.rocketsoftware.com
> 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of 
> icheal Butz
> Sent: 06 March 2012 21:53
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: LAE instruction
> 
> So  SAC 512
>LAE R3,0(,R4)
> 
> R3 is CPYA 

Re: LAE instruction

[Micheal Butz]

Or a more practical use of LAE


Is chaing thru control blocks from another address space 
SAC. 512
LAM   R3,R3,ASNALET
L.   R3,ASXBFTCB
USING TCB,R3
LAE.   R4,TCBRBP
USING R4,RB




Sent from my iPhone

On Mar 6, 2012, at 5:53 PM, Rob Scott  wrote:

> Micheal, 
> 
> Putting a bit of "meat on the bones" to create an example piece of code with 
> comments and notes :
> 
> (o) We are going to process a linked list of "FOO" elements in a dataspace 
> and calculate some random hash value based on a subset of bytes in the 
> FOO_NAME field.
> (o) This code has been just typed into my e-mail - they may be typos/errors
> (o) "WA" is the working storage structure/DSECT
> 
> 
> DO,
>ALESERV ADD,STOKEN=WA_FOO_STOKEN,  Add dataspace containing linked 
> list of FOOs
>ALET=WA_FOO_ALET,  
>AL=WORKUNIT,
>   MF=(E,WA_ALESERV_LIST)
>DOEXIT (LTR,R15,R15,NZ)Failed - quick exit
>SAC512AR-Mode (1)
>SYSSTATE ASCENV=ARInform assembler of AR-mode
>LR6,WA_FOO_HEADGet head of list
>LAMAR6,AR6,WA_FOO_ALETGet dataspace ALET (2) 
>USING FOO,R6
>DO UNTIL=(ICM,R6,B'',FOO_NEXT,Z)Traverse list (3)
>LAER7,FOO_NAMEPoint to FOO_NAME (4)
>LAER1,8(,R7)Use R1 for temp pointer (5)
>XCWA_HASH,WA_HASHZero hash value
>DO FROM=(R14,=AL4(L'FOO_NAME-8))
>XRR0,R0
>ICR0,0(,R1)Get 1-byte (6)
>ALR0,WA_HASHAdd to hash value
>STR0,WA_HASHStore new value
>LAER1,1(,R1)Next byte of name (6)
>ENDDO
>NCWA_HASH,=X'00FF'0-255 range for hash
>ENDDO
>SAC0Inform assembler (7)
>SYSSTATE ASCENV=P
> ENDDO(8)
> 
> rest of code (9)
> 
> Notes :
> 
> (1) I think it is always worth having a macro to do both the SAC and the 
> SYSSTATE for you in one hit (not shown)- stops you forgetting the SYSSTATE 
> and that can confuse any macros that follow.
> (2) Loading the ALET in to the AR for the first time - R6 will be able to 
> address data in the dataspace
> (3) AR-mode makes traversing data structures in dataspaces easy as you can 
> just use normal instructions (if you play by the rules)
> (4) Because LAE used and FOO dsect covers R6+AR6 - AR7 will contain ALET for 
> dataspace after instruction executed
> (5) This time we are using R1 to point at 8 bytes into FOO_NAME (for whatever 
> reason) - note that AR1 will get the dataspace ALET
> (6) Loading and using a byte from the dataspace 
> (7) See (1) 
> (8) Assuming all ARs are zero before we start, if the code goes thru 
> successfully, then AR1, AR6 and AR7 will contain the ALET of the dataspace 
> here - you may wish to consider zeroing the ARs at this point if they are no 
> longer needed.
> (9) Prudent use of "LAM   AR14,AR1,=4A(0)" will protect you from 
> unintentional AR values in "working" regs after calling certain system 
> services - you can never be sure how in-house macros expand.  
> 
> Hope this helps
>
> 
> Rob Scott
> Lead Developer
> Rocket Software
> 275 Grove Street * Newton, MA 02466-2272 * USA
> Tel: +1.781.684.2305
> Email: rsc...@rs.com
> Web: www.rocketsoftware.com
> 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of Micheal Butz
> Sent: 06 March 2012 21:53
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: LAE instruction
> 
> So  SAC 512
>LAE R3,0(,R4)
> 
> R3 is CPYA from access R4  right 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of McKown, John
> Sent: Tuesday, March 06, 2012 4:22 PM
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: LAE instruction
> 
> Yes, from the LAE instruction text:
> 
> 
> The address specified by the X2, B2, and D2 fields is placed in general 
> register R1. Access register R1 is loaded with a value that depends on the 
> current value of the address-space-control bits, bits 16 and
> 17 of the PSW. If the address-space-control bits are
> 01 binary, the value placed in the access register also depends on whether 
> the B2 field is zero or non- zero.
> 
> ...
> 
> PSW Bits
> 16 and 17
> Value Placed in Access Register R1
> 00  hex (zeros in bit positions 0-31)
> 
> 10 0001 hex (zeros

Re: LAE instruction

[Micheal Butz]

I see thanks the displacement used calculating Gr.   If not for LAE

You would have to use L RX,8(,RY)
Then CPYA. RX,RY. Rob
Thanks for explanation of practical
Use of LAE













Sent from my iPhone

On Mar 6, 2012, at 5:53 PM, Rob Scott  wrote:

> Micheal, 
> 
> Putting a bit of "meat on the bones" to create an example piece of code with 
> comments and notes :
> 
> (o) We are going to process a linked list of "FOO" elements in a dataspace 
> and calculate some random hash value based on a subset of bytes in the 
> FOO_NAME field.
> (o) This code has been just typed into my e-mail - they may be typos/errors
> (o) "WA" is the working storage structure/DSECT
> 
> 
> DO,
>ALESERV ADD,STOKEN=WA_FOO_STOKEN,  Add dataspace containing linked 
> list of FOOs
>ALET=WA_FOO_ALET,  
>AL=WORKUNIT,
>   MF=(E,WA_ALESERV_LIST)
>DOEXIT (LTR,R15,R15,NZ)Failed - quick exit
>SAC512AR-Mode (1)
>SYSSTATE ASCENV=ARInform assembler of AR-mode
>LR6,WA_FOO_HEADGet head of list
>LAMAR6,AR6,WA_FOO_ALETGet dataspace ALET (2) 
>USING FOO,R6
>DO UNTIL=(ICM,R6,B'',FOO_NEXT,Z)Traverse list (3)
>LAER7,FOO_NAMEPoint to FOO_NAME (4)
>LAER1,8(,R7)Use R1 for temp pointer (5)
>XCWA_HASH,WA_HASHZero hash value
>DO FROM=(R14,=AL4(L'FOO_NAME-8))
>XRR0,R0
>ICR0,0(,R1)Get 1-byte (6)
>ALR0,WA_HASHAdd to hash value
>STR0,WA_HASHStore new value
>LAER1,1(,R1)Next byte of name (6)
>ENDDO
>NCWA_HASH,=X'00FF'0-255 range for hash
>ENDDO
>SAC0Inform assembler (7)
>SYSSTATE ASCENV=P
> ENDDO(8)
> 
> rest of code (9)
> 
> Notes :
> 
> (1) I think it is always worth having a macro to do both the SAC and the 
> SYSSTATE for you in one hit (not shown)- stops you forgetting the SYSSTATE 
> and that can confuse any macros that follow.
> (2) Loading the ALET in to the AR for the first time - R6 will be able to 
> address data in the dataspace
> (3) AR-mode makes traversing data structures in dataspaces easy as you can 
> just use normal instructions (if you play by the rules)
> (4) Because LAE used and FOO dsect covers R6+AR6 - AR7 will contain ALET for 
> dataspace after instruction executed
> (5) This time we are using R1 to point at 8 bytes into FOO_NAME (for whatever 
> reason) - note that AR1 will get the dataspace ALET
> (6) Loading and using a byte from the dataspace 
> (7) See (1) 
> (8) Assuming all ARs are zero before we start, if the code goes thru 
> successfully, then AR1, AR6 and AR7 will contain the ALET of the dataspace 
> here - you may wish to consider zeroing the ARs at this point if they are no 
> longer needed.
> (9) Prudent use of "LAM   AR14,AR1,=4A(0)" will protect you from 
> unintentional AR values in "working" regs after calling certain system 
> services - you can never be sure how in-house macros expand.  
> 
> Hope this helps
>
> 
> Rob Scott
> Lead Developer
> Rocket Software
> 275 Grove Street * Newton, MA 02466-2272 * USA
> Tel: +1.781.684.2305
> Email: rsc...@rs.com
> Web: www.rocketsoftware.com
> 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of Micheal Butz
> Sent: 06 March 2012 21:53
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: LAE instruction
> 
> So  SAC 512
>LAE R3,0(,R4)
> 
> R3 is CPYA from access R4  right 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of McKown, John
> Sent: Tuesday, March 06, 2012 4:22 PM
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: LAE instruction
> 
> Yes, from the LAE instruction text:
> 
> 
> The address specified by the X2, B2, and D2 fields is placed in general 
> register R1. Access register R1 is loaded with a value that depends on the 
> current value of the address-space-control bits, bits 16 and
> 17 of the PSW. If the address-space-control bits are
> 01 binary, the value placed in the access register also depends on whether 
> the B2 field is zero or non- zero.
> 
> ...
> 
> PSW Bits
> 16 and 17
> Value Placed in Access Register R1
> 00  hex (zeros in bit positions 0-31)
> 
> 10 0001 hex (zeros

Re: LAE instruction

[Micheal Butz]

But plays no role as far as access register value

Sent from my iPhone

On Mar 6, 2012, at 3:48 PM, "Shmuel Metz (Seymour J.)" 
 wrote:

> In <02fb01ccfbcb$fca77eb0$f5f67c10$@net>, on 03/06/2012
>   at 02:04 PM, Micheal Butz  said:
> 
>> . What would the sac value e.g. 256,512,768 have to be that
>> when using the LAE instructions with the following operands LAE 
>> 3,0(R4) would AR3 get loaded with AR4 
> 
> None; try LAE R3,0(,R4)
> 
>> Second what value does the displacement play in the instruction
> 
> It's added to the base and index registers.
> 
> -- 
> Shmuel (Seymour J.) Metz, SysProg and JOAT
> ISO position; see <http://patriot.net/~shmuel/resume/brief.html> 
> We don't care. We don't have to care, we're Congress.
> (S877: The Shut up and Eat Your spam act of 2003)
> 
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

Re: LAE instruction

[Micheal Butz]

I Know in access register mode  B2 ALWAYS implies corresponding AR

thanks 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Blaicher, Christopher Y.
Sent: Tuesday, March 06, 2012 4:27 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: LAE instruction

Yes, set the SAC bits first, otherwise the access register is set with
zeros.

The other point that others are making is that when in access register mode,
the instruction format is VERY important.

LAE  R3,(R4)  - loads the value from the location pointed to by R4 in the
home address space into R3 and sets the AR3 register with 0, regardless of
the SAC values at the time.

LAE  R3,0(0,R4)   - loads the value from the location pointed to by R4 in
the address space indicated by access register AR4, if the SAC value is
other than b'00', and loads AR3 with the SAC appropriate value.

Even if you never write access register sensitive code, it is far better to
use the correct instruction format.  A) It gets you in the habit; and B) You
never know when a piece of code may become access register sensitive.

Chris Blaicher
Senior Software Engineer, Software Services
Syncsort Incorporated
50 Tice Boulevard, Woodcliff Lake, NJ 07677
P: 201-930-8260  |  M: 512-627-3803    
E: cblaic...@syncsort.com

www.syncsort.com

Check out our Knowledge Base at www.syncsort.com/support

Syncsort aims for the best product and service experience. 
We welcome your feedback.


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: Tuesday, March 06, 2012 3:07 PM
To: MVS List Server 1
Subject: Re: LAE instruction

Sorry misspelled the name John McKown. Excuse me

Sent from my iPhone

On Mar 6, 2012, at 4:00 PM, Micheal Butz  wrote:

> John Mckiwns reply was a explanation of the SAC inst.Which I am aware
of
> 
> The Doc for LAE says the inst the functionality is dependent on PSW bits
> 
> 16 17 address space control bits these are set by the SAC inst
> 
> 
> So my original question remains does
> 
> Should address space control buts be set via the sac before executing the
LAE 
> 
> 
> Sent from my iPhone
> 
> On Mar 6, 2012, at 3:37 PM, Rob Scott  wrote:
> 
>> John McKown's reply covered these points very well
>> 
>> Rob Scott
>> Lead Developer
>> Rocket Software
>> 275 Grove Street * Newton, MA 02466-2272 * USA
>> Tel: +1.781.684.2305
>> Email: rsc...@rs.com
>> Web: www.rocketsoftware.com
>> 
>> 
>> -Original Message-
>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On
Behalf Of Micheal Butz
>> Sent: 06 March 2012 19:59
>> To: IBM-MAIN@bama.ua.edu
>> Subject: Re: LAE instruction
>> 
>> Thanks
>> 
>> Regarding my questions
>> 
>> The doc says the inst is dependent
>> On address space control bits which is set by the SAC inst. 
>> 
>> Secondly seems like the displacement doesn't play a role in the inst
>> 
>> Sent from my iPhone
>> 
>> On Mar 6, 2012, at 2:49 PM, Rob Scott  wrote:
>> 
>>>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE
R3,(R4,R0)"
>>> 
>>> Should read :
>>> 
>>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE
R3,0(R4,R0)"
>>> 
>>> Rob Scott
>>> Lead Developer
>>> Rocket Software
>>> 275 Grove Street * Newton, MA 02466-2272 * USA
>>> Tel: +1.781.684.2305
>>> Email: rsc...@rs.com
>>> Web: www.rocketsoftware.com
>>> 
>>> 
>>> -Original Message-
>>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On 
>>> Behalf Of Rob Scott
>>> Sent: 06 March 2012 19:47
>>> To: IBM-MAIN@bama.ua.edu
>>> Subject: Re: LAE instruction
>>> 
>>> Commas are *very* important in AR-mode
>>> 
>>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE
R3,(R4,R0)"
>>> 
>>> Coded that way there is no automatic way that AR3 is going to inherit
the AR4 value.
>>> 
>>> You need : "LAE   R3,0(,R4)"
>>> 
>>> This will ensure that AR3 is populated from the AR for the referenced
base register R4.
>>> 
>>> 
>>> Rob Scott
>>> Lead Developer
>>> Rocket Software
>>> 275 Grove Street * Newton, MA 02466-2272 * USA
>>> Tel: +1.781.684.2305
>>> Email: rsc...@rs.com
>>> Web: www.rocketsoftware.com
>>> 
>>> 
>>> -Original Message-
>>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On 
>

Re: LAE instruction

[Micheal Butz]

So  SAC 512
LAE R3,0(,R4)

 R3 is CPYA from access R4  right 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of McKown, John
Sent: Tuesday, March 06, 2012 4:22 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: LAE instruction

Yes, from the LAE instruction text:


The address specified by the X2, B2, and D2 fields is
placed in general register R1. Access register R1 is
loaded with a value that depends on the current
value of the address-space-control bits, bits 16 and
17 of the PSW. If the address-space-control bits are
01 binary, the value placed in the access register
also depends on whether the B2 field is zero or non-
zero.

...

PSW Bits
16 and 17
Value Placed in Access Register R1
00  hex (zeros in bit positions 0-31)

10 0001 hex (zeros in bit positions 0-30
and one in bit position 31)

01 If B2 field is zero:  hex (zeros in
bit positions 0-31)
If B2 field is nonzero: Contents of access
register B2

11 0002 hex (zeros in bit positions 0-29
and 31, and one in bit position 30)

>From the SAC instruction 

CodeName of ModeResult in PSW Bits 16 & 17
Primary space   00
0001Secondary space 10
0010Access register 01
0011Home space  11
All others Invalid



SAC 512 has is '0010' from the above and results in b'01' or AR mode in the
PSW bits 16 & 17. Which is what is required for the LAE instruction to set
the access register of the result access register from the base access
register (when not b'').



John McKown 

Systems Engineer IV

IT

 

Administrative Services Group

 

HealthMarkets(r)

 

9151 Boulevard 26 * N. Richland Hills * TX 76010

(817) 255-3225 phone * 

john.mck...@healthmarkets.com * www.HealthMarkets.com

 

Confidentiality Notice: This e-mail message may contain confidential or
proprietary information. If you are not the intended recipient, please
contact the sender by reply e-mail and destroy all copies of the original
message. HealthMarkets(r) is the brand name for products underwritten and
issued by the insurance subsidiaries of HealthMarkets, Inc. -The Chesapeake
Life Insurance Company(r), Mid-West National Life Insurance Company of
TennesseeSM and The MEGA Life and Health Insurance Company.SM

 

> -Original Message-
> From: IBM Mainframe Discussion List 
> [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz
> Sent: Tuesday, March 06, 2012 3:00 PM
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: LAE instruction
> 
> John Mckiwns reply was a explanation of the SAC inst.
> Which I am aware of
> 
> The Doc for LAE says the inst the functionality is dependent 
> on PSW bits
> 
> 16 17 address space control bits these are set by the SAC inst
> 
> 
> So my original question remains does
> 
> Should address space control buts be set via the sac before 
> executing the LAE 
> 
> 
> Sent from my iPhone
> 
> On Mar 6, 2012, at 3:37 PM, Rob Scott 
>  wrote:
> 
> > John McKown's reply covered these points very well
> > 
> > Rob Scott
> > Lead Developer
> > Rocket Software
> > 275 Grove Street * Newton, MA 02466-2272 * USA
> > Tel: +1.781.684.2305
> > Email: rsc...@rs.com
> > Web: www.rocketsoftware.com
> > 
> > 
> > -Original Message-
> > From: IBM Mainframe Discussion List 
> [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz
> > Sent: 06 March 2012 19:59
> > To: IBM-MAIN@bama.ua.edu
> > Subject: Re: LAE instruction
> > 
> > Thanks
> > 
> > Regarding my questions
> > 
> > The doc says the inst is dependent
> > On address space control bits which is set by the SAC inst. 
> > 
> > Secondly seems like the displacement doesn't play a role in the inst
> > 
> > Sent from my iPhone
> > 
> > On Mar 6, 2012, at 2:49 PM, Rob Scott 
>  wrote:
> > 
> >>> You have coded "LAE   R3,0(R4)" - which is the same as 
> "LAE   R3,(R4,R0)"
> >> 
> >> Should read :
> >> 
> >> You have coded "LAE   R3,0(R4)" - which is the same as 
> "LAE   R3,0(R4,R0)"
> >> 
> >> Rob Scott
> >> Lead Developer
> >> Rocket Software
> >> 275 Grove Street * Newton, MA 02466-2272 * USA
> >> Tel: +1.781.684.2305
> >> Email: rsc...@rs.com
> >> Web: www.rocketsoftware.com
> >> 
> >> 
> >> -Original Message-
> >> From: IBM Mainframe Discussion List 
> [mailto:IBM-MAIN@bama.ua.edu] On 
> >> Behalf Of Rob Scott
> >> Sent: 06 March 2012 19:47
> >> To: IBM-MAIN@bama.ua.edu
> >> Subject: Re: LAE instruction

Re: LAE instruction

[Micheal Butz]

Sorry misspelled the name John McKown. Excuse me

Sent from my iPhone

On Mar 6, 2012, at 4:00 PM, Micheal Butz  wrote:

> John Mckiwns reply was a explanation of the SAC inst.Which I am aware of
> 
> The Doc for LAE says the inst the functionality is dependent on PSW bits
> 
> 16 17 address space control bits these are set by the SAC inst
> 
> 
> So my original question remains does
> 
> Should address space control buts be set via the sac before executing the LAE 
> 
> 
> Sent from my iPhone
> 
> On Mar 6, 2012, at 3:37 PM, Rob Scott  wrote:
> 
>> John McKown's reply covered these points very well
>> 
>> Rob Scott
>> Lead Developer
>> Rocket Software
>> 275 Grove Street * Newton, MA 02466-2272 * USA
>> Tel: +1.781.684.2305
>> Email: rsc...@rs.com
>> Web: www.rocketsoftware.com
>> 
>> 
>> -Original Message-
>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
>> Of Micheal Butz
>> Sent: 06 March 2012 19:59
>> To: IBM-MAIN@bama.ua.edu
>> Subject: Re: LAE instruction
>> 
>> Thanks
>> 
>> Regarding my questions
>> 
>> The doc says the inst is dependent
>> On address space control bits which is set by the SAC inst. 
>> 
>> Secondly seems like the displacement doesn't play a role in the inst
>> 
>> Sent from my iPhone
>> 
>> On Mar 6, 2012, at 2:49 PM, Rob Scott  wrote:
>> 
>>>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,(R4,R0)"
>>> 
>>> Should read :
>>> 
>>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,0(R4,R0)"
>>> 
>>> Rob Scott
>>> Lead Developer
>>> Rocket Software
>>> 275 Grove Street * Newton, MA 02466-2272 * USA
>>> Tel: +1.781.684.2305
>>> Email: rsc...@rs.com
>>> Web: www.rocketsoftware.com
>>> 
>>> 
>>> -Original Message-
>>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On 
>>> Behalf Of Rob Scott
>>> Sent: 06 March 2012 19:47
>>> To: IBM-MAIN@bama.ua.edu
>>> Subject: Re: LAE instruction
>>> 
>>> Commas are *very* important in AR-mode
>>> 
>>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,(R4,R0)"
>>> 
>>> Coded that way there is no automatic way that AR3 is going to inherit the 
>>> AR4 value.
>>> 
>>> You need : "LAE   R3,0(,R4)"
>>> 
>>> This will ensure that AR3 is populated from the AR for the referenced base 
>>> register R4.
>>> 
>>> 
>>> Rob Scott
>>> Lead Developer
>>> Rocket Software
>>> 275 Grove Street * Newton, MA 02466-2272 * USA
>>> Tel: +1.781.684.2305
>>> Email: rsc...@rs.com
>>> Web: www.rocketsoftware.com
>>> 
>>> 
>>> -Original Message-
>>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On 
>>> Behalf Of Micheal Butz
>>> Sent: 06 March 2012 19:05
>>> To: IBM-MAIN@bama.ua.edu
>>> Subject: LAE instruction
>>> 
>>> Hi,
>>> 
>>> 
>>> 
>>> I have two part question regarding the LAE instruction
>>> 
>>> 
>>> 
>>> . What would the sac value e.g. 256,512,768 have to be that when
>>> using the LAE instructions with the following operands LAE  3,0(R4) 
>>> would
>>> AR3 get loaded with AR4
>>> 
>>> 
>>> 
>>> . Second what value does the displacement play in the instruction
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>> 
>>>   Thanks 
>>> 
>>> 
>>> --
>>> For IBM-MAIN subscribe / signoff / archive access instructions, send 
>>> email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
>>> 
>>> --
>>> For IBM-MAIN subscribe / signoff / archive access instructions, send 
>>> email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
>>> 
>>> --
>>> For IBM-MAIN subscribe / signoff / archive access instructions, send 
>>> email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
>> 
>> --
>> For IBM-MAIN subscribe / signoff / archive access instructions, send email 
>> to lists...@bama.ua.edu with the message: INFO IBM-MAIN
>> 
>> --
>> For IBM-MAIN subscribe / signoff / archive access instructions,
>> send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
> 
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

Re: LAE instruction

[Micheal Butz]

John Mckiwns reply was a explanation of the SAC inst.Which I am aware of

The Doc for LAE says the inst the functionality is dependent on PSW bits

16 17 address space control bits these are set by the SAC inst


So my original question remains does

Should address space control buts be set via the sac before executing the LAE 


Sent from my iPhone

On Mar 6, 2012, at 3:37 PM, Rob Scott  wrote:

> John McKown's reply covered these points very well
> 
> Rob Scott
> Lead Developer
> Rocket Software
> 275 Grove Street * Newton, MA 02466-2272 * USA
> Tel: +1.781.684.2305
> Email: rsc...@rs.com
> Web: www.rocketsoftware.com
> 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of Micheal Butz
> Sent: 06 March 2012 19:59
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: LAE instruction
> 
> Thanks
> 
> Regarding my questions
> 
> The doc says the inst is dependent
> On address space control bits which is set by the SAC inst. 
> 
> Secondly seems like the displacement doesn't play a role in the inst
> 
> Sent from my iPhone
> 
> On Mar 6, 2012, at 2:49 PM, Rob Scott  wrote:
> 
>>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,(R4,R0)"
>> 
>> Should read :
>> 
>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,0(R4,R0)"
>> 
>> Rob Scott
>> Lead Developer
>> Rocket Software
>> 275 Grove Street * Newton, MA 02466-2272 * USA
>> Tel: +1.781.684.2305
>> Email: rsc...@rs.com
>> Web: www.rocketsoftware.com
>> 
>> 
>> -Original Message-
>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On 
>> Behalf Of Rob Scott
>> Sent: 06 March 2012 19:47
>> To: IBM-MAIN@bama.ua.edu
>> Subject: Re: LAE instruction
>> 
>> Commas are *very* important in AR-mode
>> 
>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,(R4,R0)"
>> 
>> Coded that way there is no automatic way that AR3 is going to inherit the 
>> AR4 value.
>> 
>> You need : "LAE   R3,0(,R4)"
>> 
>> This will ensure that AR3 is populated from the AR for the referenced base 
>> register R4.
>> 
>> 
>> Rob Scott
>> Lead Developer
>> Rocket Software
>> 275 Grove Street * Newton, MA 02466-2272 * USA
>> Tel: +1.781.684.2305
>> Email: rsc...@rs.com
>> Web: www.rocketsoftware.com
>> 
>> 
>> -Original Message-
>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On 
>> Behalf Of Micheal Butz
>> Sent: 06 March 2012 19:05
>> To: IBM-MAIN@bama.ua.edu
>> Subject: LAE instruction
>> 
>> Hi,
>> 
>> 
>> 
>> I have two part question regarding the LAE instruction
>> 
>> 
>> 
>> . What would the sac value e.g. 256,512,768 have to be that when
>> using the LAE instructions with the following operands LAE  3,0(R4) 
>> would
>> AR3 get loaded with AR4
>> 
>> 
>> 
>> . Second what value does the displacement play in the instruction
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>>Thanks 
>> 
>> 
>> --
>> For IBM-MAIN subscribe / signoff / archive access instructions, send 
>> email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
>> 
>> --
>> For IBM-MAIN subscribe / signoff / archive access instructions, send 
>> email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
>> 
>> --
>> For IBM-MAIN subscribe / signoff / archive access instructions, send 
>> email to lists...@bama.ua.edu with the message: INFO IBM-MAIN
> 
> --
> For IBM-MAIN subscribe / signoff / archive access instructions, send email to 
> lists...@bama.ua.edu with the message: INFO IBM-MAIN
> 
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

--
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

Re: LAE instruction

[Micheal Butz]

Thanks
 
Regarding my questions

The doc says the inst is dependent
On address space control bits which is set by the SAC inst. 

Secondly seems like the displacement doesn't play a role in the inst

Sent from my iPhone

On Mar 6, 2012, at 2:49 PM, Rob Scott  wrote:

>> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,(R4,R0)"
> 
> Should read :
> 
> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,0(R4,R0)"
> 
> Rob Scott
> Lead Developer
> Rocket Software
> 275 Grove Street * Newton, MA 02466-2272 * USA
> Tel: +1.781.684.2305
> Email: rsc...@rs.com
> Web: www.rocketsoftware.com
> 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of Rob Scott
> Sent: 06 March 2012 19:47
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: LAE instruction
> 
> Commas are *very* important in AR-mode
> 
> You have coded "LAE   R3,0(R4)" - which is the same as "LAE   R3,(R4,R0)"
> 
> Coded that way there is no automatic way that AR3 is going to inherit the AR4 
> value.
> 
> You need : "LAE   R3,0(,R4)"
> 
> This will ensure that AR3 is populated from the AR for the referenced base 
> register R4.
> 
> 
> Rob Scott
> Lead Developer
> Rocket Software
> 275 Grove Street * Newton, MA 02466-2272 * USA
> Tel: +1.781.684.2305
> Email: rsc...@rs.com
> Web: www.rocketsoftware.com
> 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of Micheal Butz
> Sent: 06 March 2012 19:05
> To: IBM-MAIN@bama.ua.edu
> Subject: LAE instruction
> 
> Hi,
> 
> 
> 
> I have two part question regarding the LAE instruction 
> 
> 
> 
> . What would the sac value e.g. 256,512,768 have to be that when
> using the LAE instructions with the following operands LAE  3,0(R4) would
> AR3 get loaded with AR4 
> 
> 
> 
> . Second what value does the displacement play in the instruction
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Thanks 
> 
> 
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LAE instruction

[Micheal Butz]

Hi,

 

I have two part question regarding the LAE instruction 



. What would the sac value e.g. 256,512,768 have to be that when
using the LAE instructions with the following operands LAE  3,0(R4) would
AR3 get loaded with AR4 

 

. Second what value does the displacement play in the instruction

 

 

 

 

 

 Thanks 


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Re: Return code = X'14' from ATTACH JSTCB=YES

[Micheal Butz]

I ran it as command processor TESTAUTH ' ' CP
And it worked 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: Sunday, March 04, 2012 5:00 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Return code = X'14' from ATTACH JSTCB=YES

Sorry was running under TESTAUTH SO EXEC PGM=IKJEF

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Sunday, March 04, 2012 4:56 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Return code = X'14' from ATTACH JSTCB=YES

On Sun, 4 Mar 2012 16:31:44 -0500 Micheal Butz 
wrote:

:>Hi,
:>
:> 
:>
:>I got a return code of X'15' from ATTACH JSTCB=YES
:>
:> 
:>
:> 
:>
:> 
:>
:>
:>14  
:> 
:> 
:> 
:> 
:> 
:> 
:>
:> Meaning: Program error. An authorized task that  
:> specified JSTCB=YES is not a job step task.  
:> Processing not completed.
  
:> Action: Either remove the JSTCB=YES option from this 
:> ATTACH macro or specify JSTCB=YES on the ATTACH  
:> macro for the current task. 

:>Does this mean that only the initiator can issue a ATTACH JSTCB=YES

Nope. The program receiving control via EXEC PGM= is also a job step task.

--
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Re: Return code = X'14' from ATTACH JSTCB=YES

[Micheal Butz]

Sorry was running under TESTAUTH SO EXEC PGM=IKJEF

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Sunday, March 04, 2012 4:56 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Return code = X'14' from ATTACH JSTCB=YES

On Sun, 4 Mar 2012 16:31:44 -0500 Micheal Butz 
wrote:

:>Hi,
:>
:> 
:>
:>I got a return code of X'15' from ATTACH JSTCB=YES
:>
:> 
:>
:> 
:>
:> 
:>
:>
:>14  
:> 
:> 
:> 
:> 
:> 
:> 
:>
:> Meaning: Program error. An authorized task that  
:> specified JSTCB=YES is not a job step task.  
:> Processing not completed.
  
:> Action: Either remove the JSTCB=YES option from this 
:> ATTACH macro or specify JSTCB=YES on the ATTACH  
:> macro for the current task. 

:>Does this mean that only the initiator can issue a ATTACH JSTCB=YES

Nope. The program receiving control via EXEC PGM= is also a job step task.

--
Binyamin Dissen 
http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


Should you use the mailblocks package and expect a response from me,
you should preauthorize the dissensoftware.com domain.

I very rarely bother responding to challenge/response systems,
especially those from irresponsible companies.

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Return code = X'14' from ATTACH JSTCB=YES

[Micheal Butz]

Hi,

 

I got a return code of X'15' from ATTACH JSTCB=YES

 

 

 


14  
 
 
 
 
 
 

 Meaning: Program error. An authorized task that  
 specified JSTCB=YES is not a job step task.  
 Processing not completed.
  
 Action: Either remove the JSTCB=YES option from this 
 ATTACH macro or specify JSTCB=YES on the ATTACH  
 macro for the current task. 

 

 

Does this mean that only the initiator can issue a ATTACH JSTCB=YES


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Re: Linkage tables

[Micheal Butz]

Got it

Sent from my iPhone

On Mar 4, 2012, at 1:47 PM, Ray Overby  wrote:

> Assuming this data is produced by a "summary format" in IPCS I believe the LX 
> is 2B and the EX is 00.
> 
> On 3/4/2012 11:46 AM, Micheal Butz wrote:
>> PC
>>   NUMBER
>>  
>>  2B00  The Following PC number is for LX or linkage index 0 as The
>> high order 0's signify
>> 
>> -Original Message-
>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
>> Of Peter Relson
>> Sent: Sunday, March 04, 2012 8:32 AM
>> To: IBM-MAIN@bama.ua.edu
>> Subject: Re: Linkage tables
>> 
>>> Does anyone know how to display the linkage tables
>> >from an IPCS dump assuming I dump PCAUTH address space
>> 
>> Summary Format will display a lot of information.
>> 
>> If you literally want to display the linkage tables (both linkage first
>> and linkage second if the ASN-and-LX-reuse facility is active), then
>> follow the real-pointer chains described in the Principles of Operation,
>> starting from the ASTE (the virtual address of the linkage table / linkage
>> first table is in ASCBLTOV)
>> 
>> Peter Relson
>> z/OS Core Technology Design
>> 
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IPCS VSMDATA

[Micheal Butz]

Hi,

 

I am trying to track some storage allocation thru IPCS using VSMDATA 

 

 

There are four  data areas described by VSMDATA DQE (descriptor Queue
element) FQE (free queue element)

 

SPQE (subpool queue element) SPQA (subpool queue anchors)

 

 

The DQE  describes storage allocated from a 1K page FROM (? What subpool)
and (? What TCB)

 

The FQE (free queue element) size (remaining size from 1k )

 

 

The SPQE What TCB owns the subpool 

 

The SPQE points to the SPQA which points DQE for storage allocated 

 

 

Is there an easier way of determining what storage has been allocated and
not freed by a TCB

 

 

Thanks 


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Re: Linkage tables

[Micheal Butz]

PC
  NUMBER  
  
 2B00  The Following PC number is for LX or linkage index 0 as The
high order 0's signify

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Peter Relson
Sent: Sunday, March 04, 2012 8:32 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Linkage tables

>Does anyone know how to display the linkage tables 
>from an IPCS dump assuming I dump PCAUTH address space

Summary Format will display a lot of information.

If you literally want to display the linkage tables (both linkage first 
and linkage second if the ASN-and-LX-reuse facility is active), then 
follow the real-pointer chains described in the Principles of Operation, 
starting from the ASTE (the virtual address of the linkage table / linkage 
first table is in ASCBLTOV)

Peter Relson
z/OS Core Technology Design

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Linkage tables

[Micheal Butz]

Hi


Does anyone know how to display the linkage tables from an IPCS dump assuming I 
dump PCAUTH address space

Sent from my iPhone

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Re: TCBTQE

[Micheal Butz]

Are these created by Z/OS or by the user or both

Sent from my iPhone

On Feb 26, 2012, at 3:50 PM, Edward Jaffe  wrote:

> On 2/26/2012 12:04 PM, Micheal Butz wrote:
>> Does  the TCBTQE contain the TQE (time slice for that task to run)
> 
> TCBTQE points to the chain of TQEs mapped by IHATQE. You can create TQEs 
> using  STIMER or STIMERM.
> 
> -- 
> Edward E Jaffe
> Phoenix Software International, Inc
> 831 Parkview Drive North
> El Segundo, CA 90245
> 310-338-0400 x318
> edja...@phoenixsoftware.com
> http://www.phoenixsoftware.com/
> 
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TCBTQE

[Micheal Butz]

Hi,

 

Does  the TCBTQE contain the TQE (time slice for that task to run)

 

  


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Re: DU-AL in IPCS dump

[Micheal Butz]

Can you please elaborate is this  a parameter on VERBEXIT SUMDUMP 

 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Friday, February 24, 2012 7:33 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: DU-AL in IPCS dump

CR2 -> DUCT

On Thu, 23 Feb 2012 20:35:52 -0500 Micheal Butz 
wrote:

:>In a ipcs dump where can I see a TCBs. DU-AL
:>
:>Sent from my iPhone
:>
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http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


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you should preauthorize the dissensoftware.com domain.

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DU-AL in IPCS dump

[Micheal Butz]

In a ipcs dump where can I see a TCBs. DU-AL

Sent from my iPhone

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Princeple of operations link with Grande instructions

[Micheal Butz]

Hi,

 

Would anyone have a link to POP's book/PDF with 64 bit instructions

 

 

 

thanks

 


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Re: Difference between DREF storage and Page fixed storage

[Micheal Butz]

AH now I understand EXCP ... CCW   the data address portion of the CCW
nothing to do with DFSMS

   
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Edward Jaffe
Sent: Wednesday, February 22, 2012 9:59 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Difference between DREF storage and Page fixed storage

On 2/22/2012 12:51 AM, Micheal Butz wrote:
> Please explain I/O should not be done to DREF using "DREF storage as
buffer
> area for I/O"

Anything referenced by the I/O channel program should be fixed.

-- 
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Phoenix Software International, Inc
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El Segundo, CA 90245
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edja...@phoenixsoftware.com
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Re: Difference between DREF storage and Page fixed storage

[Micheal Butz]

Normally when getting storage "OBTAIN" the default is subpool 0 which
pageable

GET DCB_ADDRESS,AREA_ADDRESS almost always AREA_ADDRESS is from subpool 0 ?


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Bill Fairchild
Sent: Wednesday, February 22, 2012 10:19 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Difference between DREF storage and Page fixed storage

I/O should not be done directly to or from any page whose real page backing
the virtual page is not fixed.  If the real-to-virtual relationship is not
guaranteed to last as long as the I/O operation runs, then an I/O request
may start writing data out from the page, before the I/O finishes the
operating system may change the real address backing the virtual page, and
the data that is being written out will continue being written out from the
original real page which may or may not be assigned to any virtual page at
that instant.  Nothing will crash as a result, but the data written out is
almost certainly partly wrong, and it might be used to compromise the
system's or user's data security.

If, however, you do a read I/O into a virtual page whose real address
changes while the I/O is in flight, then the real address that was formerly
used for the virtual page may or may not be assigned immediately to another
page.  If it is, then some randomly chosen other user will have one of his
pages hosed.  If it is hosed before that other user alters the page or
before the operating system zeroes out the page (if this is necessary), then
nothing bad will happen to that other user.  But If the other user starts
making use of that page while the I/O is still running, then the results are
unpredictable and almost certainly really bad for that user.  If it is not
assigned to another user for a long time, then nothing will be hosed, but
the user who did the read I/O will not be able to find some of the data that
was read.

In general, either of the above scenarios is double plus ungood.

Depending on how the IXG macro works and on exactly what the doc said, it
may be that the following is true:  you code the IXG macro and point it to
some DREF storage to use "as a buffer"; the IXG macro transfers control to a
module that knows how to do I/O properly; this module acquires a small piece
of FIXED storage for whatever I/O operation is necessary to find the member
name; the module does the I/O, then copies the member name from the FIXED
I/O buffer into the DREF page you told IXG to use; then the module frees up
the FIXED storage it used behind the curtains before returning control to
your program.  The member name is now (Voila!) in the DREF storage, the I/O
worked correctly, and nobody's storage has been hosed.

Or it may be a doc error.  Or it may be that no I/O is really necessary for
the IXG service to find the member name.  In any case, if the IXG service
does I/O directly to a DREF page, then this is an APARable error.

I suggest you re-read the macro's doc very carefully, and then use FIXED
storage unless the doc clearly explains why DREF will work.

Bill Fairchild

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: Wednesday, February 22, 2012 2:52 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Difference between DREF storage and Page fixed storage

Please explain I/O should not be done to DREF using "DREF storage as buffer
area for I/O"


When I used sysplex IXG macros to obtain member information the doc said use
DREF storage -Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Edward Jaffe
Sent: Wednesday, February 22, 2012 2:46 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Difference between DREF storage and Page fixed storage

On 2/21/2012 10:47 PM, Jim Mulder wrote:
>   The operating system reserves the right to exchange the frame 
> backing any DREF page (LSQA or SQA) at any time.

Which is why I/O should not be done to DREF storage, only to fixed storage.

--
Edward E Jaffe
Phoenix Software International, Inc
831 Parkview Drive North
El Segundo, CA 90245
310-338-0400 x318
edja...@phoenixsoftware.com
http://www.phoenixsoftware.com/

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Re: Difference between DREF storage and Page fixed storage

[Micheal Butz]

Please explain I/O should not be done to DREF using "DREF storage as buffer
area for I/O"


When I used sysplex IXG macros to obtain member information the doc said use
DREF storage  
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Edward Jaffe
Sent: Wednesday, February 22, 2012 2:46 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Difference between DREF storage and Page fixed storage

On 2/21/2012 10:47 PM, Jim Mulder wrote:
>   The operating system reserves the right to exchange the frame backing
> any DREF page (LSQA or SQA) at any time.

Which is why I/O should not be done to DREF storage, only to fixed storage.

-- 
Edward E Jaffe
Phoenix Software International, Inc
831 Parkview Drive North
El Segundo, CA 90245
310-338-0400 x318
edja...@phoenixsoftware.com
http://www.phoenixsoftware.com/

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Re: ACCESS=PUBLIC on ALESERV macro

[Micheal Butz]

Okay ... Just wanted to understand the concept

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Chris Craddock
Sent: Tuesday, February 21, 2012 4:24 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: ACCESS=PUBLIC on ALESERV macro

On Tue, Feb 21, 2012 at 2:15 PM, Micheal Butz
wrote:

> If I adding the STOKEN of another address to either my DU-AL PASN-AL can I
> specify PUBLIC on the ALESERV macro and bypass the authorization)
>
> Typically when I get the alet of another address I do a AXSET to give
> myself
> authorization to go there
>
>Would adding PUBLIC entry for the ALET of another address space via
> ALESERV bypass the need to do a AXSET
>


No and no. Just don't do it. Adding addressability to another address space
this way is not really supported outside of BCP components - even though
the macro documentation might seem to suggest otherwise. Consider it a wild
hare that escaped. The supported approaches are documented in the extended
addressability guide.


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Difference between DREF storage and Page fixed storage

[Micheal Butz]

Hi,

 

Would any know the difference between (disabled reference storage) DREF e.g.
subpool 215 and Page fixed storage e.g. subpool 223

>From what I understand DREF means the program is running disable for
interrupts and thus no pagIing should occur so the doc say use DREF storage

While fixed storage means storage is fixed and the same thing applies no
paging should occur

 

 

thanks   


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ACCESS=PUBLIC on ALESERV macro

[Micheal Butz]

Hi,

 

If I adding the STOKEN of another address to either my DU-AL PASN-AL can I
specify PUBLIC on the ALESERV macro and bypass the authorization) 

Typically when I get the alet of another address I do a AXSET to give myself
authorization to go there

 

  Would adding PUBLIC entry for the ALET of another address space via
ALESERV bypass the need to do a AXSET

 

 


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Entry point on attach

[Micheal Butz]

Hi

Again if I do a attach with disp=no
And r1 has the tcb address I can look at the TCBRBP or relating CDE for the 
loadpoint of the module

Sent from my iPhone

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Program entry point on Attached program

[Micheal Butz]

Hi,

 

I know that if a program is re-entrant a subsequent ATTACH will use that
address as the entry point.

 

How about a non-reentrant program

 

 

If I do a ATTACH DISP=NO is the attached program LOADED and if so is there a
way to find the entry point

 

 


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EXTRACT FIELDS=COMM for subtasks

[Micheal Butz]

Hi,

 

I know EXTRACT FIELDS=COMM (using the ECB) for stop or modify command works
for the TCB your running dunning the course of my programming

I attach 4 other subtasks is there any parameter on the ATTACH e.g. like
ALCOPY( work for access lists) where I can share COMECBPT among subtasks

 

thanks   


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Assembler list

[Micheal Butz]

Hi,

 

Would anyone know how to subscribe to the assembler list 

 

 

 

 Thanks


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Re: Cics Global User Exit

[Micheal Butz]

Can they have CICS API so that I can trace thru it with CEDF

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Barkow, Eileen
Sent: Monday, January 09, 2012 3:59 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Cics Global User Exit

no

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: Monday, January 09, 2012 3:52 PM
To: IBM-MAIN@bama.ua.edu
Subject: Cics Global User Exit

Do CICS Global User exits have to be loaded In CSA


Sent from my iPhone

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Cics Global User Exit

[Micheal Butz]

Do CICS Global User exits have to be loaded In CSA


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CICS Global exit XEIIN

[Micheal Butz]

Hi,

 

I have assembled and enabled CICS exit XEIIN It is my understanding that it
should get invoked whenever a CICS api is encountered

 

However this doesn't seem to be the case if anyone could shed some light on
this I would appreciate it

 

 

 

thsnks


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Re: Debugging CICS Global User Exits

[Micheal Butz]

Yes Are Global Exits loaded in CSA

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Edward Jaffe
Sent: Sunday, January 08, 2012 1:21 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Debugging CICS Global User Exits

On 1/7/2012 8:12 PM, Micheal Butz wrote:
> Hi,
>
>   Would anyone know the best method to debug CICS Global User Exits For
MVS I
> usually used XDC

z/XDC?

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Debugging CICS Global User Exits

[Micheal Butz]

Hi,

 

 

 Would anyone know the best method to debug CICS Global User Exits For MVS I
usually used XDC 

 

 

 


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Re: Control Blocks Generated By Attach

[Micheal Butz]

Only one CDE 

The TCB is just a control block that keeps track of ownership of resources
storage,  modules loaded, in the case of DB2 which DB2 SSID is associated
with task
Also generated with a certain storage key TCBPKF as to what storage key it
can access of course this can be changed by modeset

Just wondering if I got it right


thanks 


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Sunday, January 01, 2012 3:21 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Control Blocks Generated By Attach

On Sun, 1 Jan 2012 15:09:01 -0500 Micheal Butz 
wrote:

:>If I do 4 attaches to the same program then there will be only one copy of
:>the program 

If RENT.

:>But each TCB will have its own set of RB's indicating where each  task is
to
:>resume processing

Yes.

In fact, ATTACH terminates before the module is loaded. The LOAD is done by
the new task. 

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Control Blocks Generated By Attach

[Micheal Butz]

Hi,

 

 

If I do 4 attaches to the same program then there will be only one copy of
the program 

 

But each TCB will have its own set of RB's indicating where each  task is to
resume processing

 

 


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Re: register Values TCBGRS vs TCBRB->XRBREGS

[Micheal Butz]

FIRST dispatched but later on is the RB constantly updated

Sent from my iPhone

On Dec 22, 2011, at 3:59 PM, "Shmuel Metz (Seymour J.)" 
 wrote:

> In , on 12/22/2011
>   at 08:30 AM, Micheal Butz  said:
> 
>> How about when the TCBs CPU time slice is up and control Is given up
>> to a different task
> 
> TCBGRS. The register fields in an RB generally represent the registers
> at the time the RB was created or first dispatched. YMMV.
> 
> -- 
> Shmuel (Seymour J.) Metz, SysProg and JOAT
> ISO position; see <http://patriot.net/~shmuel/resume/brief.html> 
> We don't care. We don't have to care, we're Congress.
> (S877: The Shut up and Eat Your spam act of 2003)
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Re: register Values TCBGRS vs TCBRB->XRBREGS

[Micheal Butz]

How about when the TCBs CPU time slice is up and control
Is given up to a different task


Thanks


Sent from my iPhone

On Dec 22, 2011, at 8:16 AM, Peter Relson  wrote:

>> Would anyone know what the differences at a point in time between the
>> values in TCBGRS and The Values of the registers in XRBREGS of the RB
>> pointed  to by TCBRB
> 
> As with may things, the answer is "is depends". For example, it depends on 
> what "point in time"  and what kind of RB is involved.
> 
> I think of it this way,  for an SVC:
> -- The front end of the SVC FLIH saves intoTCBGRS.
> -- If an SVRB is created, then the regs are copied into the RB/XSB.
> -- If no RB is created (type 1 SVC), then no copying is done.
> 
> If you are looking while the SVC is in control, you might have a different 
> answer than if you are looking after the SVC has returned.
> 
> And then of course external and I/O interrupts can come into play.
> 
> Peter Relson
> z/OS Core Technology Design
> 
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register Values TCBGRS vs TCBRB->XRBREGS

[Micheal Butz]

Hi,

 

 

 Would anyone know what the differences at a point in time between the
values in TCBGRS and The Values of the registers in XRBREGS of the RB
pointed  to by TCBRB



 I am assuming of course TCBRB is the currently executing RB

 

 

THANKS 


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Testing g RTM routine

[Micheal Butz]

Hi,

 

Would anyone know how to test the RTM routine of a SRB when I issue a
schedule even though SRB activity is asynchronous it takes off automatically

 

 

   


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Re: SRBEPA

[Micheal Butz]

Sp 226

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Peter Relson
Sent: Sunday, October 23, 2011 10:06 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA

>There is not much of a real difference. SQA will even overflow into CSA. 
It is a matter of "definition". Also the manual says to use SQA. In 
addition, SQA is >automatically page-fixed. I don't know why you'd want 
executable code in [E]SQA vice [E]CSA.

>http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/iea2a890/6.3.4

The thread is primarily about the SRB routine. The reference is about the 
SRB itself. The SRB must be in (E)SQA; it must not be in (E)CSA.

>So for the SRB control block 241,
No, never.

Peter Relson
z/OS Core Technology Design

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Re: z/OS Control block question

[Micheal Butz]

Cann't a Authorized program do a ATTACH JSTCB=YES 

anytime  


-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Wayne Driscoll
Sent: Saturday, October 22, 2011 8:29 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: z/OS Control block question

Please explain how "all TCB's under a given JSTCB will point to the same 
TIOT" is incorrect, but "every TCB with the same TCBJSTCB will normally 
have the same TIOT" is true, when the two statements make the same point? 

===
Wayne Driscoll
OMEGAMON DB2 L3 Support/Development
wdrisco(AT)us.ibm.com
===



From:
"Shmuel Metz (Seymour J.)" 
To:
IBM-MAIN@bama.ua.edu
Date:
10/22/2011 06:28 PM
Subject:
Re: z/OS Control block question
Sent by:
IBM Mainframe Discussion List 



In
,
on 10/20/2011
   at 10:05 AM, Wayne Driscoll  said:

>but all TCB's under a given JSTCB will point to the same TIOT.

Actually not. There will generally be more than one JSTCB. What is
true is that every TCB with the same TCBJSTCB will normally[1] have
the same TIOT.

[1] I'm not aware of any exceptions.
 
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Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

[Micheal Butz]

Is all that's required for setting a recovery routine for the SRB is setting
a address in SRBFRRA ? 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Tom Harper
Sent: Tuesday, October 18, 2011 8:48 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH

Michael,

It sounds like you are issuing the SETFRR under your TCB which is going to
SCHEDULE your SRB. This is not necessary and will almost certainly cause you
problems, such as the 0F8 abend, and this FRR will not protect your SRB.

FRR's can be used to establish a recovery environment for a TCB, but I don't
think you really need one here. If you do need such an environment, I would
use an ESTAEX.

You can choose to use an FRR with your SRB, or, you can just let it
percolate back to your TCB, as Chris mentioned. If you do want an FRR for
your SRB, you can just set its address in the SRBFRRA field or you can issue
your own SETFRR rearly in the SRB code. I would also suggest issuing an
SRBTIMER macro to catch any loops you might have.

Like the Binjamin and Chris, I wonder what you're trying to accomplish here.
It sounds like this is your first foray into this sort of coding, but it
also appears that you haven't read all of the background material in the
z/OS Authorized Programming Guide, which I suggest you should do. In there
are the answers to all of the questions you've been asking here.

If you are determined to push ahead, I'm hoping you are testing on a sandbox
system. 

Please be more communicative with your objectives here.

Tom

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Tuesday, October 18, 2011 3:10 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH

On Tue, 18 Oct 2011 00:26:08 -0400 Micheal Butz 
wrote:

:>I am trying to issue a branch entry form of  a macro in a other address
:>space since the specifications say PASN=HASN=SASN

Which macro?

:>SRB was the only way to go, the branch entry form of the macro was the
only :>code in the SRB I figured I would set up a FRR 

:>So that if anything goes wrong RTM would give control to the FRR I could
:>examine the SDWA for any problems

Have you done FRR's before? ESTAEs? If not, you might be biting off more
than you can chew with testing a FRR and SRB's at the same time.

Under which conditions will you recover?

You might want to set it up so that the SRB will abend your issuing task. 

Also, I don't get the connection between what you are doing and a
non-reentrent TSO command.

Try to give details on WHAT you are trying to accomplish - not how you are
trying to do it.

:>-Original Message-
:>From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On
Behalf :>Of Chris Craddock
:>Sent: Tuesday, October 18, 2011 12:05 AM
:>To: IBM-MAIN@bama.ua.edu
:>Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH :>
:>No, you werent where you thought you were in the code. The system doesn't
:>lie about what happened.  You can't issue any SVC instructions while you
:>have an FRR on the stack, regardless of what kind of FRR you have. And
don't :>forget you may be calling other system services whether you're aware
of it :>or not. 
:>
:>Leaving aside the general undesirability of testing SRB code  by trial and
:>error, If you did manage to get the SRB scheduled then two interesting
:>things are happening to you. First you have another independent unit of
work :>running (the SRB) which will muddy the waters because any error that
befalls :>the SRB will be reflected back on the TCB you're running under so
your :>debugging information is going to be quite confusing. 
:>
:>Frankly you're kind of stumbling around in a coal mine with a flashlight
:>even trying this. I would usually give a little sermon about all the
things :>that can go horribly wrong. I will spare you that but here's the
rub -- :>there's not a lot of chance you're going to suddenly converge on a
solution :>that works. Tell us what problem you're trying to solve and maybe
we can :>help you without trashing your system. 
:>
:>Sent from my iPad
:>
:>On Oct 17, 2011, at 10:07 PM, Micheal Butz 
:>wrote:
:>
:>> I didn't issue any SVC
:>>
:>> The code blew up under TESTAUTH at the fifth instruction after the :>>
expansion of the SETFRR macro :>> :>> I normally get 0F8 when I am in XMEM
mode and issue a SVC I didn't abended
:>> on a SVC I abended whitin STM of the SETFRR inst
:>>
:>> -Original Message-
:>> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On
:>Behalf :>> Of Li

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

[Micheal Butz]

I am trying to issue a branch entry form of  a macro in a other address
space since the specifications say PASN=HASN=SASN

SRB was the only way to go, the branch entry form of the macro was the only
code in the SRB I figured I would set up a FRR 

So that if anything goes wrong RTM would give control to the FRR I could
examine the SDWA for any problems

 

   

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Chris Craddock
Sent: Tuesday, October 18, 2011 12:05 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH

No, you werent where you thought you were in the code. The system doesn't
lie about what happened.  You can't issue any SVC instructions while you
have an FRR on the stack, regardless of what kind of FRR you have. And don't
forget you may be calling other system services whether you're aware of it
or not. 

Leaving aside the general undesirability of testing SRB code  by trial and
error, If you did manage to get the SRB scheduled then two interesting
things are happening to you. First you have another independent unit of work
running (the SRB) which will muddy the waters because any error that befalls
the SRB will be reflected back on the TCB you're running under so your
debugging information is going to be quite confusing. 

Frankly you're kind of stumbling around in a coal mine with a flashlight
even trying this. I would usually give a little sermon about all the things
that can go horribly wrong. I will spare you that but here's the rub --
there's not a lot of chance you're going to suddenly converge on a solution
that works. Tell us what problem you're trying to solve and maybe we can
help you without trashing your system. 

Sent from my iPad

On Oct 17, 2011, at 10:07 PM, Micheal Butz 
wrote:

> I didn't issue any SVC 
> 
> The code blew up under TESTAUTH at the fifth instruction after the
> expansion of the SETFRR macro
> 
> I normally get 0F8 when I am in XMEM mode and issue a SVC I didn't abended
> on a SVC I abended whitin STM of the SETFRR inst
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On
Behalf
> Of Lizette Koehler
> Sent: Monday, October 17, 2011 10:54 PM
> To: IBM-MAIN@bama.ua.edu
> Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH
> 
>> Hi,
>> 
>> 
>> 
>> I am trying to establish a FRR in a TSO command processor program that is
> not re-
>> entrant this is because
> 
>> 
>> Later I schedule a SRB and I want to use the routine I established as a
> FRR, as  input
>> to the SRBFRRA parameter
>> 
> 
> Did you review the abend and code?
> S0F8 - 14 - THE SVC ISSUER HAD AN ENABLED UNLOCKED TASK MODE FRR.   
>IE. EUT=YES WAS SPECIFIED ON THE SETFRR MACRO.
> 
> Did it help?
> 
> Are you a member of the assembler language newsgroup?  You might have
better
> response there or better assistance.   assembler-l...@listserv.uga.edu

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Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

[Micheal Butz]

I didn't issue any SVC 

 The code blew up under TESTAUTH at the fifth instruction after the
expansion of the SETFRR macro

I normally get 0F8 when I am in XMEM mode and issue a SVC I didn't abended
on a SVC I abended whitin STM of the SETFRR inst

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Lizette Koehler
Sent: Monday, October 17, 2011 10:54 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH

> Hi,
> 
> 
> 
> I am trying to establish a FRR in a TSO command processor program that is
not re-
> entrant this is because

> 
> Later I schedule a SRB and I want to use the routine I established as a
FRR, as  input
> to the SRBFRRA parameter
>  

Did you review the abend and code?
S0F8 - 14 - THE SVC ISSUER HAD AN ENABLED UNLOCKED TASK MODE FRR.   
IE. EUT=YES WAS SPECIFIED ON THE SETFRR MACRO.

Did it help?

Are you a member of the assembler language newsgroup?  You might have better
response there or better assistance.   assembler-l...@listserv.uga.edu



Lizette

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SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

[Micheal Butz]

Hi,

 

I am trying to establish a FRR in a TSO command processor program that is
not re-entrant this is because

 

Later I schedule a SRB and I want to use the routine I established as a FRR,
as  input to the SRBFRRA parameter

 

While tracing thru TESTAUTH 

 

After establishing a breakpoint at the STM inst  I get the following abend

 

 SETFRR A,FRRAD=SWAPFRR,WRKREGS=(7,8),EUT=YES

*MACDATE03/23/2006   

 L 7,PSACSTK-PSA(0,0)ADDR OF CURRENT 

 CL7,PSANSTK-PSA(0,0)IS CURRENT STACK

*NORMAL STACK

 JNE   *+8   NO, BRANCH  

 OIPSAMFLGS-PSA(0),X'80' IND EUT TYPE FRR

 STM   14,3,16(7)SAVE REGS 14-3  

 

SYSTEM ABEND CODE 0F8   REASON CODE 0014 under TESTAUTH


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Re: SRBEPA

[Micheal Butz]

I am issuing a branch entry form of  a macro, in the SRB 

So for the SRB control block 241,

For the SRB code 227

 Thank you for all your help



-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Chris Craddock
Sent: Monday, October 17, 2011 6:27 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA

On Mon, Oct 17, 2011 at 5:31 PM, Shmuel Metz (Seymour J.) <
shmuel+ibm-m...@patriot.net> wrote:

> In
> ,
> on 10/17/2011
>at 11:27 AM, Chris Craddock  said:
>
> >On the other hand; If you are trying to schedule an SRB into
> >-any-other- address space, then (somehow) you have to make sure
> >the code will be addressable when the SRB is dispatched. In
> >general that means loading it into common storage (technically it
> >should be in SQA rather than CSA, but that's a minor nit)
>
> Why? As long as the address is accessible and the code will be
> addressable, why can't it be private and pagable? MVS can handle a
> page fault in an SRB routine.
>
> Now, if you're going to schedule SRB's into multiple address spaces
> for the same routine, then you would want the code in common so that
> you only need a single copy.



If you can arrange ahead of time for the code to be loaded in the foreign
address space then of course it can be in private. I said as much. It is
also true that SRB's can take page faults, so the SRB code *can* be in
pageable storage... However, it is very desirable for the SRB to be able to
run through its processing without taking any unnecessary page faults. An
ordinary SRB dispatch is an extremely efficient mechanism, but if the SRB
subsequently interrupted and has to be suspended (e.g. for a page fault) the
system has quite a lot of work to do to save its state (SSRB, FRR stack,
linkage stack etc). It is still fast, but why take the hit? Kind of like the
old joke about Ferraris. She's a made a to go, not a to stop.



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Re: SRBEPA

[Micheal Butz]

Page fault that means it does't have to be fixed unless I just don't get it

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Shmuel Metz (Seymour J.)
Sent: Monday, October 17, 2011 6:32 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA

In
,
on 10/17/2011
   at 11:27 AM, Chris Craddock  said:

>On the other hand; If you are trying to schedule an SRB into
>-any-other- address space, then (somehow) you have to make sure 
>the code will be addressable when the SRB is dispatched. In 
>general that means loading it into common storage (technically it 
>should be in SQA rather than CSA, but that's a minor nit)

Why? As long as the address is accessible and the code will be
addressable, why can't it be private and pagable? MVS can handle a
page fault in an SRB routine.

Now, if you're going to schedule SRB's into multiple address spaces
for the same routine, then you would want the code in common so that
you only need a single copy.
 
-- 
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 ISO position; see  
We don't care. We don't have to care, we're Congress.
(S877: The Shut up and Eat Your spam act of 2003)

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Re: SRBEPA

[Micheal Butz]

Does that mean subpool 227 as opposed to to 241

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Jim Mulder
Sent: Monday, October 17, 2011 4:03 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA

IBM Mainframe Discussion List  wrote on 10/17/2011 
01:03:09 PM:

> (E)SQA has the correct storage attributes. (E)SQA is key zero and page
> fixed. You should never load SRB code into anything but key zero and the
> code should never be paged out, hence my use of the term SQA as a 
technical
> nit. You -can- make appropriate choices of subpool and macro options to 
get
> equivalent attributes from (E)CSA and if (as usual) there's no SQA 
available

  The SRB control block must be in fixed common storage.

  There is no requirement for the SRB code to be in fixed storage 
(unless the code executes disabled for I/O and external 
interrupts).

  There is no requirement for the SRB code to be in key zero storage.
Of course, if the code is in common storage or in the private area
of an address space where untrusted code can execute, it should be 
in some system key (0-7).


Jim Mulder   z/OS System Test   IBM Corp.  Poughkeepsie,  NY

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Re: SRBEPA

[Micheal Butz]

The normal sequence then is common when scheduling to a different address
space 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Tom Harper
Sent: Sunday, October 16, 2011 3:39 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA

Michael,

If the target address space is the scheduling address space, then it is
easily possible.

Or, if the target address space is a different address space, it could have
passed the address of the SRB routine earlier.

But, if you are scheduling into an arbitrary address space, placing the code
in common is certainly simpler.

Your questions are asking "what is possible". Perhaps you might be asking
what is best practice, or, even better, tell us what you are trying to
accomplish.

Tom

- Original Message -----
From: Micheal Butz [mailto:michealb...@optonline.net]
Sent: Sunday, October 16, 2011 03:30 PM
To: IBM-MAIN@bama.ua.edu 
Subject: Re: SRBEPA

How can something be addressable in the target address space if is not in
common



-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Sunday, October 16, 2011 7:36 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA

On Sun, 16 Oct 2011 07:09:07 -0400 Micheal Butz 
wrote:

:>Thats what I thought there was a
:>Document XMEM for beginners which said both the SRB and SRB rtn EPA have
to be in common 

The routine only has to be addressable in the target address space.

:>On Oct 16, 2011, at 6:46 AM, Tom Harper  wrote:

:>> No, it does not.

:>> - Original Message -
:>> From: Micheal Butz [mailto:michealb...@optonline.net]
:>> Sent: Sunday, October 16, 2011 06:04 AM
:>> To: IBM-MAIN@bama.ua.edu 
:>> Subject: SRBEPA

:>> Does anyone know if the SRB rtn has to live common

--
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http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


Should you use the mailblocks package and expect a response from me,
you should preauthorize the dissensoftware.com domain.

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Re: SRBEPA

[Micheal Butz]

How can something be addressable in the target address space if is not in
common



-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Binyamin Dissen
Sent: Sunday, October 16, 2011 7:36 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA

On Sun, 16 Oct 2011 07:09:07 -0400 Micheal Butz 
wrote:

:>Thats what I thought there was a
:>Document XMEM for beginners which said both the SRB and SRB rtn EPA have
to be in common 

The routine only has to be addressable in the target address space.

:>On Oct 16, 2011, at 6:46 AM, Tom Harper  wrote:

:>> No, it does not.

:>> - Original Message -----
:>> From: Micheal Butz [mailto:michealb...@optonline.net]
:>> Sent: Sunday, October 16, 2011 06:04 AM
:>> To: IBM-MAIN@bama.ua.edu 
:>> Subject: SRBEPA

:>> Does anyone know if the SRB rtn has to live common

--
Binyamin Dissen 
http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


Should you use the mailblocks package and expect a response from me,
you should preauthorize the dissensoftware.com domain.

I very rarely bother responding to challenge/response systems,
especially those from irresponsible companies.

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Display command for JOBS

[Micheal Butz]

Hi,

 

  Would anyone know when issuing the following console command

 

 

D A,JOBNAME and  OWT is displayed under M/S column

 

What does OWT stand for ?

 

 

thanks 


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SRB routine

[Micheal Butz]

Hi,

 

Does anyone know if the SRB routine SRBEPA has to reside in common

 

 

thanks


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SRB routine

[Micheal Butz]

Hi,

 

Would anyone know if the SRB routine SRBEPA has to reside in common

 

thanks


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Re: SRBEPA

[Micheal Butz]

So if I have a piece of code in my pgm

E.G. RTN000 I can point at EPA to it

E.G LA R3,RTN000
   ST R3,SRBEPA

And set SRBASCB to a different address space

Sent from my iPhone

On Oct 16, 2011, at 7:35 AM, Binyamin Dissen  wrote:

> On Sun, 16 Oct 2011 07:09:07 -0400 Micheal Butz 
> wrote:
> 
> :>Thats what I thought there was a
> :>Document XMEM for beginners which said both the SRB and SRB rtn EPA have to 
> be in common 
> 
> The routine only has to be addressable in the target address space.
> 
> :>On Oct 16, 2011, at 6:46 AM, Tom Harper  wrote:
> 
> :>> No, it does not.
> 
> :>> - Original Message -
> :>> From: Micheal Butz [mailto:michealb...@optonline.net]
> :>> Sent: Sunday, October 16, 2011 06:04 AM
> :>> To: IBM-MAIN@bama.ua.edu 
> :>> Subject: SRBEPA
> 
> :>> Does anyone know if the SRB rtn has to live common
> 
> --
> Binyamin Dissen 
> http://www.dissensoftware.com
> 
> Director, Dissen Software, Bar & Grill - Israel
> 
> 
> Should you use the mailblocks package and expect a response from me,
> you should preauthorize the dissensoftware.com domain.
> 
> I very rarely bother responding to challenge/response systems,
> especially those from irresponsible companies.
> 
> --
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Re: SRBEPA

[Micheal Butz]

Thats what I thought there was a
Document XMEM for beginners which said both the SRB and SRB rtn EPA have to be 
in common 

Sent from my iPhone

On Oct 16, 2011, at 6:46 AM, Tom Harper  wrote:

> Michael,
> 
> No, it does not.
> 
> Tom
> 
> 
> - Original Message -----
> From: Micheal Butz [mailto:michealb...@optonline.net]
> Sent: Sunday, October 16, 2011 06:04 AM
> To: IBM-MAIN@bama.ua.edu 
> Subject: SRBEPA
> 
> Does anyone know if the SRB rtn has to live common
> 
> Thanks in advance
> 
> 
> Sent from my iPhone
> 
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SRBEPA

[Micheal Butz]

Does anyone know if the SRB rtn has to live common

Thanks in advance


Sent from my iPhone

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SRB code

[Micheal Butz]

Hi. 

I know you can'nt issue SVC from a. SRB however PC rtn's are allowed

My question is can that PC rtn issue a
SVC


Thanks



Sent from my iPhone

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Clarification of Sysevent

[Micheal Butz]

Hi,

 The following is a description from SYSEVENT 


  
ENTRY=SVC for the following SYSEVENTs:   
  
   DONTSWAP OKSWAP
   TRANSWAP STGTEST   
   REQASCL REQASD 
   REQSRMST ENQHOLD   
   ENQRLSEREQLPDAT  





 I guess this means I cann't  use branch entry for the above mentioned
sysevents

 

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SRB code

[Micheal Butz]

Hi,

 

I have piece of code that I am running in my program as a SRB the question I
have is the following the 

 

 

  The addressability to this piece of code is that by the base register
established at entry to this program or the code gets control at SRBEPA has
the entry point pointed to by R15

 

 

  thanks   


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Re: TSO TEST Debugging with TPUT and input paramters

[Micheal Butz]

The parameter is a - if I enter a - 

Is the CPPL a half length 1 followed by '-' 

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Tony Harminc
Sent: Thursday, October 06, 2011 6:03 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: TSO TEST Debugging with TPUT and input paramters

On 6 October 2011 17:29, Micheal Butz  wrote:
> When entering the command paramters are they surrounded by quotes

Generally, no. But you have to enter what the command is expecting,
and it's possible that it wants a quoted string.

Are you sure what you have is a TSO command? Certainly any program can
issue TPUT when running under TSO. (For that matter any program
running in batch or CICS or whatever can issue TPUT to an online TSO
terminal.)

What error messages, if any, are you getting?

Tony H.

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Re: TSO TEST Debugging with TPUT and input paramters

[Micheal Butz]

When entering the command paramters are they surrounded by quotes

Thanks

Sent from my iPhone

On Oct 6, 2011, at 4:40 PM, "Williamson, James R"  
wrote:

> When I enter TEST command CP 
> TSO replies enter command for CP. 
> I then enter:   command parameters 
> And if the command is written to TSO command processor standards, it 
> processes the parameters passed to it. 
> 
> The CP parameters are passed differently than the parms for an ordinary 
> program. 
> 
> 
> -Original Message-
> From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf 
> Of Micheal Butz
> Sent: Thursday, October 06, 2011 3:18 PM
> To: IBM-MAIN@bama.ua.edu
> Subject: TSO TEST Debugging with TPUT and input paramters
> 
> Hi
> I have a program I am trying to debug that issues TPUTS so I have to use the 
> CP parm however it has input paramters and they are not passed when using the 
> CP parm 
> 
> Any help appreciated
> 
> Thanks
> 
> Sent from my iPhone
> 
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TSO TEST Debugging with TPUT and input paramters

[Micheal Butz]

Hi
I have a program I am trying to debug that issues TPUTS so I have to use the CP 
parm however it has input paramters and they are not passed when using the CP 
parm 

Any help appreciated

Thanks

Sent from my iPhone

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OUCB usage

[Micheal Butz]

Hi,

 

The OUCB control Block seems to contain information about Virtual storage
swapping. 

 

Would anybody know if that's per page Of Virtual Storage, meaning
ASCBOUCB->OUCB->VITUALSTORAGE PAGE IN THAT AS  



While if I were to issue a SYSEVENT DONTSWAP macro

 

All pages of Virtual Storage in that address would be swapped in

 

 

Thanks  


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IFCID Distributed data Header

[Micheal Butz]

I am looking at a distributed header in memory well the first 2 bytes are
the length of the header meaning if there any long names in this header they
are encompossed in the length

 

At offset +4 I can see the Requester name for 16 bytes the offset for this
field at offset +1c I can see QWHDSVNM for 16 bytes

 

The long name indcator for both of there fields QWHDRQNM_Off and
QWHDSVNM_Off are both zeros however it is clear looking at

in memory that long names for both of there fields exist as they follow the
last field of DSNDQWHD DSECT QWHDEND another

inconsistency the length of the distributed header seems to encompess the
long name of requestor loction name   

Any help clearing this up would be appreciateded

 

 

 


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Re: IFCID Product section layout

[Micheal Butz]

That mean If the Standard Header in the Product section is X'52' bytes in
length the next Header should follow 

It doesn't look like it to me

Thanks

-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Martin Packer
Sent: Thursday, September 08, 2011 9:05 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: IFCID Product section layout

In the same section of the 101 record, stacked one after the other in the 
section. Their lengths are in their first byte (or maybe two).

Martin

Martin Packer,
Mainframe Performance Consultant, zChampion
Worldwide Banking Center of Excellence, IBM

+44-7802-245-584

email: martin_pac...@uk.ibm.com

Twitter / Facebook IDs: MartinPacker
Blog: 
https://www.ibm.com/developerworks/mydeveloperworks/blogs/MartinPacker



From:
Micheal Butz 
To:
IBM-MAIN@bama.ua.edu
Date:
09/09/2011 00:55
Subject:
IFCID Product section layout
Sent by:
IBM Mainframe Discussion List 



I have a question regarding the product section The documentation says 
that
the product section can have may headers seems like there is always a
Standard header, but then the other header might also be present

(correlation, distributed, cpu) my question is if the other headers are
present were would they be located

 

Listed below is a link to the doc 

 

http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/dsnpfk15/5.4.1.4?

SHELF=DSNSHKA4.bks
<
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/dsnpfk15/5.4.1.4

?SHELF=DSNSHKA4.bks&DT=20090429161615&CASE=> &DT=20090429161615&CASE=

 

http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/dsnpfk15/5.4.1?AC

TION=MATCHES
<
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/dsnpfk15/5.4.1?A

CTION=MATCHES&REQUEST=product+section&TYPE=FUZZY&SHELF=DSNSHKA4.bks&DT=20090
429161615&CASE=&searchTopic=TOPIC&searchText=TEXT&searchIndex=INDEX&rank=RAN
K&ScrollTOP=FIRSTHIT%23FIRSTHIT>
&REQUEST=product+section&TYPE=FUZZY&SHELF=DSNSHKA4.bks&DT=20090429161615&CAS
E=&searchTopic=TOPIC&searchText=TEXT&searchIndex=INDEX&rank=RANK&ScrollTOP=F
IRSTHIT#FIRSTHIT

 


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Unless stated otherwise above:
IBM United Kingdom Limited - Registered in England and Wales with number 
741598. 
Registered office: PO Box 41, North Harbour, Portsmouth, Hampshire PO6 3AU






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IFCID Product section layout

[Micheal Butz]

I have a question regarding the product section The documentation says that
the product section can have may headers seems like there is always a
Standard header, but then the other header might also be present

(correlation, distributed, cpu) my question is if the other headers are
present were would they be located

 

Listed below is a link to the doc  

 

http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/dsnpfk15/5.4.1.4?
SHELF=DSNSHKA4.bks
 &DT=20090429161615&CASE=



http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/dsnpfk15/5.4.1?AC
TION=MATCHES

&REQUEST=product+section&TYPE=FUZZY&SHELF=DSNSHKA4.bks&DT=20090429161615&CAS
E=&searchTopic=TOPIC&searchText=TEXT&searchIndex=INDEX&rank=RANK&ScrollTOP=F
IRSTHIT#FIRSTHIT

 


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Re: SYNCH[X] vs LINK[X]

[Micheal Butz]

In a earlier post John Gilmore wrote as long as the copy is  
refershable reusable the Info is kept in the CDE


Sent from my iPhone

On Aug 23, 2011, at 2:47 PM, Gerhard Postpischil   
wrote:



On 8/23/2011 1:05 PM, Micheal Butz wrote:

If I have a peice of code that was MVCL somewere it can'nt be
the object of synch/synch


OK, I'll bite - why not?

Gerhard Postpischil
Bradford, VT

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Re: SYNCH[X] vs LINK[X]

[Micheal Butz]

If I have a peice of code that was MVCL somewere it can'nt be the  
object of synch/synch






Sent from my iPhone

On Aug 23, 2011, at 12:12 PM, john gilmore   
wrote:


Binyamin Dissen has already made the crucial point: LINK[X]  
specifies a name (or alias); SYNCH[X] specifies an address.


An apparently not quite obvious corollary of this distinction is  
that LINK[X] makes a LOAD[X] available under the hood/bonnet; SYNCH 
[X] does not.  The exit routine nominated in a SYNCH[X] macro  
instruction must already be present in virtual storage.  The load  
module or program object nominated in a LINK[X] macro instruction  
need not be.  (A copy known to be present will, of course, be used  
if it is refreshable or reentrant.)


John Gilmore Ashland, MA 01721-1817 USA
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Re: SYNC vs LINK

[Micheal Butz]

Does sync create a SVRB ( for the SVC only) and no RB or PRB for the  
program


Sent from my iPhone

On Aug 23, 2011, at 7:55 AM, Mike Myers   
wrote:



Micheal:

Yes,  as I recall, SYNC  (SVC 12) was designed to invoke exit  
routines on behalf of system routines (like OPEN, CLOSE, etc.), and  
therefore calls on the program by its address (found in some exit  
list or exit pointer), whereas LINK (SVC 6) calls out a program by  
name (as Binyamin says) and was intended for calling separately  
compiled program subroutines, which would have a CDE (either created  
by the LOAD or LINK SVC routine).


Mike Myers
Mentor Services Corporation


On 08/23/2011 07:03 AM, Micheal Butz wrote:

Does that mean sync doesn't have to be associated with a CDE

Sent from my iPhone

On Aug 22, 2011, at 11:07 AM, Binyamin Dissen > wrote:


On Mon, 22 Aug 2011 08:35:06 -0400 Micheal Butz >

wrote:

:>Would any one the difference between the the SYNCH LINK. Macros  
both
:>transfer control and seem to syncrounous execution of code and  
create

:>an RB

SYNC is to address. LINK is to name.

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Director, Dissen Software, Bar & Grill - Israel


Should you use the mailblocks package and expect a response from me,
you should preauthorize the dissensoftware.com domain.

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especially those from irresponsible companies.

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Re: SYNC vs LINK

[Micheal Butz]

Does that mean sync doesn't have to be associated with a CDE

Sent from my iPhone

On Aug 22, 2011, at 11:07 AM, Binyamin Dissen > wrote:


On Mon, 22 Aug 2011 08:35:06 -0400 Micheal Butz >

wrote:

:>Would any one the difference between the the SYNCH LINK. Macros both
:>transfer control and seem to syncrounous execution of code and  
create

:>an RB

SYNC is to address. LINK is to name.

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