low
private subpool: 0-127 (and 131-132 depending on the key)
There is nothing wrong with an unauthorized application using any of the low
privae subpools. After all, they can't use anything else.
Peter Relson
z/OS Core Technology Design
John K wrote:
I had to turn off FLAG(PAGE0) for SWAREQ and TRKCALC.
SWAREQ addressed this almost 15 years ago. TRKCALC was changed over 15 years
ago. Please avoid using ancient versions of macros.
Shmuel wrote:
The obvious example is CVTPTR, which currently is an absolute EQU. Changing
requiring the invoker to include the CVT.
Maybe there are some macros that don't do that. If you find any in z/OS, let me
know and maybe we can get that improved.
Peter Relson
z/OS Core Technology Design
use TPROT on a purported ASCB address and if I didn't get success, I'd know it
wasn't an ASCB address (because an ASCB cannot be paged out).
Peter Relson
z/OS Core Technology Design
were added since the previous release). That gives you the
direct way to see what you can rely upon being available, for whichever you
choose as your oldest release. Maybe that's just me.
Peter Relson
z/OS Core Technology Design
so could have been a candidate for conversion. But
functionally it is not necessary. Anyone who truly wants conversion of the
operand for some reason could avoid using NOP and code a conditional branch
with mask 0. That will get converted.
Peter Relson
z/OS Core Technology Design
refreshed is treated as one that better
not modify itself because at any point it might be refreshed back to a previous
state.
Peter Relson
z/OS Core Technology Design
withdrawal of
the transactional execution facility, even though it is part of the z/OS 2.4
ALS.
Peter Relson
z/OS Core Technology Design
ow me this
as a Right-Unit View DFP value".
Peter Relson
z/OS Core Technology Design
E 24
NOPR 0
immediately before the END
The assembly will work fine. And when you bind it, the "minimum" across the
CSECTs is what will by default be used.
Peter Relson
z/OS Core Technology Design
4 for data such as a DCB, affects only non-reentrant modules. So try to
avoid that.
Peter Relson
z/OS Core Technology Design
macro invocation (perhaps putting
a comment on each line with keyword=value) such as
M A=1,Set the A parameter to ...<* in col 72>
B=2,Set the B parameter to ...<* in col 72>
...
Peter Relson
z/OS Core Technology Design
s Ed Jaffe mentioned, when something like RMODE=SPLIT is used
on the bind of a program object. In the RMODE=SPLIT case you
can end up with one part of the executable in one RMODE and the other part in
another RMODE and V-Con's between the two parts are resolved at module fetch
time.
Peter Relson
quire addressability to wherever a literal generated by the macro might get
placed. Obviously you could set that up temporarily with LARL, wherever needed,
if you choose not to devote a reg for that purpose.
Peter Relson
z/OS Core Technology Design
take care of logic specific to that module, with the recovery mainline doing
the routing and taking care of logic that is general to the flow. We find that
that makes it more natural to keep recovery in synch with module changes.
Peter Relson
z/OS Core Technology Design
rea that can hold both GRs
and ARs).
Do note that there are limits to the number of entries you get by default on
the linkage stack.
And keep in mind that ESTAE-type recovery routine retry is sensitive to the
linkage stack level when the routine is established.
Peter Relson
z/OS Core Technology Design
three are 2-byte
instructions and LHI is a 4-byte instruction comes into play. It is apparent
that LHI creates a bigger instruction-space footprint. That in turn can lead to
increased cache line usage.
Peter Relson
z/OS Core Technology Design
nk older releases of the assembler used to require for each SETC
symbol, but apparently that is no longer required.)
I saw no mention that "SR" is at best the 4th best choice for zeroing a
register. I'll leave the other 3 (and perhaps more) as an exercise for the
reader, for a while.
Peter Relson
z/OS Core Technology Design
oduces the
requisite load module / program object.
Peter Relson
z/OS Core Technology Design
;always be zero".
In any case, that's why we agree that it would be nice to document.
Peter Relson
z/OS Core Technology Design
the reference's GETSTOR function to have the same
information.
Peter Relson
z/OS Core Technology Design
n be easier not having to deal with a WTOR to respond to.
Here, some "CHECK=NO" option would indicate similarly "I do know what I'm
doing".
Peter Relson
z/OS Core Technology Design
B2 EQU *-L'F1,X'20'
Peter Relson
z/OS Core Technology Design
ecifically know what "@PSA" is, so my guess could be wrong. The
two CALC statements are likely too simplistic if you are trying to reference
the PSA's of all processors (such as within a loop), due to the concepts of
prefixing and reverse prefixing.
Peter Relson
z/OS Core Technology Design
nterface has certain characteristics) do not belong on
assembler-list. IBM-Main is a much better choice, getting to a wider audience
of folks who might help.
Peter Relson
z/OS Core Technology Design
rd-aligned). So if you need a section
ordered on a boundary stronger than doubleword, the module must be on a page
boundary.
It is not the case that this necessarily causes the module to be rounded to a
4K multiple.
Peter Relson
z/OS Core Technology Design
R8,PSATOLD-PSA(0)
** ASMA309W Operand PSATOLD-PSA(0) resolved to a displacement with no base
register
0008 5880 021C 021C 6 L
R8,PSATOLD-PSA(,0)
000C 5880 021C 021C 7 L
R8,PSATOLD-PSA(0,0)
Peter Relson
z/OS Core Technology Design
to the default defaults
(I noticed only that you have RMODEX=64TRUE which makes sense but is not the
default default).
Peter Relson
z/OS Core Technology Design
-Original Message-
From: Ed Jaffe
Sent: Thursday, May 4, 2023 8:08 PM
To: Peter Relson ; assembler-list@listserv.uga.edu
Cc: Jonathan
oth load modules and program objects without
requiring the use of COMPAT(ZOSV2R1).
In a simple experiment, this seemed to do the right thing.
I don't have any idea about ALIGNT.
Peter Relson
z/OS Core Technology Design
I suggest, by the way, that you use the TEXT keyword of WTO. It can make things
much more flexible for you, since the message line is then not part of the WTO
expansion, rather just the address of it.
Peter Relson
z/OS Core Technology Design
e the address is not 0 but
still within the first page. The case of 0 is orders of magnitude more likely.
Peter Relson
z/OS Core Technology Design
The assembler's FLAG(PAGE0) is provided to catch at assembly-time errors such as
AHRx,2 when you might have intended AHI Rx,2
Peter Relson
z/OS Core Technology Design
dress in z/OS and locations 0-x'7FF' are set by z/OS
not to be fetch-protected.
Therefore they are accessible to any program, without "access error".
Programming interfaces such as FLCCVT, PSATOLD and PSAAOLD are within this
range.
DO NOT change control register bits.
Peter Relson
EST(R)
IEW2650I 5102 MODULE ENTRY NOT PROVIDED. ENTRY DEFAULTS TO SECTION TEST1.
And if you reversed the includes, entry would default to TEST2.
In the absence of a name on an END statement, I'd think it unwise to rely on
whatever rule might exist, when you have multiple CSECTs.
Peter Relson
Joe,
Please post a small assembler program that, when you assemble it, has the
anomaly you cite. I'd think you could take the Metal C assembler, and strip out
most of it.
The following program, based on the tiny amount of data that you chose to share
in your post, when assembled on z/OS shows
>RMODE(SPLIT)?
The only case in z/OS module fetch processing that pays attention to RSECT is
building the nucleus.
The read-only part of the nucleus consists of RSECTs. The read-write part of
the nucleus consists of CSECTs.
RSECT does not factor into RMODE(SPLIT) processing.
Peter
ion to the binder, and in
some cases has meaning to the operating system. It does have meaning for
modules built into the z/OS nucleus, for example.
Peter Relson
z/OS Core Technology Design
.
Mike S wrote
CATTR use requires GOFF object format, which I don't want to use.
Why would you not want to use GOFF? I can think of only one module in all of
z/OS that cannot use GOFF. I'll let guesses occur before providing the answer
in a day or two.
Peter Relson
z/OS Core Technology Design
,64) on GETMAIN or STORAGE OBTAIN is
easy to code. Or RMODE 24 on your module if the module is not reentrant and you
don't mind the whole loadmod below 16M. Or RMODE=SPLIT in a program object with
suitable RMODE 24 CSECT(s).
Peter Relson
z/OS Core Technology Design
hey do apply across CSECTs in a loadmod or a
program object (include the RMODE=24 and RMODE=31 CSECTs in an RMODE=SPLIT
program object).
Peter Relson
z/OS Core Technology Design
ve
no way of knowing if they could use "LARL" so don't even try.
An entertaining thought for an assembler enhancement would be a pseudo-op that
generated "LA" or "LARL" depending on whether the target was in a CSECT or a
DSECT (maybe allowing for LAY too).
Peter Relson
z/OS Core Technology Design
in the AMODE of the
caller. There are other, long-winded, ways to accomplish this (that quite
possibly no one uses).
The principles of operation is not, for the most part, a user's guide. It is a
user's manual.
Peter Relson
z/OS Core Technology Design
t indicate AMODE 31. How you accomplish that is up to you.
Peter Relson
z/OS Core Technology Design
for using a hypothetical move-long-relative would be the
same as using MVCL, just using LARL where needed. And once the setup has been
done, there is no need for a new instruction.
Peter Relson
z/OS Core Technology Design
nd retried
silently to the next instruction could we consider that the program continues
as expected.
Peter Relson
z/OS Core Technology Design
nstructive use if the OS itself uses LBEAR and STBEAR.
Peter Relson
z/OS Core Technology Design
k to avoid compares and
branches is not, in general, usable within the OS.
Peter Relson
z/OS Core Technology Design
to go.
Here's a simple example with LOCTR
TEST CSECT
MAIN1LOCTR
M1 DSF
SUBR LOCTR
MAIN2LOCTR
M2A DSF
SUBR LOCTR
S1 DSF
MAIN2LOCTR
M2B DSF
END
The order of instructions in the OBJ will be M1, S1, M2A M2B
Peter Relson
z/OS
) with the instruction to be paged
out by an asynchronous process before the program interrupt handler could look.
Just about the only productive use of TPROT is when you are supervisor state
and have reason to know that the storage being accessed is supposed to be
page-fixed. In that case a CC=
ook at the area mapped by IHAFACL and pointed
to by ECVTFACL (you can also use IHAFACL to look at the PSA area, with a little
manipulation to account for the header of the area pointed to by ECVTFACL)
Peter Relson
z/OS Core Technology Design
explicitly.
The issuer of RACROUTE does not generally need to care how the customer set up
their profiles and access lists, so does not care whether access is granted to
an individual user ID or to a group to which the individual user ID is
connected.
Peter Relson
z/OS Core Technology Design
The other downside is that you are in unsupported territory (at least
would be for z/OS). The interface is the executable macro. But at least if
you got it 100% right you could reproduce any problem using a real macro
invocation such that it would become reportable.
Peter Relson
z/OS Core Technology Design
art of its architecture level set.
Peter Relson
z/OS Core Technology Design
ressed that it is to you. It's a great
instruction (which is presumably why it was made available to us mere
mortals from those previously available only to the millicode folks). But
"clearer"? That wouldn't be an adjective I'd use.
Peter Relson
z/OS Core Technology Design
area chain from time of
error and formatting the registers that had been saved). Can the
designation be used for additional things such as Tony T seems to want to
do? I suppose so.
Peter Relson
z/OS Core Technology Design
sing -- if they need to retry and then
return to you, and if the recovery routine was established before your
code updated the linkage stack. That's the sort of situation that might
well exist. For that, your use of the linkage stack would cause things not
to work.
Peter Relson
z/OS Core Technology Design
g the linkage stack, always save the low halves
in the provided 72-byte area, and "high halves" in the area you obtain.
Why do it two different ways? If supporting AMODE 31 and AMODE 64 at the
same point, you might well have required that the AMODE 64 caller provide
a 144-byte area.
Peter Relson
z/OS Core Technology Design
BPXMBATC) was implemented, it used a 72-byte
savearea (and even then the module had a comment that it was OK to invoke
via Attach, LINK, Load/Call, "TSO call" and "Batch/Exec" (maybe that's
EXEC PGM= which is an attach).
The change appears to have been made in z/OS 2.1.
Pe
ooks at the value at +4
to decide if that is the previous pointer or if the previous pointer is at
+x'88'.
Peter Relson
z/OS Core Technology Design
5-1) is part of the linkage conventions.
Peter Relson
z/OS Core Technology Design
Tony wrote:
1) What is "B's save area"?...or is it the save area allocated
by B and used by C when C receives control?
It is the "or" -- B's save area is the save area allocated by B. B
provides that to what it calls (such as C). It will (as filled in by C)
contain B's registers at the time
-byte savearea (I don't know why they didn't similarly change that).
This makes REXX LINK more compatible with REXX ATTACH -- the target
routine in both cases gets a 144-byte savearea.
Peter Relson
z/OS Core Technology Design
are running on a
supported release.
Peter Relson
z/OS Core Technology Design
save the low halves there, and (if
needed) save the high halves in an area that you obtain upon entry and
identify that you have done so in the 2nd word.
Peter Relson
z/OS Core Technology Design
er is not known to be providing a 144-byte save area yet you want/need
to save high halves too.
That situation/approach surely applies to zVSE too.
Peter Relson
z/OS Core Technology Design
d programs. And they're not supported by
Language Environment.
Yes they are compatible (to the extent that is important) and you can use
them in any AMODE. You can chain backwards, interpreting the information
saved at offset 4. You cannot forward-chain.
Peter Relson
z/OS Core Technology Design
at happens or not).
Peter Relson
z/OS Core Technology Design
are
utilizing information produced by the program responsible for dealing with
the subtleties.
Peter Relson
z/OS Core Technology Design
.
Peter Relson
z/OS Core Technology Design
; and need not be
preserved if used.
A program might be able to take advantage of that, if using the regs when
not calling anything.
Only the part about regs 8-15 bytes 0-7 is related to the fact that the VR
storage overlaps the FPR storage.
Peter Relson
z/OS Core Technology Design
the RUCSA feature was added -- although doing that
adding had little if anything to do with user-key CSA being anything other
than a bad idea.
It has never been possible for an unauthorized program to acquire common
storage.
Peter Relson
z/OS Core Technology Design
.
Peter Relson
z/OS Core Technology Design
es regardless of the AMODE of the
caller. But if you are stuck, for compatibility, with the "old (AMODE
31)" callers passing a 72-byte save area, things are more complicated.
Having a unique entry point for each AMODE can be a good approach for such
a case.
Peter Relson
z/OS Core Technology Design
n by "switches between"? It is fine to use a different
style than the style your caller was using (as long as the savearea
provided is big enough to accommodate your needs), without having any care
about what was being used by your caller. The string at +4 identifies how
you saved your c
activate
saving/restoring of the additional FPRs).
Peter Relson
z/OS Core Technology Design
k unit use FPRs 8-15 or VRs?".
If the answer is no, then that work unit does not save/restore those regs
upon undispatch/redispatch and thus saves some cycles.
Peter Relson
z/OS Core Technology Design
that did some sort of "print"? It could indicate that regs 0,1,14,15 are
clobbered (which this did), but that would not be relevant to the function
return.
And does GCC, as IBM C, feel free to remove the __ASM (or whatever the GCC
analog is) in the specific case being discussed? If not, why not?
Peter Relson
z/OS Core Technology Design
>At a minimum, there should be an option to say "Leave the asm alone"
As I had written previously, there is a standards proposal to do just
that.
Peter Relson
z/OS Core Technology Design
The
second applies to the code, but not the first.
True. But one might say that the treating of the __asm text as a black box
does mean that the compiler can "tell" -- basing its "knowledge" on the
user input.
Peter Relson
z/OS Core Technology Design
ation. Then any call should not optimize out the asm
statement.
-- have a #pragma option_override(asmFunct, "OPT(LEVEL,0)") in the same
source file with the function to avoid optimizing the code out
Peter Relson
z/OS Core Technology Design
es, it would be nice if there were a link to it from the z/OS doc.
And when a new version is posted, they append to assembler-list, providing
the link.
Peter Relson
z/OS Core Technology Design
And what is the "default" with respect to getting the compiler to honor
what was coded (and how do you override that default if that default is
not right for the case in hand)?
Peter Relson
z/OS Core Technology Design
SM has to be
produced (unless the default for __ASM is that only things identified as
changed are changed, including global data structures). Maybe you'd get
the same effect with this program if the __asm was instead a "call" to an
external routine.
Peter Relson
z/OS Core Technology Design
index register. That's how
you'd code it in assembler (of course you'd have the "160" where "var"
is).
Peter Relson
z/OS Core Technology Design
from the data
within the LOCTR section. And if you have such addressability then you
could have your LTORG within that LOCTR-defined area too so that anyone's
macros could use literals.
Peter Relson
z/OS Core Technology Design
s that can avoid
the need for reference to storage containing static data.
Peter Relson
z/OS Core Technology Design
entry from the linkage
stack and giving control to the instruction after the PC, in the PC
issuer's state and key (assuming that the key 0 routine did not change the
linkage stack entry itself).
Peter Relson
z/OS Core Technology Design
to IBM-Main.
Peter Relson
z/OS Core Technology Design
ptical that anything provides the RB / linkage stack regs as
the only set of regs, as that is close to useless for debugging.
And of course the SDWA has information about the type of event.
Peter Relson
z/OS Core Technology Design
sed. If there could be concurrent updates, the above approach will
not work.
Peter Relson
z/OS Core Technology Design
that as of z/OS 2.3 (and thus for all
in-full-support z/OS releases) you can rely on the availability of IAF2.
Peter Relson
z/OS Core Technology Design
nment of the operand is not relevant to the discussion. As
pointed out, a misaligned operand would have resulted in a specification
exception.
Peter Relson
z/OS Core Technology Design
alternatives, choose
the one that has the smallest instruction byte footprint.
BCTR is a 2 byte instruction. But don't sacrifice the readability of your
code.
Peter Relson
z/OS Core Technology Design
to run in a known state and then,
if you need to do something based on your called state, switch
conditionally to that, and then switch back to the known state.
Peter Relson
z/OS Core Technology Design
It appears that the editorial rules for Principles of Operation
are stricter than those for Services.
They certainly are. A lot stricter. Related to the fact that the machine
has to enforce restrictions.
Software does not "have to" (but of course it can be nice if it does).
Peter R
As Keven Hall mentioned, If it were required that there be no crossing of
page boundary from TBEGINC through TEND, the principles of operation would
have said so.
There is no such requirement.
Peter Relson
z/OS Core Technology Design
for accessing data that you know is in the primary
address space, saving you from having to set an access register.
Peter Relson
z/OS Core Technology Design
question: yes.
It is a very valuable technique for AR mode.
Peter Relson
z/OS Core Technology Design
, if there is not any reason for it to remain
private, it gets converted to public.
I am told that 148064 has been made public.
Peter Relson
z/OS Core Technology Design
uot; have been coded back then as "...(1,0)" to
avoid getting flagged).
Peter Relson
z/OS Core Technology Design
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