On 2012-08-29 11:42, Edward Jaffe wrote:
On 8/29/2012 11:07 AM, John Ehrman wrote:
But be careful: I've seen many examples of poor coding practices that --
simply because they were familar -- were propagated from one program to
another, to the detriment of all.
When I worked for a large bank
Yep, have seen the same in network design, application design ...design it
config or code it, that's it ...never look back sometimes
Scott ford
www.identityforge.com
On Aug 29, 2012, at 2:50 PM, Martin Truebner wrote:
> Ed,
>
>>> ... is descended from the same singular ...
>
> Happens everywhe
On 29 August 2012 20:42, Edward Jaffe wrote:
> On 8/29/2012 11:07 AM, John Ehrman wrote:
>
>>
>> But be careful: I've seen many examples of poor coding practices that --
>> simply because they were familar -- were propagated from one program to
>> another, to the detriment of all.
>>
>
> When I w
Ed,
>> ... is descended from the same singular ...
Happens everywhere. It is called "first line syndrome".
--
Martin
Pi_cap_CPU - all you ever need around MWLC/SCRT/CMT in z/VSE
more at http://www.picapcpu.de
On 8/29/2012 11:07 AM, John Ehrman wrote:
But be careful: I've seen many examples of poor coding practices that --
simply because they were familar -- were propagated from one program to
another, to the detriment of all.
When I worked for a large bank in the 1980s, and saw how "new" JCL was
co
Binyamin Dissen commented:
>Yes, the difference between real world programming and ivory tower
>programming. In real world programming you want the sequences to be
>familiar so that others can more easily maintain the programs. Those
>with a view from the top of Mt. Olympus may think otherwise, but
Private reply.
Is there a list of the "stereotyped" code sequences? I'm already aware
of the LA and MVI/MVC sequence.
People on the list might like to see a complete list. Would make a great
SHARE presentation!
Regards,
John Ganci
On 8/29/2012 8:58 AM, Edward Jaffe wrote:
On 8/29/2012 6:33 A
I do know of one such list; but it is highly unofficial, not of course
mine, and not for me to disseminate. Someone else may be in a
position to be more helpful.
Worth repeating is that nny such list, like its elements, is
obsolescent when it is published.
Such obsolescence is also a problem wit
On Aug 29, 2012, at 08:35, John Gilmore wrote:
>
> More generally, while IBM's efforts to optimize instruction sequences
> that it finds frequently in its code samples are unambiguously
> praiseworthy, I am more doubtful about systematiic attempts to exploit
> them. Its C-and-PL/I optimization mac
On Aug 28, 2012, at 17:35, Tony Harminc wrote:
>
> You can very quickly find out if an instruction is available on your
> machine by looking at the instruction table provided by the good folks
> at Tachon Software.
>
> http://www.tachyonsoft.com/inst390o.htm
>
Is that up to date? I understand that
I am not really arguing against the use of such functional units as
| . . . MVI/MVC to clear a field by propagation . . .
which I like to call 'idioms'. I had/have rather longer sequences in
mind, and I think Mr Dissen did too.
My railings against the repeated, not very thoughtful use of
stereo
On 8/29/2012 6:33 AM, John Gilmore wrote:
Second, and more important, while Mr Dissen's notion that stereotyped,
'easy to understand' code sequences are to be prized "in the real
world" is his to cherish, I find it unattractive. Such sequences,
often copied unreflectively from elsewhere, are too
Binyamin Dissen writes:
Yes, the difference between real world programming and ivory tower
programming. In real world programming you want the sequences to be
familiar so that others can more easily maintain the programs. Those
with a view from the top of Mt. Olympus may think otherwise, but thei
sday, August 28, 2012 6:35 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> On 28 August 2012 11:24, McKown, John
> wrote:
> > Yes, but I cannot simply relate the "such and such" facility to an
> actual processor.
On Tue, 28 Aug 2012 19:53:00 -0400 Tony Harminc wrote:
:>On 28 August 2012 10:53, Steve Hobson wrote:
:>> Younger readers may like to know that years ago we would test the low two
:>> bits of R15 for zero like this:
:>> CLI *+1,B'1100'
:>> EXR15,*-4
:>> BNE error
On 29 August 2012 01:53, Tony Harminc wrote:
>
> Well, this one is perhaps the perfect example - jocular, of course (as
> made all the clearer by the commented version), but still the sort of
> thing that was to be found in real programs. My suggestion to use
> familiar sequences is to avoid the
On 28 August 2012 10:53, Steve Hobson wrote:
> Younger readers may like to know that years ago we would test the low two
> bits of R15 for zero like this:
>
> CLI *+1,B'1100'
> EXR15,*-4
> BNE error
John Gilmore said a few days ago "On the other hand, familiar
instru
On 28 August 2012 11:24, McKown, John wrote:
> Yes, but I cannot simply relate the "such and such" facility to an actual
> processor. Except by looking at the documentation for the processor. I would
> like the reverse mapping. I.e. look for "such and such" facility and get a
> list of current
On 8/28/2012 5:45 AM, David Bond wrote:
TMLL was included with the first set of Relative and Immediate instructions
way back on the 9672-G2. If you are willing to use AHI and BRC, then there
is not reason not to use TMLL.
I didn't see your response before I wrote mine. I said 'G3' but I'm su
On 8/28/2012 5:27 AM, McKown, John wrote:
Value to be tested is in a register, not storage. On the newer machines, the
TMLL instruction can do this. But I run on a z9BC.
TMLL has been supported since 9672-G3 as TML.
--
Edward E Jaffe
Phoenix Software International, Inc
831 Parkview Drive Nort
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of McKown, John
Sent: Tuesday, August 28, 2012 11:25 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
Yes, but I cannot simply relate the "such and such" facility to an actual
processor. Except by look
On 2012-08-28 11:24, McKown, John wrote:
Yes, but I cannot simply relate the "such and such" facility to an actual processor. Except by
looking at the documentation for the processor. I would like the reverse mapping. I.e. look for "such
and such" facility and get a list of current processors w
ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> "Never" is putting it a bit strong. Suppose you are -- sorry, were --
> writing a macro that generates the code. Do you want a macro parameter
> that specifies a one-byte work area?
>
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of John Gilmore
Sent: Tuesday, August 28, 2012 9:46 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
Keith Riddell writes:
One thought - your method gives eq
"Never" is putting it a bit strong. Suppose you are -- sorry, were --
writing a macro that generates the code. Do you want a macro parameter
that specifies a one-byte work area?
BTW, the reason for omitting comments was to allow the reader a slight
frisson on figuring out how it actually works. A
SM and The
MEGA Life and Health Insurance Company.SM
> -Original Message-
> From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
> l...@listserv.uga.edu] On Behalf Of Robin Vowels
> Sent: Tuesday, August 28, 2012 10:21 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re
tserv.uga.edu] On Behalf Of Gord Tomlin
> Sent: Tuesday, August 28, 2012 9:53 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> Instructions that are not supported on all z/Architecture machines can
> generally be identified in the Pr
From: "Steve Hobson"
Sent: Wednesday, 29 August 2012 12:53 AM
Younger readers may like to know that years ago we would test the low two
bits of R15 for zero like this:
CLI *+1,B'1100'
EXR15,*-4
BNE error
Never necessary to do that:
STC15,X
TMX,3
SEMBLER-
l...@listserv.uga.edu] On Behalf Of Robin Vowels
Sent: Monday, August 27, 2012 8:27 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
How about no registers?
TM X+3,3
BNZ ...
From: "McKown, John"
Sent: Tuesday, 28 August 2012 10:27 PM
Value to be tested is in a register, not storage.
I've already given an example with the data in R15.
On the newer machines, the TMLL instruction can do this. But I run on a z9BC.
-Original Message-
From: IBM Mainframe
On Aug 28, 2012, at 08:53, Steve Hobson wrote:
> Younger readers may like to know that years ago we would test the low two
> bits of R15 for zero like this:
>
> CLI *+1,B'1100'
> EXR15,*-4
> BNE error
>
> Best regards, Steve Hobson
>
Ah, yes; without even a line comment.
Younger readers may like to know that years ago we would test the low two
bits of R15 for zero like this:
CLI *+1,B'1100'
EXR15,*-4
BNE error
Best regards, Steve Hobson
CICS Strategy, HLASM Development, Master Inventor
Hursley Laboratories, MP 189, Room A3138, UK
Ti
Instructions that are not supported on all z/Architecture machines can
generally be identified in the Principles of Operation by the presence
of an entry under Program Exceptions in the form:
- Operation (if the such-and-such facility is not installed)
--
Regards, Gord Tomlin
Action Software I
Sent: Tuesday, August 28, 2012 2:26 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Fwd: Re: which instructions should I use?
>
> Sorry, that wasn't the best (unoptimised branch order), besides being wrong
> and using the wrong register. I must be having
Longborough
Sent: Tuesday, August 28, 2012 2:26 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Fwd: Re: which instructions should I use?
Sorry, that wasn't the best (unoptimised branch order), besides being wrong and
using the wrong register. I must be having a bad hair day.
Here's the amend
-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of McKown, John
Sent: Tuesday, August 28, 2012 9:29 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
Thanks. I didn't realize that. I have trouble understanding from the
SSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> TMLL was included with the first set of Relative and Immediate
> instructions
> way back on the 9672-G2. If you are willing to use AHI and BRC, then
> there
> is not reason not to use TMLL.
>
&g
John,
TMLH and TMLL are part of initial z/ARCH- If you have one of the older
reference cards (or a POP old enough)) you might even find a reference
to note 3.
note 3: also available in 390 mode.
--
Martin
Pi_cap_CPU - all you ever need around MWLC/SCRT/CMT in z/VSE
more at http://www.picapcpu.d
TMLL was included with the first set of Relative and Immediate instructions
way back on the 9672-G2. If you are willing to use AHI and BRC, then there
is not reason not to use TMLL.
On Tue, 28 Aug 2012 07:27:59 -0500, McKown, John wrote:
>Value to be tested is in a register, not storage. On the
Assumes address is in a storage location.
Most of the discussion has been based on the premise that we are talking
about an error code in R15, although the code I was copying was from the
start of the program where Rx contains a function code.
Tony Thigpen
-Original Message -
From: Rob
27, 2012 9:54 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> On 2012-08-27 12:31, Bill Fairchild wrote:
> >
> > LA R0,3
> > NR R1,R15
> > BNZ BAD_RC
> >
> > And in 3 or 4 years, IBM will have implemented all
m: IBM Mainframe Assembler List [mailto:ASSEMBLER-
> l...@listserv.uga.edu] On Behalf Of Robin Vowels
> Sent: Monday, August 27, 2012 8:27 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> How about no registers?
>
> TM X+3,3
> B
Sorry, that wasn't the best (unoptimised branch order), besides being
wrong and using the wrong register. I must be having a bad hair day.
Here's the amended version:
*
LAR0,3 Mask for multiple of 4
NRR0,R1
Bigger RCs are invalid
*
Brent Longborough
> -Original Message -
>
> Date:Mon, 27 Aug 2012 13:19:10 -0400
> From: Tony Thigpen
> Subject: Re: which instructions should I use?
>
> Your code requires 2 scratch
From: "Paul Gilmartin"
Sent: Tuesday, 28 August 2012 12:48 PM
On 2012-08-27 19:36, Robin Vowels wrote:
or, if worried about preserving R15
LR0,15
SLL 0,30
LTR 0,0
BNZ ...
Doesn't SLL set the condition code?
No.
But SLA does.
On 2012-08-27 12:31, Bill Fairchild wrote:
>
> LA R0,3
> NR R1,R15
> BNZ BAD_RC
>
> And in 3 or 4 years, IBM will have implemented all of this logic in a single
> instruction with an opcode something like this: LANRBNZ. And the processors
> will have over 4K different opcodes by then.
>
The
On 2012-08-27 19:36, Robin Vowels wrote:
>
> or, if worried about preserving R15
>LR0,15
>SLL 0,30
>LTR 0,0
>BNZ ...
Doesn't SLL set the condition code?
-- gil
On 2012-08-27 11:26, John Ehrman wrote:
>
> There's no need for a based branch: just write
>
> JH INVALID_RC (as before)
> LARL 0,START
> AR 15,0
> BR 15
> START JRC0
> JRC4
> JRC8
>
Assuming the content of R15 (and R0) is expend
From: "McKown, John"
Sent: Tuesday, 28 August 2012 1:34 AM
Destroys the contents of R15, so I guess I would load R15 into, say, R0 and do
the OR operation on R0. However, I'm on
a z9 and will likely never be on anything more advanced. So I'll need to load
the mask into another register, say
How about no registers?
TM X+3,3
BNZ ...
- Original Message -
From: "Tony Thigpen"
Sent: Tuesday, 28 August 2012 3:19 AM
Your code requires 2 scratch registers. The following uses just 1
scratch register and does not require literal storage:
LA R0,3
NR R0,R15
LTR R0,R0
BNZ
From: "John Gilmore"
Sent: Tuesday, 28 August 2012 1:19 AM
Register contents that are a multiple of 4 are all of the form
x...xx00
Inclusive ORing such a value with the mask
1...1100
and testing the result for equality with this same mask then yields a
simple, low-overhead test for
; From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
> l...@listserv.uga.edu] On Behalf Of Binyamin Dissen
> Sent: Monday, August 27, 2012 3:01 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> On Mon, 27 Aug 2012 14:13:12 -0500
On Mon, 27 Aug 2012 14:13:12 -0500 "McKown, John"
wrote:
:>Very nice! I'll just eliminate the LTR as other posts have shown and use the
AR R15,0 / BR R14 that Mr. Ehrman showed as well. I first came up with my
"solution" when I was a wee, young sysprog and have never bothered to change.
"If i
TennesseeSM and The
MEGA Life and Health Insurance Company.SM
> -Original Message-
> From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
> l...@listserv.uga.edu] On Behalf Of Tony Thigpen
> Sent: Monday, August 27, 2012 12:19 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> S
On 8/27/2012 1:19 PM, Tony Thigpen wrote:
Your code requires 2 scratch registers. The following uses just 1
scratch register and does not require literal storage:
LA R0,3
NR R0,R15
LTR R0,R0
BNZ BAD_RC
Why do you need the LTR? NR sets the condition code.
When I bother to add check
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Tony Thigpen
Sent: Monday, August 27, 2012 12:19 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
Your code requires 2 scratch registers. The
I also use the CL to catch negatives. One of those tricks I got from
this list.
Why the LTR? I don't know. I guess the reason is that I don't hardly
ever use an 'and' so I failed to notice that NR set the correct
condition code when I wrote this many years ago.
Tony Thigpen
-Original Messa
TMLL is better because more compact, assuming that John McKown---We're
in a thicket of Johns---wants to use such an instruction.
--jg
On 8/27/12, John Ehrman wrote:
> John McKown wrote:
>
>>As an example of (1), I quite often do:
>
>>CALL PROGRAM,(PARM1,PARM2),VL
>>CHI R15,=Y(MA
John McKown wrote:
>As an example of (1), I quite often do:
>CALL PROGRAM,(PARM1,PARM2),VL
>CHI R15,=Y(MAXENTRIES)
>JH INVALID_RC
>B*+4(R15)
>START JRC0
>JRC4
>JRC8
>MAXENTRIES EQU *-START/4
There's no need for a based branch:
tserv.uga.edu] On Behalf Of John Gilmore
Sent: Monday, August 27, 2012 10:20 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
Register contents that are a multiple of 4 are all of the form
x...xx00
Inclusive ORing such a value with the mask
1...1100
and t
e-
> From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
> l...@listserv.uga.edu] On Behalf Of John Gilmore
> Sent: Monday, August 27, 2012 12:06 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> What you're doing is fine on
EGA Life and Health Insurance Company.SM
>
>
>> -Original Message-
>> From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
>> l...@listserv.uga.edu] On Behalf Of John Gilmore
>> Sent: Monday, August 27, 2012 10:20 AM
>> To: ASSEMBLER-LIST@LISTSERV.U
Gilmore
> Sent: Monday, August 27, 2012 10:20 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> Register contents that are a multiple of 4 are all of the form
>
> x...xx00
>
> Inclusive ORing such a value with the mask
>
>
r List [mailto:ASSEMBLER-
>> l...@listserv.uga.edu] On Behalf Of Martin Truebner
>> Sent: Monday, August 27, 2012 8:15 AM
>> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
>> Subject: Re: which instructions should I use?
>>
>> John,
>>
>> >> you still ne
gt; To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which instructions should I use?
>
> John,
>
> >> you still need base+displacement desire for an index register;
>
> They come in most cases when there is space in the nibbles for it. But
> for the case you cited
John,
>> you still need base+displacement desire for an index register;
They come in most cases when there is space in the nibbles for it. But
for the case you cited there is no need to cover code in
"procedure division" with a base. (Dynamic storage and literalpool
do have a base!) -Here is
MEGA Life and Health Insurance Company.SM
> -Original Message-
> From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
> l...@listserv.uga.edu] On Behalf Of John Gilmore
> Sent: Friday, August 24, 2012 3:08 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: which i
The comments are essential, and they should motivate (instead of
describing) an instruction sequence.
On the other hand, familiar instruction sequences don't have much
charm for me. They are, I think, more likely to lull readers to sleep
than to be 'more comprehensible'. I, at least, sit up whe
IBM Mainframe Assembler List wrote on
08/24/2012 03:18:55 PM:
> From: Tony Harminc
> ..., write using instructions and instruction sequences that
> are clear and well known. Someone will thank you for it later, even if
> you never meet that someone.
Amen
And leave comments. You may be the pe
IBM Mainframe Assembler List wrote on
08/24/2012 03:12:35 PM:
> From: Martin Truebner
>
> Frank,
>
> as Randy already said
>
> CLI 0(R3),0
> JNE NOT_ZERO
>
> or
>
> TM 0(R3),X'FF'
> JNZ NOT_ZERO
>
> will do without forceing the reader to go to POP and find out what you
> ment (and I would for ce
reportedly).
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Scott Ford
Sent: Friday, August 24, 2012 2:11 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
Is there any really difference between a
BNE
IBM Mainframe Assembler List wrote on
08/24/2012 03:11:25 PM:
> From: Scott Ford
>
> Is there any really difference between a
>
> BNE and a JNE
>
> ?
depends if you have a base register for your code or not.
BNE fails if no base register. JNE fails if label branched to is not in
the same CSEC
On 24 August 2012 14:48, Frank Swarbrick wrote:
> Assembler newbie here; please be gentle.
>
> Given the following:
> - r7 points to the input parm list
> - r2 indexes the input parm list
By fours, I trust...
> I want to see if the first byte of the parm I am interested in is x'00'.
>
>
Frank,
as Randy already said
CLI 0(R3),0
JNE NOT_ZERO
or
TM 0(R3),X'FF'
JNZ NOT_ZERO
will do without forceing the reader to go to POP and find out what you
ment (and I would for certain use one of the new instructions, if I can
replace two against one (or better)).
--
Martin
Pi_cap_CPU - al
y, August 24, 2012 1:54 PM
> To: 'IBM Mainframe Assembler List'
> Subject: RE: which instructions should I use?
>
> I probably would have used:
>
>CLI 0(1,R3),X'00'
>JNE ...
>
> No literal.
>
>
> -Original Message-
Oops.
I meant: CLI 0(R3),X'00'
-Original Message-
From: Randy Schafer
Sent: Friday, August 24, 2012 1:54 PM
To: 'IBM Mainframe Assembler List'
Subject: RE: which instructions should I use?
I probably would have used:
CLI 0(1,R3),X'00'
I probably would have used:
CLI 0(1,R3),X'00'
JNE ...
No literal.
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Frank Swarbrick
Sent: Friday, August 24, 2012 1:48 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sub
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