I do want to point out the elephant in the room however, and that is the Intel
ME firmware, which is still present and active (without it, the silicon won't
be in a state where it could initialize the main cores). If you want a truly
libre firmware system you'll need to look outside of the x86
Good to meet you Aditya!
For POWER9 support, there is an existing port here:
https://github.com/3mdeb/coreboot/tree/talos_2_support
It would be very interesting to get that cleaned up / finished and merged into
the main coreboot tree. We may be able to provide remote access to hardware to
Yes, you are correct. Typing too quickly, thinking of POWER8 :)
- Original Message -
> From: "Merlin Büge"
> To: "Timothy Pearson"
> Cc: "coreboot"
> Sent: Thursday, October 17, 2019 2:40:28 PM
> Subject: Re: [coreboot] Re: OpenBMC on KGP
It's not really PoC quality; FWIW we actually use it in production (with
passwords changed etc.). The main limits that are run into are related to the
tiny AST2050 and its associated Flash device -- there is very little Flash or
RAM available on these platforms (by modern standards) and
My understanding is that this is not possible due to PSP and AGESA binaries.
Even if AMD were to eventually allow the AGESA binary to be used by coreboot,
the PSP remains a signed binary module alongside AGESA, and there would likely
be binary PI modules required as well.
As it stands however
Can you start with a memtest run with the hardware configuration that causes
the kernel bug to trigger?
- Original Message -
> From: "Kinky Nekoboi"
> To: "Vikings GmbH"
> Cc: "Piotr Król" , "coreboot" ,
> "insurgo"
> Sent: Wednesday, October 2, 2019 2:44:22 AM
> Subject: [coreboot]
if
there's interest. :)
Thanks!
- Original Message -
> From: "Vikings GmbH"
> To: "Piotr Król" , insu...@riseup.net
> Cc: "coreboot" , "Timothy Pearson"
> , "Andrew Luke Nesbit"
>
> Sent: Tuesday, September
- Original Message -
> From: "Patrick Georgi"
> To: "Timothy Pearson"
> Cc: "ron minnich" , "David Hendricks"
> , "coreboot"
>
> Sent: Monday, September 2, 2019 3:26:45 AM
> Subject: Re: [coreboot] Re: Web si
- Original Message -
> From: "ron minnich"
> To: "Timothy Pearson"
> Cc: "Patrick Georgi" , "David Hendricks"
> , "coreboot"
>
> Sent: Monday, September 2, 2019 2:56:21 AM
> Subject: Re: [coreboot] Re: Web si
- Original Message -
> From: "Patrick Georgi"
> To: "Timothy Pearson"
> Cc: "David Hendricks" , "coreboot"
>
> Sent: Monday, September 2, 2019 1:06:10 AM
> Subject: Re: [coreboot] Re: Web site revamp
> Am So.,
- Original Message -
> From: "Jonathan Zhang"
> To: "Timothy Pearson"
> Cc: "coreboot"
> Sent: Monday, September 2, 2019 12:06:54 AM
> Subject: Re: [coreboot] Web site revamp
> Hi,
>
> I believe we have consensus that the curre
- Original Message -
> From: "Patrick Georgi"
> To: "Timothy Pearson"
> Cc: "David Hendricks" , "coreboot"
>
> Sent: Sunday, September 1, 2019 10:30:30 AM
> Subject: Re: [coreboot] Re: Web site revamp
> Am So.,
- Original Message -
> From: "ron minnich"
> To: "Patrick Georgi"
> Cc: "Matt B" , "Timothy Pearson"
> , "David Hendricks"
> , "coreboot"
> Sent: Sunday, September 1, 2019 2:49:42 PM
> Subject: Re: [cor
- Original Message -
> From: "David Hendricks"
> To: "Timothy Pearson"
> Cc: "coreboot"
> Sent: Saturday, August 31, 2019 7:08:55 PM
> Subject: Re: [coreboot] Web site revamp
>> If people are not aware of the ME, PSP, AGESA
ll one off entirely to force
the other, but at the same time we do need to be very clear in words that
non-technical people may understand just what is what.
Thanks!
--
Timothy Pearson
Raptor Engineering, LLC
https://www.raptorengineering.com
___
c
open ISA
platforms aims to provide a fully open, auditable boot process with maximum
control over the technology."
Thoughts?
--
Timothy Pearson
Raptor Engineering, LLC
https://www.raptorengineering.com
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org
- Original Message -
> From: "Julius Werner"
> To: "Timothy Pearson"
> Cc: "Martin Roth" , "Peter Stuge" ,
> "coreboot"
> Sent: Thursday, May 2, 2019 5:23:58 PM
> Subject: Re: [coreboot] Re: What maintenance
I would suggest the same industry standard maintenance period that would
normally apply to a commercial, closed source product. For instance, consumer
hardware might only receive a year or two of support from initial release, but
an embedded system might be more typically see 3-5 years or
in their process to join and grow in the community.
>
> The time frame would be early May to early September:
> https://developers.google.com/open-source/gsoc/timeline.
>
> So if you're interested in growing our community, please speak up :-)
>
>
> Thanks,
> Patrick
ep w83795g pre: radeon
>
We should probably create a board documentation tips/tricks section in
GIT since the Wiki is no longer available.
Side note: I still wish there was an easier way to do this; I never
bothered transferring documentation to GIT because of the added time /
complexity vs. the
I think there was some work being put
into adding the relocateable ramstage support but I don't know current
status.
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGIN PGP SIGNATURE-
Version: GnuPG
space taken up with
Talos / Blackbird boards for the most part).
Things should settle down some after Christmas, so I'll see what I can
do to pull the old D16 dev platform back out at that time and start
testing / merging patches. Are there any others that I should also help
take a look at?
-
gt; <mailto:coreboot@coreboot.org>
> https://mail.coreboot.org/mailman/listinfo/coreboot
>
>
>
> --
> Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
> Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft:
> Hamburg
> Geschäftsführer
orate on it.
We have a page on our Wiki here that is attempting to track what is
needed and get a port off the ground:
https://wiki.raptorcs.com/wiki/Coreboot/ToDo
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptoreng
for those platforms;
while they are old enough that the ME can be significantly reduced, it
cannot be completely eliminated.
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGIN PGP SIGNATURE-
Versi
On 11/05/2018 03:44 PM, Daniel Gröber wrote:
> On Sun, Nov 04, 2018 at 02:21:10PM -0600, Timothy Pearson wrote:
>> Since Raptor has the ability to allocate official MACs (non-local),
>> which can be useful at the enterprise level via DHCP pinning, I might
>> see if we can re
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On 11/03/2018 01:51 PM, Daniel Gröber wrote:
> On Sat, Nov 03, 2018 at 01:28:06PM -0500, Timothy Pearson wrote:
>> Very nice work! I too had been intending to work on this at some
>> nebulous date in the future, great to see i
eat to see it actually done and boards
ordered!
Quick question -- how are you handling MAC allocation? Each module
comes with the MAC address on a sticker; the mainboard itself doesn't
have a MAC allocated to the BMC port until the module is installed.
In any case, we'll probably be switching a
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 10/28/2018 06:27 PM, Philipp Stanner wrote:
> Well, which client would you especially recommend?
On my side I'm rather fond of Konversation. Pidgin is decent too.
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (
ill just shut down the real time
channel and make Email seem like the most attractive option. ;-)
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGIN PGP SIGNATURE-
Version: GnuPG v1
iQEcBAEB
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On 06/12/2018 01:14 PM, Timothy Pearson wrote:
> As of late last week:
>
> W have the processor user guide, full register documentation, and a
> smattering of other resources released publicly [1]. The PHB
> documentation is s
-BEGIN PGP SIGNED MESSAGE-
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On 07/21/2018 03:50 PM, taii...@gmx.com wrote:
> On 07/21/2018 04:17 PM, Timothy Pearson wrote:
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA256
>>
>> On 07/19/2018 10:35 PM, taii...@gmx.com wrote:
>>> (not
PUs to run; the only way to tell
is by looking at the board serial and comparing against the tables in an
ASUS errata document.
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGIN PGP SIGNATUR
ce on non-multithreaded games so
> this is disappointing but I will investigate further.
>
> [1] turionpowercontrol, an overclocking software
This sounds like CC6 broke. Can you check to see if CC6 is enabled in
your NVRAM settings?
--
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct
On 07/12/2018 10:41 PM, Kyösti Mälkki wrote:
> On Fri, Jul 13, 2018 at 5:41 AM, Timothy Pearson
> mailto:tpear...@raptorengineering.com>>
> wrote:
>
> Good to know, thanks for testing! I've been looking into relocateable
> ramstage in case suspend was still fai
:
> Hi guys!
>
> I have just tested my KGPE-D16's suspend a few times with the latest
> master and it works fine - takes around a minute to get back to my linux
> terminal.
--
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (swi
db508565d2483394b709654c57533e55eebace51 07/10/2017
>
>>
>> Repeat tests with current master.
>
> Thanks, I will have info for you by the end of the this weekend and I
> will also investigate things myself if S3 doesn't work...
>
Just wanted to follow up on the bise
fab a chip with the right resources, but there is no
reason to actually fab a chip, nor do I personally have the resources to
do so.
In practice, publicly available implementations are what determine the
actual openness of an architecture. Compared to fab and design costs,
everything else is n
On 06/25/2018 02:30 AM, Timothy Pearson wrote:
> On 06/24/2018 08:06 PM, Nico Huber wrote:
>> On 25.06.2018 01:55, Timothy Pearson wrote:
>>> On 06/24/2018 06:41 PM, Timothy Pearson wrote:
>>>> On 06/24/2018 06:35 PM, Nico Huber wrote:
>>>>> On 24.06.20
On 06/24/2018 08:06 PM, Nico Huber wrote:
> On 25.06.2018 01:55, Timothy Pearson wrote:
>> On 06/24/2018 06:41 PM, Timothy Pearson wrote:
>>> On 06/24/2018 06:35 PM, Nico Huber wrote:
>>>> On 24.06.2018 23:52, Timothy Pearson wrote:
>>>>
On 06/24/2018 06:41 PM, Timothy Pearson wrote:
> On 06/24/2018 06:35 PM, Nico Huber wrote:
>> On 24.06.2018 23:52, Timothy Pearson wrote:
>>> On 06/24/2018 03:43 PM, Nico Huber wrote:
>>>> On 24.06.2018 21:37, taii...@gmx.com wrote:
>>>>> On 06/24/20
On 06/24/2018 06:35 PM, Nico Huber wrote:
> On 24.06.2018 23:52, Timothy Pearson wrote:
>> On 06/24/2018 03:43 PM, Nico Huber wrote:
>>> On 24.06.2018 21:37, taii...@gmx.com wrote:
>>>> On 06/24/2018 02:59 PM, ron minnich wrote:
>>>>> On Sun,
omething to work with. And it's open. It is marketed
> as open. It is designed to be open. It is based on an open platform.
I just want to counter this one point. POWER9 is absolutely not power
hungry. I've seen the 8-core chips idle at under 10W, with active loads
maybe in the 40-60W range.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 06/21/2018 01:14 AM, Timothy Pearson wrote:
> On 06/20/2018 09:13 PM, taii...@gmx.com wrote:
>> https://www.phoronix.com/forums/forum/hardware/motherboards-chipsets/1021175-risc-v-sifive-freedom-unleahsed-540-soc-hifive-unleashed-bo
.
>
Their bootloader is a blob in ROM, for what it's worth. They also will
not release source for it [1]. I haven't looked further since that
alone is a dealbreaker for an "open" / auditable chip.
[1] https://www.bunniestudios.com/blog/?p=5127
- --
Timothy Pearson
Raptor
>
>>
>> Repeat tests with current master.
>
> Thanks, I will have info for you by the end of the this weekend and I
> will also investigate things myself if S3 doesn't work...
>
If you can isolate the commit I have time blocked off this week to work
on bringing the
n to an SPI misread somewhere, but more importantly it
appears that:
1.) The SPI controller in the southbridge receives at least some leakage
power from +5VSB, and retains state as a result while the PSU is plugged in.
2.) The board reset lines don't fully reset the SPI controller in the
southbridge
3.)
ng for EARLY_CBMEM_INIT
> northbridge/intel/i440bx<- already tested
> northbridge/via/vx900 <- I know competent person to do this
> soc/intel/fsp_baytrail <- I have hardware and know person to
> double-check
> soc/intel/fsp_broadwell_de <- I
ocs at this point
>
>
> On Thu, Jun 7, 2018 at 5:59 PM Timothy Pearson
> mailto:tpear...@raptorengineering.com>>
> wrote:
>
> For anyone wanting a more affordable development platform for POWER9,
> check out the Talos II Lite:
>
> https://raptorcs.com/TALOSII
painful)?
Looking forward to seeing coreboot on ppc64el systems!
On 05/29/2018 03:45 PM, Timothy Pearson wrote:
> Sorry, can't add todayit's a little over 6,000 pages of new
> documentation. Still, hardly light reading!
>
> On 05/29/2018 03:39 PM, Timothy Pearson wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Sorry, can't add todayit's a little over 6,000 pages of new
documentation. Still, hardly light reading!
On 05/29/2018 03:39 PM, Timothy Pearson wrote:
> Register documentation was published today. Links to the three volumes
> (over 7000
/File:POWER9_Registers_vol2_version1.2_pub.pdf
https://wiki.raptorcs.com/wiki/File:POWER9_Registers_vol3_version1.2_pub.pdf
That leaves only the PHB documentation in process at this point. Almost
there
On 05/12/2018 02:34 AM, Timothy Pearson wrote:
> On 05/03/2018 06:02 PM, ron minnich wrote:
>
>
>> On T
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On 05/03/2018 06:02 PM, ron minnich wrote:
>
>
> On Thu, May 3, 2018 at 1:20 PM Timothy Pearson
> <tpear...@raptorengineering.com <mailto:tpear...@raptorengineering.com>>
> wrote:
>
> -BEGIN PGP SIGNE
dn't need is not implemented yet, which is a situation that
>>> can happen just as well on a fully blob-free board.)
>>>
>>> It's not just free software when you can port it to a completely new
>>> mainboard, in the same way that the coreboot core code is still fr
r class, though
:-) Its successor is better performing but completely closed.
https://www.phoronix.com/scan.php?page=news_item=Raptor-TALOS2-Initial-Tests
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGI
On 05/03/2018 06:02 PM, ron minnich wrote:
>
>
> On Thu, May 3, 2018 at 1:20 PM Timothy Pearson
> <tpear...@raptorengineering.com <mailto:tpear...@raptorengineering.com>>
> wrote:
>
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
> I
arge and
> fragile item from US to Europe)
> I will attend the coreboot conference in september and like Jonathan
> said, I'm really interested by a POWER9 session at this conference.
> Best regards,
> Florentin Demetrescu
>
>
> -
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On 05/03/2018 03:44 AM, Kyösti Mälkki wrote:
> On Wed, May 2, 2018 at 9:22 PM, Timothy Pearson
> <tpear...@raptorengineering.com> wrote:
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA256
>>
>> We've been k
ven vendor cooperation. Being able to shave a
significant amount of time out of the IPL would also show that
coreboot's model provides advantages over a more standard vendor flow.
Is anyone interested in signing on for a long term project of this size?
[1] https://raptorcs.com/TALOSII/
- --
Timot
POWER9 IPL process is rather bloated. It's all open, but
bloated.
I'd love to see a coreboot port done in earnest to POWER9. We have all
the information we need to do it, just need buy-in from serious
developers. Might even be some free hardware in it for interested
people
- --
Timothy Pea
they can't have (basically,
cheap, powerful, and open -- pick two), and just wanted to say that
there are open systems *right now*, no vendor coaxing needed.
Our recommendation for some time has been a mix -- arm64 client devices
(laptops, tablets, etc.) and ppc64el servers. With those two, you can
repla
gt; 2018 and let us change the way of firmware development together!
>
> Further information: www.osfc.io <http://www.osfc.io/>
> Newsletter: https://goo.gl/7JF7NW
> Twitter: osfc_io
>
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
w..) have
> STEALTH access to your banking operations at every moment?...
>
> Florentin
>
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGIN PGP SIGNATURE-
Version: GnuPG v
U's with the same core count but
> differing frequencies?
>
> Thanks
>
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGIN PGP SIGNATURE-
Version: GnuPG v1
iQEcBAEBAgAGBQJaznCJAAoJE
pported.
>
> Regards,
>
> - Eli
>
> On 11/04/18 20:44, Timothy Pearson wrote:
>> I don't know if coreboot has support for differing CPUs in the same
>> mainboard; it's not something I can recall testing at any point.
>>
>> The failure is occurring far bef
oblem.
>
> Any ideas?
>
> Thank you for your help.
>
> Regards,
>
> - Eli
>
>
>
>
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
-BEGIN PGP SIGNATURE--
reboot.git to continue remaining official
> maintenance of what remains of the maintenance of libre-friendly
> hardware, within the coreboot project)
- --
coreboot mailing list: coreboot@coreboot.org
<mailto:coreboot@coreboot.org>
https://mail.coreboot.org/mailman/listinfo/coreboot
<http
Offical firmware (hard to find this link)
> https://docs.broadcom.com/docs/9211_8i_Package_P20_IR_IT_FW_BIOS_for_MSDOS_Windows.zip
>
>
> Unfortunately they have proprietary firmware like all SAS cards but at
> least as they are used you aren't supporting further non-free development.
>
"
> name and while I could simply make something up I instead I wish to
> protest this policy and hear out a justification for it.
>
> This is a project with a main goal of improving security however having
> your name on the internet is almost always going to be bad security.
>
, mandatory plug for Talos II here: these bottlenecks disappear on
newer hardware and you don't have to accept the ME/PSP to get access to
modern speeds. The KGPE-D16 is the last and most powerful
owner-controllable x86 machine, but it is definitely showing its age in
some areas.
> Cheers, Dani
On 02/27/2018 11:15 PM, taii...@gmx.com wrote:
> On 02/22/2018 04:36 PM, Timothy Pearson wrote:
>
>> Actually, for OpenBMC work, hotplugging is often the only way to go.
>> Just be very careful to align the pins correctly the first time; you
>> don't have a second chance
-BEGIN PGP SIGNED MESSAGE-
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Thank you! If you have questions during the process please feel free to
ask.
On 02/26/2018 04:53 AM, James Hebden wrote:
> On Sun, Feb 25, 2018 at 04:25:23AM -0600, Timothy Pearson wrote:
>> On 02/25/2018 02:18 AM, Mike Banon wrote:
inal funding
effort and I haven't had any spare time to try to work on it; been
working on several other projects in what little spare time I have had
over the past year. If anyone else would like to apply the recommended
cleanups and resubmit I'm fine with that.
- --
Timothy Pearson
Raptor En
.."
>>
>>
>> Today's Topics:
>>
>> 1. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
>> 2. Re: OpenBMC & KGPE-D16 (Timothy Pearson)
>> 3. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
>> 4. Re: OpenBMC & KGPE-D16 (Timothy Pearson)
the patches now.
>
> Regards,
>
> - Eli
>
>
> On 24/02/18 00:01, Timothy Pearson wrote:
> You need these patches:
>
> https://review.coreboot.org/#/c/19822/
>
> This one in particular:
>
> https://review.coreboot.org/#/c/coreboot/+/19820/
on any nodes. Halting!
> mct_d: fatalexit
>
> If I remove the BMC module the system boots fine.
>
> I have 4 Micron MT18JSF25672PDZ-1G4F1DD modules, located in CPU1 orange
> slots.
>
> I attach both console logs.
>
> Regards,
>
> - Eli
>
>
>
> On
ou can use a test clip to externally flash it via a flashing device
> (not sure which can do 16 pins though, I would inquire on the flashrom
> mailinglist)
>
> Are you using the latest coreboot? AFAIK coreboot was patched to support
> OpenBMC, so you need a new version with the patches.
t has missing bottom capacitors or scratches on
>> the pads, always ask a seller for a photo of the bottom if you buy a
>> G34 CPU like the 6386SE.
>>> I know my English is very poor,
>> Naah it is fine :]
>>
>
>
- --
Timothy Pearson
Raptor Engineering
+
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 02/20/2018 11:50 AM, Duncan wrote:
> Hi,
>
> taii...@gmx.com:
>> On 01/31/2018 02:16 PM, Timothy Pearson wrote:
>>
>>> -BEGIN PGP SIGNED MESSAGE-
>>> Hash: SHA1
>>>
>>> Since you'
ous it wasn't shiny :-) .
>
> I want to try your OpenBMC port. I readed I have to solder the 20 pin
> connector.
>
> Pin 1 is the squared shape, isn't it? But which is Pin 1 in the female
> connector?
>
> Best regards,
>
> - Eli
>
>
> On 14/02/18 23:42,
ank you for your reply Timothy.
>
> I removed the heatsink and cleaned the cpu contacts.
>
> Now it boots.
>
> Thank you for your support.
>
> Best regards,
>
> - Eli
>
>
> On 14/02/18 22:46, Timothy Pearson wrote:
> Dead / incompatible DIMM,
. The result I think is more or less the same, it doesn't
> arrive to payload.
>
> Memory is installed in A2,B2,C2 and D2 slots.
>
> I spent multiple hours trying to figure where is the problem.
>
> Do you have any ideas?
>
> I attach the console log.
>
> Thanks in adv
ains the successful boot log of the
> fallback image. My test showed, that the board builds and runs fine up
> to the SeaBIOS payload.
>
> I believe there is a problem with the test stand, so could you please
> take it offline for now until you can look into it and provide the
> need
NICs and GFX too). Any off-board, prefetchable
> 64bit BARs that are large (say over 64MiB) in size might a viable
> starting point, where 32bit space would not run out of room. I have
> had a look at this before, but without funding did not pursue for
> submitting or completing it.
&
le some of these damaged CPUs seem to work just fine, I had
> several which do not recognize more than 1-2 pcs of memory and, thus, would
> not recommend buying one of these.
>
> Cheers, Daniel
>
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct l
't figure out how they managed to make it so affordable, this
> is seriously great.
>
> --
> coreboot mailing list: coreboot@coreboot.org
> <mailto:coreboot@coreboot.org>
> https://mail.coreboot.org/mailman/listinfo/coreboot
>
- --
Timothy Pearson
Raptor
Boot firmware, and the newer OCP nodes already come with OpenBMC.
>
>
- --
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
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> meltdown/spectre
>
> [799] via coreboot wrote:
>> Can't "we" build one or maybe two crowd founded secure Laptops (12", 15.x")
>
> The short answer to that is no, no we can't. The long answer is a
> discussion over beers or another prefered bever
ll am under the impression that fixing both issue classes
> requires microcode updates, can you link to a better explanation?
>
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Timothy Pearson
Raptor Engineering
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to do is to create a modern laptop for
>> *everyone* with the extra value of security and privacy, and in the process
>> make FLOSS appealing to mainstream instead of letting it be confined in a
>> niche. I think everyone will be better off with tools to protect their
>> privacy/
ineering effort that
is said to have been put into the Purism machines I wonder what we could
have had if said effort had been put into an aarch64 system instead of
an x86 system?
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Timothy Pearson
Raptor Engineering
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arch done on that).
>
> I hadn't realized that until now when researching an error-free
> response to you, so thanks for helping me notice that mistake in my
> understanding.
>
> Youness.
>
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Timothy Pearson
Raptor Engineering
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cation on why using the term "disabled" is
> valid in this case when HAP is enabled. You are free to disagree if
> that didn't convince you.
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Timothy Pearson
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ht
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On 12/08/2017 08:40 AM, Alberto Bursi wrote:
>
>
> On 12/08/2017 02:59 PM, Timothy Pearson wrote:
>>
>> That's just the HAP bit. The ME is limited but NOT disabled, and the
>> remaining stubs are still hackable [1].
>
les!
>
> Man, there are very serious people out there trying to demystify secrets.
>
> I will read again this article later, very concentrated... Trying to put
> some more comprehensive picture in my mind.
>
> Thank you, all of you, Black Hat, Positive Technology, and ot
(DIY approach)?..
> - And a more "politically sensitive" question (you can simply ignore it if
> it is too dangerous to answer..): do you think that Intel is somewhat ..
> "collaborative" (or at least indifferent..) to this new initiative of Dell or
> System76?..
>
ninstalled / slow fans are disconnected or failed.
Hope this helps!
[1] https://linux.die.net/man/8/fancontrol
[2] https://www.raptorengineering.com/coreboot/kgpe-d16-bmc-port-status.php
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Timothy Pearson
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be used to get around that ?
>
> thx.
>
> --mtx
>
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Timothy Pearson
Raptor Engineering
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t;
> Pierre
Just wanted to follow up with some closure on this thread. Leah
contacted us earlier this year and offered to pay; all debts have been
settled at this point and we have no further qualms or concerns
regarding Libreboot or Minifree.
Thank you all for your understanding!
- --
Tim
; SuperMicro likes to use it but it doesn't look like
any of those boards are supported (there are no reports for any of those
boards in the board status repository [1]).
[1] https://www.coreboot.org/Supported_Motherboards
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Timothy Pearson
Raptor Engineering
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