[gem5-dev] Outstanding RISC-V Instruction Patches

Hi Everyone, I have three patches that make some small changes to RISC-V's instruction formats and fix some bugs with its handling of floating point instructions that have been sitting unreviewed for a couple of weeks. The patches are #6401

Re: [gem5-dev] RISC-V FS support and custom instructions

h/riscv/isa/formats/ and definitions for each type of instruction are in src/arch/riscv/insts/. If you have any specific questions about the current ISA definition or on how to implement certain kinds of instructions, I'd be happy to help. -Alec Roelke On Thu, Jan 11, 2018 at 4:37 AM, Chri

Re: [gem5-dev] Interface for RISC-V custom instructions

Hi Robert, Are you trying to reduce compilation time of gem5 itself by bypassing the decoder description, or are you trying to add the ability to specify custom instructions in a simulation script so gem5 doesn't have to be recompiled at all to add new ones? -Alec Roelke On Thu, Feb 8, 20

Re: [gem5-dev] Interface for RISC-V custom instructions

oder. > > Robert > > Am 14.02.2018 um 03:08 schrieb Alec Roelke: > > Hi Robert, > > > > Are you trying to reduce compilation time of gem5 itself by bypassing the > > decoder description, or are you trying to add the ability to specify > custom > > instruc

[gem5-dev] Collaboration on Patches?

sonal branch of gem5 on GitHub or other git repository and then somehow push changes from there to Gerrit? Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Collaboration on Patches?

cond, as a maintainer, I believe you have enough access to just > overwrite > > someone else's commit. For instance, if you download a changeset, then > > rebase, then push to refs/for/master it will update the review request. > So, > > as a maintainer, you can make a smal

Re: [gem5-dev] Collaboration on Patches?

y research group and that's what we used > when I was at Wisconsin, too. > > Cheers, > Jason > > On Thu, Apr 19, 2018 at 12:02 PM Alec Roelke wrote: > > > I'm not trying to suggest that there should be an "official" way to > > collaborate on

Re: [gem5-dev] Collaboration on Patches?

ly long) list of > blog posts I need to write. > > Cheers, > Jason > > On Sat, Apr 21, 2018 at 5:29 PM Alec Roelke wrote: > > > That's essentially what I was getting at, but I think you put it better. > > If I do that, then what is the best way to create

Re: [gem5-dev] RISC-V Full System Support?

Hi Hesham, As Jason mentioned, there is some rudimentary support for FS simulation of RISC-V, but currently it doesn't support RISC-V's privilege modes. There are some additional patches that improve support, but those are also limited. They can be found at: - https://gem5-review.googlesourc

[gem5-dev] Micro-op Data Dependency

data dependency between the two micro-ops in the instruction? Or, better yet, is there a way I could somehow have two memory accesses in one instruction without having to split it into micro-ops? Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org

[gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

process.cc 8bc53d5565ba tests/test-progs/hello/bin/riscv/linux/hello 8bc53d5565ba Diff: http://reviews.gem5.org/r/3624/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

iscv/linux/system.cc PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION src/arch/riscv/microcode_rom.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3624/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

-- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3624/#review8722 --- On Sept. 15, 2016, 3:19 p.m., Alec Roelke wrote: &g

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

ISC-V test suite on your code? > > (https://riscv.org/software-tools/riscv-tests/) In fact, we could probably > > incorporate some (all?) of that into the regression tests. How much we > > include depends on how long the tests take. > > Alec Roelke wrote: > Yeah,

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

ur patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/utility.hh PRE-CREATION src/arch/riscv/vtophys.hh PRE-CREATION src/b

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

ur patches (such as handling locked memory). [Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] Signed-off by: Alec Roelke Diffs (updated) --

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3624/#review8728 --- On Sept. 15, 2016, 8:53 p.m., Alec Roelke wrote: > > ---

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

sa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/stacktrace.hh PRE-CREATION src/arch/riscv/mmapped_ipr.hh PRE-CREATION src/arch/riscv/pagetable.hh PRE-CREATION src/

[gem5-dev] Review Request 3627: riscv: [Patch 2/5] Added RISC-V multiply extension RV64M

instruction set, RV64I. Patch 3 will implement the floating point extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A; and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. Signed-off by: Alec Roelke Diffs

[gem5-dev] Review Request 3628: riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

: Alec Roelke Diffs - src/arch/riscv/utility.hh PRE-CREATION src/arch/riscv/registers.hh PRE-CREATION src/arch/riscv/faults.hh PRE-CREATION src/arch/riscv/faults.cc PRE-CREATION src/arch/riscv/isa/bitfields.isa PRE-CREATION src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch

[gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

t extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. Signed-off by: Alec Roelke Diffs - src/arch/riscv/isa/bitfields.isa PRE-CREATION src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch/riscv/isa/formats

[gem5-dev] Review Request 3630: riscv: [Patch 5/5] Added missing support for timing CPU models

Roelke Diffs - build_opts/RISCV PRE-CREATION src/arch/riscv/isa_traits.hh PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3630/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list

Re: [gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

nted the single- and double-precision floating point extensions, RV64FD. Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4. [Added missing file amo.isa] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/bitfields.isa

Re: [gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

or, and detailed CPU models that isn't present in patches 1-4. [Added missing file amo.isa] Signed-off by: Alec Roelke Diffs - src/arch/riscv/isa/bitfields.isa PRE-CREATION src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch/riscv/isa/formats/amo.isa PRE-CREATION src/arch/risc

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

e=58133#file58133line58> > > > > Not convention See my comment for pagetable.hh. - Alec --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3624/#review8

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

files that are more or less > > 1:1 copies from other architectures? > > Alec Roelke wrote: > I didn't; I used cp and then hg add. Does hg copy do anything different? > > Andreas Hansson wrote: > Yeah that is a bit of an issue. If you didn't actually use

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

les copied from other architectures using hg copy.] Signed-off by: Alec Roelke Diffs (updated) - build_opts/RISCV PRE-CREATION ext/libelf/elf_common.h 49cbf4bb0d36 src/arch/riscv/RiscvISA.py PRE-CREATION src/arch/riscv/RiscvInterrupts.py PRE-CREATION src/arch/riscv/RiscvSystem.py PR

Re: [gem5-dev] Review Request 3627: riscv: [Patch 2/5] Added RISC-V multiply extension RV64M

patches. [Added mulw instruction that was missed when dividing changes among patches.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/decoder.isa PRE-CREATION Diff: http://reviews.gem5.org/r/3627/diff/ Testing --- Thanks, Alec Roelke

Re: [gem5-dev] Review Request 3628: riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

from the first four patches. [Fix exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/faults.hh PRE-CREATION src/arch/riscv

Re: [gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

e patches.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/bitfields.isa PRE-CREATION src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch/riscv/isa/formats/amo.isa PRE-CREATION src/arch/riscv/isa/formats/formats.isa PRE-CREATION src/arch/riscv/isa/formats/me

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

files that are more or less > > 1:1 copies from other architectures? > > Alec Roelke wrote: > I didn't; I used cp and then hg add. Does hg copy do anything different? > > Andreas Hansson wrote: > Yeah that is a bit of an issue. If you didn't actually use

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

was first created.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/linux/process.cc PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION src/arch/riscv/microcode_rom.hh PRE-CREATION src/arch/riscv/mmapped_ipr.hh PRE-CREATION src/arch/riscv/pagetable.hh PRE-CREATION

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

was first created.] Signed-off by: Alec Roelke Diffs (updated) - build_opts/RISCV PRE-CREATION ext/libelf/elf_common.h 49cbf4bb0d36 src/arch/riscv/RiscvISA.py PRE-CREATION src/arch/riscv/RiscvInterrupts.py PRE-CREATION src/arch/riscv/RiscvSystem.py PRE-CREATION src/arch/riscv/Riscv

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

24/diff/8/?file=59259#file59259line2> > > > > Was the spacing like this (in this and other files)? I think > > traditionally we did not align the legal entity names. It was (same for the others). I'll change it though. On Oct. 12, 2016, 8:31 a.m., Ale

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

was first created.] [Fixed spacing for some copyright attributions.] Signed-off by: Alec Roelke Diffs (updated) - tests/test-progs/hello/bin/riscv/linux/hello 49cbf4bb0d36 src/arch/riscv/system.cc PRE-CREATION src/arch/riscv/tlb.hh PRE-CREATION src/arch/riscv/tlb.cc PRE-CREATION src/

Re: [gem5-dev] Review Request 3630: riscv: [Patch 5/5] Added missing support for timing CPU models

memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] Signed-off by: Alec Roelke Diffs (updated) - build_opts/RISCV PRE-CREATION src/arch/riscv/isa_traits.hh PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3630/diff/ Testing

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

On Oct. 12, 2016, 8:31 a.m., Alec Roelke wrote: > > Some minor questions and cosmetic issues. > > > > Could you please also confirm that the files that are copied (and then > > modified) started out as hg copy (as previously discussed). > > > > Besides that

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] Signed-off by: Alec Roelke Diffs (updated) - build_opts/RISCV PRE-CREATION ext/libelf/elf_common.h 49cbf4bb0d36 src/arch/riscv/RiscvISA.py PRE-CREATION src/

Re: [gem5-dev] Review Request 3630: riscv: [Patch 5/5] Added missing support for timing CPU models

memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] Signed-off by: Alec Roelke Diffs (updated) - build_opts/RISCV PRE-CREATION src/arch/riscv/isa_traits.hh PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION

Re: [gem5-dev] Review Request 3630: riscv: [Patch 5/5] Added missing support for timing CPU models

memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] Signed-off by: Alec Roelke Diffs (updated) - build_opts/RISCV PRE-CREATION src/arch/riscv/isa_traits.hh PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION

[gem5-dev] Review Request 3668: riscv: [Patch 6/5] Improve Linux emulation for RISC-V

are as follows: - readlinkat - sigprocmask - ioctl - clock_gettime - getrusage - getrlimit - setrlimit The first five patches implemented RISC-V with the base ISA and multiply, floating point, and atomic extensions and added support for detailed CPU models with memory timing. Signed-off by: Alec

[gem5-dev] Remote GDB with Multiple Instruction Widths?

sed ones. Is my interpretation correct? If so, how do other ISAs (notably x86) handle breakpoints on variable instruction widths? Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Remote GDB with Multiple Instruction Widths?

ased on a target binary you > give it. > > Somebody who's more familiar with how ARM does it could probably give you a > better answer. > > Gabe > > On Sat, Aug 10, 2019 at 6:56 AM Alec Roelke wrote: > > > I'm trying to fix the remote connection to GDB in RISC-V

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

#x27;t have any errors or warnings like you're describing. I tried compiling it on a virtual machine running Ubuntu 14.04 and gcc 4.8.4, it also works. I tested with gem5.debug and gem5.fast. - Alec --- This is an

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

> > > I'm not sure if the problem is that you've based this on an older version > > of gem5, or maybe we're just using different compilers (I'm use gcc-4.8). > > Alec Roelke wrote: > I ignored a few of the style warnings because I saw some other places i

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/bitfields.isa PRE-CREATION src/arch

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

is is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3624/#review8952 ------- On Oct. 21, 2016, 6:12 p.m., Alec Roelke wrote: > > --- > This is

Re: [gem5-dev] Review Request 3628: riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv

Re: [gem5-dev] Review Request 3630: riscv: [Patch 5/5] Added missing support for timing CPU models

memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] [Fixed some style errors in locked_mem.hh.] Signed-off by: Alec Roelke Diffs (updated) - build_opts/RISCV PRE-CREATION src/arch/riscv/isa_traits.hh PRE-CREATION

Re: [gem5-dev] Review Request 3668: riscv: [Patch 6/5] Improve Linux emulation for RISC-V

els with memory timing. [Fixed incompatibility with changes made from patch 1.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/linux/linux.hh PRE-CREATION src/arch/riscv/linux/process.cc PRE-CREATION Diff: http://reviews.gem5.org/r/3668/diff/ Testing --- Thank

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

> > > I'm not sure if the problem is that you've based this on an older version > > of gem5, or maybe we're just using different compilers (I'm use gcc-4.8). > > Alec Roelke wrote: > I ignored a few of the style warnings because I saw some other places i

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

> > > I'm not sure if the problem is that you've based this on an older version > > of gem5, or maybe we're just using different compilers (I'm use gcc-4.8). > > Alec Roelke wrote: > I ignored a few of the style warnings because I saw some other places i

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

> > > I'm not sure if the problem is that you've based this on an older version > > of gem5, or maybe we're just using different compilers (I'm use gcc-4.8). > > Alec Roelke wrote: > I ignored a few of the style warnings because I saw some other places i

Re: [gem5-dev] Status of RISC-V patches

I'll certainly add regressions for "hello" for each of the four models, and I'll try to get other "quick" tests done the same way, too. I won't be able to do all of them as m5threads hasn't been implemented for RISC-V, but I'll do what I can. I can also do the "long" ones the same way, if time is

Re: [gem5-dev] Status of RISC-V patches

But that's a project for another day :). > > Again, I want to stress that we can't expect you to spend lots of time > writing great regressions. It would be very hypocritical :). Anything is > acceptable. Of course, better regressions mean that RISC-V will be more > usable

Re: [gem5-dev] Status of RISC-V patches

using. For the most part, > all of the tests are just functional tests. The configurations for the > system are specified in the tests/configs () Python files. > > Hopefully this will help you get started. Let us know if you have more > questions. Maybe someone with more regression te

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Diffs (updated) - build_opts/RISCV PR

Re: [gem5-dev] Review Request 3624: arch: [Patch 1/5] Added RISC-V base instruction set RV64I

on v1.9" (https://riscv.org/specifications/privileged-isa/). - Alec --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3624/#review9006 -------

Re: [gem5-dev] Review Request 3628: riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

PRE-CREATION src/arch/riscv/isa/includes.isa PRE-CREATION src/arch/riscv/isa/operands.isa PRE-CREATION src/arch/riscv/registers.hh PRE-CREATION src/arch/riscv/utility.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3628/diff/ Testing --- Thanks, Alec Roelke

Re: [gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

ple patches.] [Fixed some minor formatting issues.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/operands.isa PRE-CREATION src/arch/riscv/registers.hh PRE-CREATION src/arch/riscv/types.hh PRE-CREATION src/arch/riscv/isa/bitfields.isa PRE-CREATION src/arch/

Re: [gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/bit

Re: [gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/main.isa

Re: [gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/bitfields

[gem5-dev] RISC-V RV64A Implementation (Review Request #3629)

;m going to leave patch 4 as it is and implement the corrections in a new patch that will come out before the regression patch. Also, I would have preferred to say this in a comment to patch 4 on the review board, but I couldn't find a comment field

Re: [gem5-dev] Review Request 3629: riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

that will come out before the regression patch. - Alec Roelke On Nov. 2, 2016, 2:36 a.m., Alec Roelke wrote: > > --- > This is an automatically generated e-mail. To reply, visit

Re: [gem5-dev] RISC-V RV64A Implementation (Review Request #3629)

ad the regressions you're making are robust enough to find bugs, too! > > I believe you can "review" your own patch on reviewboard in order to add a > comment to it. > > Cheers, > Jason > > On Tue, Nov 1, 2016 at 10:49 PM Alec Roelke wrote: > > > He

[gem5-dev] Review Request 3693: riscv: [Patch 7/5] Corrected LRSC semantics

upport for more detailed CPU models and the sixth patch corrected the implementations of Linux constants and structs. There will be an eighth patch that adds some regression tests for the instructions. Signed-off by: Alec Roelke Diffs - src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch

Re: [gem5-dev] Review Request 3693: riscv: [Patch 7/5] Corrected LRSC semantics

e) + pkt->getSize() <= blkSize' failed. I can't seem to track down what's causing the error. Can anybody help me? - Alec Roelke On Nov. 2, 2016, 7:34 p.m., Alec Roelke wrote: > > --- > This is an automatic

Re: [gem5-dev] Review Request 3693: riscv: [Patch 7/5] Corrected LRSC semantics

> On Nov. 2, 2016, 7:38 p.m., Alec Roelke wrote: > > This doesn't work with the O3 CPU model; I wrote a simple program that > > performs a lr.w followed by sc.w that works with the atomic-simple, > > timing-simple, and minor CPU models, but with the O3 model I get

[gem5-dev] Review Request 3694: riscv: [Patch 8/5] Added some regression tests to RISC-V

functionality. Signed-off by: Alec Roelke Diffs - tests/test-progs/insttest/src/riscv/rv64f.h PRE-CREATION tests/test-progs/insttest/src/riscv/rv64f.cpp PRE-CREATION tests/test-progs/insttest/src/riscv/rv64i.h PRE-CREATION tests/test-progs/insttest/src/riscv/rv64i.cpp PRE-CREATION tests

Re: [gem5-dev] Review Request 3694: riscv: [Patch 8/5] Added some regression tests to RISC-V

#3693), and apparently it is caused by an issue with the O3 model and performing a load or store that crosses a cache line. Is the other error caused by this as well? - Alec Roelke On Nov. 3, 2016, 7:36 p.m., Alec Roelke wrote: > >

Re: [gem5-dev] Review Request 3693: riscv: [Patch 7/5] Corrected LRSC semantics

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3693/#review9030 --- On Nov. 2, 2016, 7:34 p.m., Alec Roelke wrote: > > ---

Re: [gem5-dev] Review Request 3693: riscv: [Patch 7/5] Corrected LRSC semantics

h.] Signed-off by: Alec Roelke Diffs (updated) - src/arch/riscv/isa/decoder.isa PRE-CREATION src/arch/riscv/isa/formats/mem.isa PRE-CREATION src/arch/riscv/locked_mem.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3693/diff/ Testing --- Thanks, A

Re: [gem5-dev] Review Request 3693: riscv: [Patch 7/5] Corrected LRSC semantics

> On Nov. 2, 2016, 7:38 p.m., Alec Roelke wrote: > > This doesn't work with the O3 CPU model; I wrote a simple program that > > performs a lr.w followed by sc.w that works with the atomic-simple, > > timing-simple, and minor CPU models, but with the O3 model I get

[gem5-dev] RISC-V Patches

have not encountered this except when trying to run some of the regression tests I made for patch 3694 on O3. It would make the most sense to change patch 3624 to fix it, but since that would delay shipping it, I think it would be better to make a new patch. Thanks, Alec Roelke

Re: [gem5-dev] RISC-V Patches

while :). > > Cheers, > Jason > > On Sun, Nov 20, 2016 at 2:20 PM Alec Roelke wrote: > > > Hello Everyone, > > > > It has been about two weeks since the last review for my 8 RISC-V patches > > except the 7th patch, so it seems to me like most of them can be

Re: [gem5-dev] Review Request 3694: riscv: [Patch 8/5] Added some regression tests to RISC-V

, only a subset are tested due to similar functionality. [Added directories for o3-timing tests that don't work.] Signed-off by: Alec Roelke Diffs (updated) - tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json PRE-CREATION tests/quick/se/02.insttest/ref/

[gem5-dev] changeset in gem5: riscv: [Patch 7/5] Corrected LRSC semantics

rected the implementations of Linux constants and structs. There will be an eighth patch that adds some regression tests for the instructions. [Removed some commented-out code from locked_mem.hh.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power diffs

[gem5-dev] changeset in gem5: riscv: [Patch 6/5] Improve Linux emulation fo...

- setrlimit The first five patches implemented RISC-V with the base ISA and multiply, floating point, and atomic extensions and added support for detailed CPU models with memory timing. [Fixed incompatibility with changes made from patch 1.] Signed-off

[gem5-dev] changeset in gem5: riscv: [Patch 5/5] Added missing support for ...

.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power diffstat: build_opts/RISCV |2 +- src/arch/riscv/isa_traits.hh |2 + src/arch/riscv/locked_mem.hh | 111 ++ 3 files changed, 91 insertions(+), 24 deletions

[gem5-dev] changeset in gem5: riscv: [Patch 2/5] Added RISC-V multiply exte...

support for timing, minor, and detailed CPU models that is missing from the first four patches. [Added mulw instruction that was missed when dividing changes among patches.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power diffstat: src/arch

[gem5-dev] changeset in gem5: riscv: [Patch 8/5] Added some regression test...

defined in linux/process.hh, some have been given numbers but not definitions for the toolchain, or are merely stubs that always return 0. Of the ones that do work properly, only a subset are tested due to similar functionality. Signed-off by: Alec Roelke

[gem5-dev] changeset in gem5: riscv: [Patch 3/5] Added RISCV floating point...

simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power diffstat: src/arch/riscv/faults.cc |7 + src/arch/riscv/faults.hh

[gem5-dev] changeset in gem5: arch: [Patch 1/5] Added RISC-V base instructi...

copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power diffstat:

[gem5-dev] Review Request 3780: riscv: Fix crash when syscall argument reg index is too high

://reviews.gem5.org/r/3780/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

t/src/riscv/rv64i.cpp 97eebddaae84 Diff: http://reviews.gem5.org/r/3781/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

riscv/linux-rv64i/minor-timing/config.json 97eebddaae84 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout 97eebddaae84 Diff: http://reviews.gem5.org/r/3781/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list gem

Re: [gem5-dev] Review Request 3780: riscv: Fix crash when syscall argument reg index is too high

ff? - Alec --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3780/#review9261 ------- On Jan. 12, 2017, 9 p.m., Alec Roelke wrote: >

Re: [gem5-dev] Review Request 3780: riscv: Fix crash when syscall argument reg index is too high

process.cc 97eebddaae84 Diff: http://reviews.gem5.org/r/3780/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

.gem5.org/r/3781/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

e-mail. To reply, visit: http://reviews.gem5.org/r/3781/#review9294 --- On Jan. 23, 2017, 7:36 p.m., Alec Roelke wrote: > > --- > This is an autom

[gem5-dev] RISC-V: Unknown opcode 0x00

know what's going on? Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

rv64i/simple-timing/simerr 97eebddaae84 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout 97eebddaae84 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt 97eebddaae84 Diff: http://reviews.gem5.org/r/3781/diff/ Testing --- Thanks, Alec R

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3781/#review9301 --- On Jan. 24, 2017, 4:33 p.m., Alec Roelke wrote: > > --- > This is an

[gem5-dev] changeset in gem5: riscv: Fix crash when syscall argument reg in...

changeset ada5603bdb1c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ada5603bdb1c description: riscv: Fix crash when syscall argument reg index is too high By default, doSyscall gets the values of six registers to be used for system call arguments.

Re: [gem5-dev] RISC-V: Unknown opcode 0x00

Hi Everyone, Does anybody know anything about how gem5 reads binaries and why this problem might be happening? If full-system mode for RISC-V is to be supported in the future (and probably for multithreading in SE mode as well), this will probably need to be fixed. Thanks, Alec Roelke On Mon

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

riscv/linux-rv64i/simple-timing/stats.txt 63325e5b0a9d Diff: http://reviews.gem5.org/r/3781/diff/ Testing --- Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request 3781: riscv: Remove ECALL tests from insttest

v64i output directory, but I still don't see them here. - Alec --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3781/#review9316 -------

[gem5-dev] changeset in gem5: riscv: Remove ECALL tests from insttest

changeset 0e73ec98b6bc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0e73ec98b6bc description: riscv: Remove ECALL tests from insttest The system calls tested in rv64i.cpp in RISC-V's insttest suite have different behavior depending on the operating

[gem5-dev] Exception in Speculated Instruction?

e.com/c/2340/2 - https://gem5-review.googlesource.com/c/2341/2 Thanks, Alec Roelke ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

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