Hello Kazi,
If by core to core communication latency, you are referring to the latency
imposed by read sharing a cache block, you can use TrafficGenerator from
gem5 stdlib. The example below is most probably not the best way to do
this, but I could successfully measure the latency of moving the
Hello Kazi,
Can you direct me on how I can reproduce the error you are getting? Can you
please answer the following questions?
- What script are you running?
- What command are you using?
- What version of gem5 are you using (which commit/branch)?
- Did you build gem5 with DRAMSim3?
Best
Hello Kazi,
I looked at the script and you should make the following changes:
from gem5.components.memory import SingleChannelDDR3_1600 --> from
gem5.components.memory.dramsim_3 import SingleChannelDDR3_1600
requires(isa_required=ISA.ARM) --> requires(isa_required=ISA.X86), if it
does not work
Hello Kazi,
Take a look at configs/example/gem5_library/arm-hello.py. It is a good
example of SE mode for ARM ISA. If you are interested in instantiating a
memory module look at lines 47, and 62 from the same file.
P.S. I'm checking out the stable branch on the gem5 repo
(Hash:
Hello Travis,
You need to write a script that describes the system you want to test with
synthetic traffic, then you can add a PyTrafficGen to your system. The
PyTrafficGen object has several functions that generate the traffic you
want such as createLinear, createRandom, createDram, createIdle,
Hello,
I would say overall DRAMSim3 is more accurate and to be honest it is much
easier to use than DRAMSim2. I am also doing an evaluation on memory models
between DRAMSim3 and gem5, based on the current results I would suggest you
use either DRAMSim3 (using the temporary solution I proposed) or
Btw, the controller from DRAMSim3 does not need an interface connected to
itself (the timings for those models come from DRAMSim3).
Best,
On Wed, Mar 24, 2021 at 6:31 PM Mahyar Samani wrote:
> Hello Monica, Aravind, and Ipshita
>
> Currently the script in configs/common/MemConfig.py does not
Hello Monica, Aravind, and Ipshita
Currently the script in configs/common/MemConfig.py does not work with
DRAMSim3 models. You can create a DRAMSim3 controller using the following
piece of code (ini_path should point the ini file for the DRAMSim3 model
you would like to use):
class
Hey Anthony,
Can you send more information to reproduce this error?
Best Regrads
On Sat, Dec 5, 2020 at 2:40 AM anthonyabeo--- via gem5-users <
gem5-users@gem5.org> wrote:
> Hi Everyone,
>
> I am new here and just started playing with gem5. I run into an error (as
> specified in the subject)
Hey Yogeshwaran,
Since the gem5-20.1 release, it now supports DRAMSim3 integration so there
is no need for you to follow the instructions there. There is a readme file
in ext/dramsim3 that you can follow and build gem5 with DRAMSim3, also,
class DRAMSim3 inherits from AbstractMemory which will
ink this will require any packet of size to spend 2 cycles in
> the XBar, limiting bandwidth. I fixed this by taking the max of 1 cycle and
> the payloadDelay instead, however, I’m unsure if this is correct.
>
>
>
> *From:* Mahyar Samani via gem5-users
> *Sent:* October 20, 2020 8:
Hey Fisher,
The XBar can at maximum deliver a bandwidth equivalent to 1 packet size
(which I believe is 64 bytes) per cycle (e.g. if the clk_freq is set to
1GHz, it will at max deliver 64GBps). Does this information comply with the
results you are seeing?
Best Regards,
On Tue, Oct 13, 2020 at
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