Access on ALESERV

2012-06-13 Thread Micheal Butz
Hi, Can anyone explain to me the significance of the ACCESS parameter on the ALESERV MACRO THANKS -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message:

Re: ALESEERV AL=PASN

2012-06-12 Thread Micheal Butz
available to all units of work in the pasn address space. --Dave On 6/12/2012 7:09 AM, Micheal Butz wrote: > Hi, > > > > Does AL=PASN on the ALESERV macro mean that the ALET is available to all > address spaces > > > > Which is the same concept LXRES w

ALESEERV AL=PASN

2012-06-12 Thread Micheal Butz
Hi, Does AL=PASN on the ALESERV macro mean that the ALET is available to all address spaces Which is the same concept LXRES with SYSTEM=YES Correct ?? -- For IBM-MAIN subscribe / signoff / archive access instruction

Re: SRB mode question

2012-06-10 Thread Micheal Butz
- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz Sent: 10 June 2012 16:30 To: IBM-MAIN@bama.ua.edu Subject: SRB mode question Hi, It's been a while since I scheduled an SRB If I use any IBM services in a SRB I use the branch entry from but I just l

SRB mode question

2012-06-10 Thread Micheal Butz
Hi, It's been a while since I scheduled an SRB If I use any IBM services in a SRB I use the branch entry from but I just looked at some documentation "Cross memory for beginners" And it seems PC rtns are also okay in SRB mode didn't specify SSWITH (space switch or not) Just wanted to

Re: EXTRACT,QEDIT macro

2012-04-24 Thread Micheal Butz
Thank you -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Gerhard Postpischil Sent: Monday, April 23, 2012 8:49 PM To: IBM-MAIN@bama.ua.edu Subject: Re: EXTRACT,QEDIT macro On 4/23/2012 5:30 PM, Micheal Butz wrote: > If after issuing

Re: EXTRACT,QEDIT macro

2012-04-24 Thread Micheal Butz
Thank you -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Tony Harminc Sent: Monday, April 23, 2012 6:25 PM To: IBM-MAIN@bama.ua.edu Subject: Re: EXTRACT,QEDIT macro On 23 April 2012 17:30, Micheal Butz wrote: >  I have a quest

EXTRACT,QEDIT macro

2012-04-23 Thread Micheal Butz
Hi, I have a question regarding the usage of the Extract Qedit macros for operator communication I have started task looking to process a Flush Or Modify command via the com/cib the pointer to the CIB is just for the current task If after issuing the EXTRACT to get the address of the c

Re: Explination of S0C4 reason code 4 and related data areas

2012-04-22 Thread Micheal Butz
areas On Fri, 20 Apr 2012 17:19:25 -0400 Micheal Butz wrote: :>Was wondering If someone could clear up some things for me :>A S0C4 reason code 4 means the storage key and the PSW key don't match :>typically trying to access storage key 0 when the PSW key is key 8 Usually update, b

Explination of S0C4 reason code 4 and related data areas

2012-04-20 Thread Micheal Butz
Hi, Was wondering If someone could clear up some things for me A S0C4 reason code 4 means the storage key and the PSW key don't match typically trying to access storage key 0 when the PSW key is key 8 Two questions arise from this . Does it matter what the PSW key at the

Re: 0C4 pic 4

2012-04-15 Thread Micheal Butz
the key as determined by IVSK, why not simply do it in Key 0? On Sun, 15 Apr 2012 13:29:55 -0400 Micheal Butz wrote: :>Hi, :> :> :> :> :> :> I am getting S0C4 04 within a wait which leads me to believe that the :>storage key of the ECB storage key is not the same as the

0C4 pic 4

2012-04-15 Thread Micheal Butz
Hi, I am getting S0C4 04 within a wait which leads me to believe that the storage key of the ECB storage key is not the same as the PSW STORAGE KEY 8- 11 Does the following code make sense to resolve this address TESTAUTH FCTN=1 TEST APF AUTORIZATION

Re: System completion code 201

2012-04-11 Thread Micheal Butz
: System completion code 201 On Tue, 10 Apr 2012 18:07:28 -0400, Micheal Butz wrote: >Hi > >I have a piece of CSA storage sp 241 >That I am obtaining in key 8 >(I know this is a no no) > >When go to supervisor state should i code KEY=NZERO on the modeset I am assuming &g

System completion code 201

2012-04-10 Thread Micheal Butz
Hi I have a piece of CSA storage sp 241 That I am obtaining in key 8 (I know this is a no no) When go to supervisor state should i code KEY=NZERO on the modeset I am assuming NZERO is 8 or should I specifically set the storage key to 8 As I am getting a system 201 durning a post/wait of an ECB

Re: SLIP PER Sotroage Alteration SVC dump

2012-04-06 Thread Micheal Butz
=== From: Micheal Butz To: IBM-MAIN@bama.ua.edu Date: 04/06/2012 03:42 PM Subject: SLIP PER Sotroage Alteration SVC dump Sent by: IBM Mainframe Discussion List Hi, I just got a hit and generated an SVC dump from a SLIP Storage Alteration My memory sort of

SLIP PER Sotroage Alteration SVC dump

2012-04-06 Thread Micheal Butz
Hi, I just got a hit and generated an SVC dump from a SLIP Storage Alteration My memory sort of escapes me on what IPCS option I would find the culprit that caused the storage overlay >From memory I do believe it would be one of the IPCS traces if someone could help I would app

Re: tcp/ip EZASMI concurrent server problem GIVE/TAKESOCET

2012-04-04 Thread Micheal Butz
www.identityforge.com On Apr 4, 2012, at 12:35 AM, Alan Altmark wrote: > On Tue, 3 Apr 2012 12:01:47 -0400, Micheal Butz > wrote: >> When I get incoming connection via SELECT/ACCEPT I move the low order ½ from >> retocde from the accept call which is the new socket I will be c

tcp/ip EZASMI concurrent server problem GIVE/TAKESOCET

2012-04-03 Thread Micheal Butz
Hi, I have an assembler concurrent server using the EZASMI interface, I am using 4 ports from my IP address 192.168.1.111 I do a socket,bind listen using ip,port,socket I create four subtasks (ATTACH) to process connection on these 4 ports, I pass these task a parameter list of KEY 8 subpool 1

Debugging EZASMI

2012-04-01 Thread Micheal Butz
Hi, I am trying to debug a TCP/IP server as a template I am using the following flow chart from a document by Tony Thigpen http://dinomasters.com/coolstuff/2004EZA.pdf My Client is a Windows MFC C++ program I have multiple connections going as per the document The accept macro I

EZASMI debugging and stimer routine

2012-03-30 Thread Micheal Butz
Hi, I have a two folded question First on debugging a TCP/IP program using the EZASMI interface. Second a question about the EZASMI ACCEPT service . I have been writing TCP/IP started task to communicate with Windows MFC C++ The Assembler started task uses the EZASMI interf

Re: WTOR problem

2012-03-19 Thread Micheal Butz
ove Street * Newton, MA 02466-2272 * USA Tel: +1.781.684.2305 Email: rsc...@rs.com Web: www.rocketsoftware.com -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz Sent: 19 March 2012 14:07 To: IBM-MAIN@bama.ua.edu Subject: Re: WTOR pr

Re: WTOR problem

2012-03-19 Thread Micheal Butz
Behalf Of Micheal Butz Sent: 19 March 2012 14:07 To: IBM-MAIN@bama.ua.edu Subject: Re: WTOR problem Rob, I understand that however moving the model *statement* would be sufficient if I coded WTOR MF=(E,WTOR_LIST) By coding WTOR TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_LX

Re: WTOR problem

2012-03-19 Thread Micheal Butz
o not have this functionality. Rob Scott Lead Developer Rocket Software 275 Grove Street * Newton, MA 02466-2272 * USA Tel: +1.781.684.2305 Email: rsc...@rs.com Web: www.rocketsoftware.com -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Mi

WTOR problem

2012-03-19 Thread Micheal Butz
Hi, I am having problems with following coding generating a re-entrable version of the WTOR below is the relvant code LTORG DEBUG_MESS DC C'THE BASE ADDRESS IS ' TBL DC240X'00' DCC'0123456789ABCDEF' WS_DSE

Re: Enclave SRB's

2012-03-16 Thread Micheal Butz
Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz Sent: 16 March 2012 15:35 To: IBM-MAIN@bama.ua.edu Subject: Enclave SRB's Hi, I am looking for information on the use of enclave SRB/TCB'

Enclave SRB's

2012-03-16 Thread Micheal Butz
Hi, I am looking for information on the use of enclave SRB/TCB's maybe an example of the usage Thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the mess

Re: LAE instruction

2012-03-07 Thread Micheal Butz
get address space must be non-swappable. > > > Raymond Wong > > > > -Original Message- > From: Micheal Butz > To: IBM-MAIN > Sent: Tue, Mar 6, 2012 8:30 pm > Subject: Re: LAE instruction > > > Or a more practical use of LAE > > s cha

Re: LAE instruction

2012-03-06 Thread Micheal Butz
Scott > Lead Developer > Rocket Software > 275 Grove Street * Newton, MA 02466-2272 * USA > Tel: +1.781.684.2305 > Email: rsc...@rs.com > Web: www.rocketsoftware.com > > > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.ed

Re: LAE instruction

2012-03-06 Thread Micheal Butz
Scott > Lead Developer > Rocket Software > 275 Grove Street * Newton, MA 02466-2272 * USA > Tel: +1.781.684.2305 > Email: rsc...@rs.com > Web: www.rocketsoftware.com > > > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On

Re: LAE instruction

2012-03-06 Thread Micheal Butz
But plays no role as far as access register value Sent from my iPhone On Mar 6, 2012, at 3:48 PM, "Shmuel Metz (Seymour J.)" wrote: > In <02fb01ccfbcb$fca77eb0$f5f67c10$@net>, on 03/06/2012 > at 02:04 PM, Micheal Butz said: > >> . What would the sac

Re: LAE instruction

2012-03-06 Thread Micheal Butz
al Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz Sent: Tuesday, March 06, 2012 3:07 PM To: MVS List Server 1 Subject: Re: LAE instruction Sorry misspelled the name John McKown. Excuse me Sent from my iPhone On Mar 6, 2012, at 4:00 PM, Micheal B

Re: LAE instruction

2012-03-06 Thread Micheal Butz
M Mainframe Discussion List > [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz > Sent: Tuesday, March 06, 2012 3:00 PM > To: IBM-MAIN@bama.ua.edu > Subject: Re: LAE instruction > > John Mckiwns reply was a explanation of the SAC inst. > Which I am aware of > > T

Re: LAE instruction

2012-03-06 Thread Micheal Butz
Sorry misspelled the name John McKown. Excuse me Sent from my iPhone On Mar 6, 2012, at 4:00 PM, Micheal Butz wrote: > John Mckiwns reply was a explanation of the SAC inst.Which I am aware of > > The Doc for LAE says the inst the functionality is dependent on PSW bits > >

Re: LAE instruction

2012-03-06 Thread Micheal Butz
.781.684.2305 > Email: rsc...@rs.com > Web: www.rocketsoftware.com > > > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf > Of Micheal Butz > Sent: 06 March 2012 19:59 > To: IBM-MAIN@bama.ua.edu > Subject: Re: LAE inst

Re: LAE instruction

2012-03-06 Thread Micheal Butz
lue. > > You need : "LAE R3,0(,R4)" > > This will ensure that AR3 is populated from the AR for the referenced base > register R4. > > > Rob Scott > Lead Developer > Rocket Software > 275 Grove Street * Newton, MA 02466-2272 * USA > Tel: +1.781.68

LAE instruction

2012-03-06 Thread Micheal Butz
Hi, I have two part question regarding the LAE instruction . What would the sac value e.g. 256,512,768 have to be that when using the LAE instructions with the following operands LAE 3,0(R4) would AR3 get loaded with AR4 . Second what value does the displacement play i

Re: Return code = X'14' from ATTACH JSTCB=YES

2012-03-04 Thread Micheal Butz
I ran it as command processor TESTAUTH ' ' CP And it worked -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz Sent: Sunday, March 04, 2012 5:00 PM To: IBM-MAIN@bama.ua.edu Subject: Re: Return code =

Re: Return code = X'14' from ATTACH JSTCB=YES

2012-03-04 Thread Micheal Butz
ES On Sun, 4 Mar 2012 16:31:44 -0500 Micheal Butz wrote: :>Hi, :> :> :> :>I got a return code of X'15' from ATTACH JSTCB=YES :> :> :> :> :> :> :> :> :>14 :> :> :> :&

Return code = X'14' from ATTACH JSTCB=YES

2012-03-04 Thread Micheal Butz
Hi, I got a return code of X'15' from ATTACH JSTCB=YES 14 Meaning: Program error. An authorized task that specified JSTCB=YES is not a job step task.

Re: Linkage tables

2012-03-04 Thread Micheal Butz
Got it Sent from my iPhone On Mar 4, 2012, at 1:47 PM, Ray Overby wrote: > Assuming this data is produced by a "summary format" in IPCS I believe the LX > is 2B and the EX is 00. > > On 3/4/2012 11:46 AM, Micheal Butz wrote: >> PC >> NUMBER >>

IPCS VSMDATA

2012-03-04 Thread Micheal Butz
Hi, I am trying to track some storage allocation thru IPCS using VSMDATA There are four data areas described by VSMDATA DQE (descriptor Queue element) FQE (free queue element) SPQE (subpool queue element) SPQA (subpool queue anchors) The DQE describes storage allocated from

Re: Linkage tables

2012-03-04 Thread Micheal Butz
PC NUMBER 2B00 The Following PC number is for LX or linkage index 0 as The high order 0's signify -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Peter Relson Sent: Sunday, March 04, 2012 8:32 AM To: IBM-MAI

Linkage tables

2012-03-03 Thread Micheal Butz
Hi Does anyone know how to display the linkage tables from an IPCS dump assuming I dump PCAUTH address space Sent from my iPhone -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua

Re: TCBTQE

2012-02-26 Thread Micheal Butz
Are these created by Z/OS or by the user or both Sent from my iPhone On Feb 26, 2012, at 3:50 PM, Edward Jaffe wrote: > On 2/26/2012 12:04 PM, Micheal Butz wrote: >> Does the TCBTQE contain the TQE (time slice for that task to run) > > TCBTQE points to the chain of TQEs mapped

TCBTQE

2012-02-26 Thread Micheal Butz
Hi, Does the TCBTQE contain the TQE (time slice for that task to run) -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

Re: DU-AL in IPCS dump

2012-02-24 Thread Micheal Butz
-> DUCT On Thu, 23 Feb 2012 20:35:52 -0500 Micheal Butz wrote: :>In a ipcs dump where can I see a TCBs. DU-AL :> :>Sent from my iPhone :> :>-- :>For IBM-MAIN subscribe / signoff / archive access instructions,

DU-AL in IPCS dump

2012-02-23 Thread Micheal Butz
In a ipcs dump where can I see a TCBs. DU-AL Sent from my iPhone -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

Princeple of operations link with Grande instructions

2012-02-22 Thread Micheal Butz
Hi, Would anyone have a link to POP's book/PDF with 64 bit instructions thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

Re: Difference between DREF storage and Page fixed storage

2012-02-22 Thread Micheal Butz
: Re: Difference between DREF storage and Page fixed storage On 2/22/2012 12:51 AM, Micheal Butz wrote: > Please explain I/O should not be done to DREF using "DREF storage as buffer > area for I/O" Anything referenced by the I/O channel program should be fixed. -- Edward E Jaffe

Re: Difference between DREF storage and Page fixed storage

2012-02-22 Thread Micheal Butz
e error. I suggest you re-read the macro's doc very carefully, and then use FIXED storage unless the doc clearly explains why DREF will work. Bill Fairchild -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz Sent: Wednesday

Re: Difference between DREF storage and Page fixed storage

2012-02-22 Thread Micheal Butz
Please explain I/O should not be done to DREF using "DREF storage as buffer area for I/O" When I used sysplex IXG macros to obtain member information the doc said use DREF storage -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Edward Ja

Re: ACCESS=PUBLIC on ALESERV macro

2012-02-21 Thread Micheal Butz
, 2012 at 2:15 PM, Micheal Butz wrote: > If I adding the STOKEN of another address to either my DU-AL PASN-AL can I > specify PUBLIC on the ALESERV macro and bypass the authorization) > > Typically when I get the alet of another address I do a AXSET to give > myself > authori

Difference between DREF storage and Page fixed storage

2012-02-21 Thread Micheal Butz
Hi, Would any know the difference between (disabled reference storage) DREF e.g. subpool 215 and Page fixed storage e.g. subpool 223 >From what I understand DREF means the program is running disable for interrupts and thus no pagIing should occur so the doc say use DREF storage While fixed st

ACCESS=PUBLIC on ALESERV macro

2012-02-21 Thread Micheal Butz
Hi, If I adding the STOKEN of another address to either my DU-AL PASN-AL can I specify PUBLIC on the ALESERV macro and bypass the authorization) Typically when I get the alet of another address I do a AXSET to give myself authorization to go there Would adding PUBLIC entry for the ALET

Entry point on attach

2012-02-17 Thread Micheal Butz
Hi Again if I do a attach with disp=no And r1 has the tcb address I can look at the TCBRBP or relating CDE for the loadpoint of the module Sent from my iPhone -- For IBM-MAIN subscribe / signoff / archive access instructions, s

Program entry point on Attached program

2012-02-17 Thread Micheal Butz
Hi, I know that if a program is re-entrant a subsequent ATTACH will use that address as the entry point. How about a non-reentrant program If I do a ATTACH DISP=NO is the attached program LOADED and if so is there a way to find the entry point

EXTRACT FIELDS=COMM for subtasks

2012-02-10 Thread Micheal Butz
Hi, I know EXTRACT FIELDS=COMM (using the ECB) for stop or modify command works for the TCB your running dunning the course of my programming I attach 4 other subtasks is there any parameter on the ATTACH e.g. like ALCOPY( work for access lists) where I can share COMECBPT among subtasks th

Assembler list

2012-01-19 Thread Micheal Butz
Hi, Would anyone know how to subscribe to the assembler list Thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

Re: Cics Global User Exit

2012-01-09 Thread Micheal Butz
-Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Micheal Butz Sent: Monday, January 09, 2012 3:52 PM To: IBM-MAIN@bama.ua.edu Subject: Cics Global User Exit Do CICS Global User exits have to be loaded In CSA Sent from my iPhone

Cics Global User Exit

2012-01-09 Thread Micheal Butz
Do CICS Global User exits have to be loaded In CSA Sent from my iPhone -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: INFO IBM-MAIN

CICS Global exit XEIIN

2012-01-08 Thread Micheal Butz
Hi, I have assembled and enabled CICS exit XEIIN It is my understanding that it should get invoked whenever a CICS api is encountered However this doesn't seem to be the case if anyone could shed some light on this I would appreciate it thsnks ---

Re: Debugging CICS Global User Exits

2012-01-08 Thread Micheal Butz
Yes Are Global Exits loaded in CSA -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Edward Jaffe Sent: Sunday, January 08, 2012 1:21 AM To: IBM-MAIN@bama.ua.edu Subject: Re: Debugging CICS Global User Exits On 1/7/2012 8:12 PM, Micheal

Debugging CICS Global User Exits

2012-01-07 Thread Micheal Butz
Hi, Would anyone know the best method to debug CICS Global User Exits For MVS I usually used XDC -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the mes

Re: Control Blocks Generated By Attach

2012-01-01 Thread Micheal Butz
2012 15:09:01 -0500 Micheal Butz wrote: :>If I do 4 attaches to the same program then there will be only one copy of :>the program If RENT. :>But each TCB will have its own set of RB's indicating where each task is to :>resume processing Yes. In fact, ATTACH terminates bef

Control Blocks Generated By Attach

2012-01-01 Thread Micheal Butz
Hi, If I do 4 attaches to the same program then there will be only one copy of the program But each TCB will have its own set of RB's indicating where each task is to resume processing -- For IBM-MAIN subscribe

Re: register Values TCBGRS vs TCBRB->XRBREGS

2011-12-22 Thread Micheal Butz
FIRST dispatched but later on is the RB constantly updated Sent from my iPhone On Dec 22, 2011, at 3:59 PM, "Shmuel Metz (Seymour J.)" wrote: > In , on 12/22/2011 > at 08:30 AM, Micheal Butz said: > >> How about when the TCBs CPU time slice is up and control Is g

Re: register Values TCBGRS vs TCBRB->XRBREGS

2011-12-22 Thread Micheal Butz
How about when the TCBs CPU time slice is up and control Is given up to a different task Thanks Sent from my iPhone On Dec 22, 2011, at 8:16 AM, Peter Relson wrote: >> Would anyone know what the differences at a point in time between the >> values in TCBGRS and The Values of the registers in

register Values TCBGRS vs TCBRB->XRBREGS

2011-12-19 Thread Micheal Butz
Hi, Would anyone know what the differences at a point in time between the values in TCBGRS and The Values of the registers in XRBREGS of the RB pointed to by TCBRB I am assuming of course TCBRB is the currently executing RB THANKS -

Testing g RTM routine

2011-10-27 Thread Micheal Butz
Hi, Would anyone know how to test the RTM routine of a SRB when I issue a schedule even though SRB activity is asynchronous it takes off automatically -- For IBM-MAIN subscribe / signoff / archive access instructio

Re: SRBEPA

2011-10-23 Thread Micheal Butz
Sp 226 -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Peter Relson Sent: Sunday, October 23, 2011 10:06 PM To: IBM-MAIN@bama.ua.edu Subject: Re: SRBEPA >There is not much of a real difference. SQA will even overflow into CSA. It is a mat

Re: z/OS Control block question

2011-10-22 Thread Micheal Butz
Cann't a Authorized program do a ATTACH JSTCB=YES anytime -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Wayne Driscoll Sent: Saturday, October 22, 2011 8:29 PM To: IBM-MAIN@bama.ua.edu Subject: Re: z/OS Control block question Please

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-18 Thread Micheal Butz
tober 18, 2011 3:10 AM To: IBM-MAIN@bama.ua.edu Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH On Tue, 18 Oct 2011 00:26:08 -0400 Micheal Butz wrote: :>I am trying to issue a branch entry form of a macro in a other address :>space since the specifications say PASN=HASN=SASN

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-17 Thread Micheal Butz
ashing your system. Sent from my iPad On Oct 17, 2011, at 10:07 PM, Micheal Butz wrote: > I didn't issue any SVC > > The code blew up under TESTAUTH at the fifth instruction after the > expansion of the SETFRR macro > > I normally get 0F8 when I am in XMEM mode and i

Re: SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-17 Thread Micheal Butz
I didn't issue any SVC The code blew up under TESTAUTH at the fifth instruction after the expansion of the SETFRR macro I normally get 0F8 when I am in XMEM mode and issue a SVC I didn't abended on a SVC I abended whitin STM of the SETFRR inst -Original Message- From: IBM Mainframe

SYSTEM ABEND CODE 0F8 REASON CODE 00000014 under TESTAUTH

2011-10-17 Thread Micheal Butz
Hi, I am trying to establish a FRR in a TSO command processor program that is not re-entrant this is because Later I schedule a SRB and I want to use the routine I established as a FRR, as input to the SRBFRRA parameter While tracing thru TESTAUTH After establishing a breakpoint a

Re: SRBEPA

2011-10-17 Thread Micheal Butz
I am issuing a branch entry form of a macro, in the SRB So for the SRB control block 241, For the SRB code 227 Thank you for all your help -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Chris Craddock Sent: Monday, October 17, 2011

Re: SRBEPA

2011-10-17 Thread Micheal Butz
Page fault that means it does't have to be fixed unless I just don't get it -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Shmuel Metz (Seymour J.) Sent: Monday, October 17, 2011 6:32 PM To: IBM-MAIN@bama.ua.edu Subject: Re: SRBEPA In , o

Re: SRBEPA

2011-10-17 Thread Micheal Butz
Does that mean subpool 227 as opposed to to 241 -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf Of Jim Mulder Sent: Monday, October 17, 2011 4:03 PM To: IBM-MAIN@bama.ua.edu Subject: Re: SRBEPA IBM Mainframe Discussion List wrote on 10/17/20

Re: SRBEPA

2011-10-16 Thread Micheal Butz
certainly simpler. Your questions are asking "what is possible". Perhaps you might be asking what is best practice, or, even better, tell us what you are trying to accomplish. Tom - Original Message ----- From: Micheal Butz [mailto:michealb...@optonline.net] Sent: Sunday, October 1

Re: SRBEPA

2011-10-16 Thread Micheal Butz
, 16 Oct 2011 07:09:07 -0400 Micheal Butz wrote: :>Thats what I thought there was a :>Document XMEM for beginners which said both the SRB and SRB rtn EPA have to be in common The routine only has to be addressable in the target address space. :>On Oct 16, 2011, at 6:46 AM, Tom Harp

Display command for JOBS

2011-10-16 Thread Micheal Butz
Hi, Would anyone know when issuing the following console command D A,JOBNAME and OWT is displayed under M/S column What does OWT stand for ? thanks -- For IBM-MAIN subscribe / signoff / archive access in

SRB routine

2011-10-16 Thread Micheal Butz
Hi, Does anyone know if the SRB routine SRBEPA has to reside in common thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO Se

SRB routine

2011-10-16 Thread Micheal Butz
Hi, Would anyone know if the SRB routine SRBEPA has to reside in common thanks -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO Sear

Re: SRBEPA

2011-10-16 Thread Micheal Butz
So if I have a piece of code in my pgm E.G. RTN000 I can point at EPA to it E.G LA R3,RTN000 ST R3,SRBEPA And set SRBASCB to a different address space Sent from my iPhone On Oct 16, 2011, at 7:35 AM, Binyamin Dissen wrote: > On Sun, 16 Oct 2011 07:09:07 -0400 Micheal Butz >

Re: SRBEPA

2011-10-16 Thread Micheal Butz
Thats what I thought there was a Document XMEM for beginners which said both the SRB and SRB rtn EPA have to be in common Sent from my iPhone On Oct 16, 2011, at 6:46 AM, Tom Harper wrote: > Michael, > > No, it does not. > > Tom > > > - Original Message --

SRBEPA

2011-10-16 Thread Micheal Butz
Does anyone know if the SRB rtn has to live common Thanks in advance Sent from my iPhone -- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@bama.ua.edu with the message: GET IBM-MAIN INFO

SRB code

2011-10-12 Thread Micheal Butz
Hi. I know you can'nt issue SVC from a. SRB however PC rtn's are allowed My question is can that PC rtn issue a SVC Thanks Sent from my iPhone -- For IBM-MAIN subscribe / signoff / archive access instructions, send email t

Clarification of Sysevent

2011-10-10 Thread Micheal Butz
Hi, The following is a description from SYSEVENT ENTRY=SVC for the following SYSEVENTs: DONTSWAP OKSWAP TRANSWAP STGTEST REQA

SRB code

2011-10-10 Thread Micheal Butz
Hi, I have piece of code that I am running in my program as a SRB the question I have is the following the The addressability to this piece of code is that by the base register established at entry to this program or the code gets control at SRBEPA has the entry point pointed to by R1

Re: TSO TEST Debugging with TPUT and input paramters

2011-10-06 Thread Micheal Butz
: TSO TEST Debugging with TPUT and input paramters On 6 October 2011 17:29, Micheal Butz wrote: > When entering the command paramters are they surrounded by quotes Generally, no. But you have to enter what the command is expecting, and it's possible that it wants a quoted string. Are you sure

Re: TSO TEST Debugging with TPUT and input paramters

2011-10-06 Thread Micheal Butz
command is written to TSO command processor standards, it > processes the parameters passed to it. > > The CP parameters are passed differently than the parms for an ordinary > program. > > > -Original Message- > From: IBM Mainframe Discussion List [mailto:IBM-

TSO TEST Debugging with TPUT and input paramters

2011-10-06 Thread Micheal Butz
Hi I have a program I am trying to debug that issues TPUTS so I have to use the CP parm however it has input paramters and they are not passed when using the CP parm Any help appreciated Thanks Sent from my iPhone -- For IBM

OUCB usage

2011-09-18 Thread Micheal Butz
Hi, The OUCB control Block seems to contain information about Virtual storage swapping. Would anybody know if that's per page Of Virtual Storage, meaning ASCBOUCB->OUCB->VITUALSTORAGE PAGE IN THAT AS While if I were to issue a SYSEVENT DONTSWAP macro All pages of Virtual Storage i

IFCID Distributed data Header

2011-09-11 Thread Micheal Butz
I am looking at a distributed header in memory well the first 2 bytes are the length of the header meaning if there any long names in this header they are encompossed in the length At offset +4 I can see the Requester name for 16 bytes the offset for this field at offset +1c I can see QWHDSVNM

Re: IFCID Product section layout

2011-09-08 Thread Micheal Butz
mpion Worldwide Banking Center of Excellence, IBM +44-7802-245-584 email: martin_pac...@uk.ibm.com Twitter / Facebook IDs: MartinPacker Blog: https://www.ibm.com/developerworks/mydeveloperworks/blogs/MartinPacker From: Micheal Butz To: IBM-MAIN@bama.ua.edu Date: 09/09/2011 00:55 Subject

IFCID Product section layout

2011-09-08 Thread Micheal Butz
I have a question regarding the product section The documentation says that the product section can have may headers seems like there is always a Standard header, but then the other header might also be present (correlation, distributed, cpu) my question is if the other headers are present were wo

Re: SYNCH[X] vs LINK[X]

2011-08-23 Thread Micheal Butz
In a earlier post John Gilmore wrote as long as the copy is refershable reusable the Info is kept in the CDE Sent from my iPhone On Aug 23, 2011, at 2:47 PM, Gerhard Postpischil wrote: On 8/23/2011 1:05 PM, Micheal Butz wrote: If I have a peice of code that was MVCL somewere it can&#x

Re: SYNCH[X] vs LINK[X]

2011-08-23 Thread Micheal Butz
If I have a peice of code that was MVCL somewere it can'nt be the object of synch/synch Sent from my iPhone On Aug 23, 2011, at 12:12 PM, john gilmore wrote: Binyamin Dissen has already made the crucial point: LINK[X] specifies a name (or alias); SYNCH[X] specifies an address. An

Re: SYNC vs LINK

2011-08-23 Thread Micheal Butz
routine). Mike Myers Mentor Services Corporation On 08/23/2011 07:03 AM, Micheal Butz wrote: Does that mean sync doesn't have to be associated with a CDE Sent from my iPhone On Aug 22, 2011, at 11:07 AM, Binyamin Dissen > wrote: On Mon, 22 Aug 2011 08:35:06 -0400 Micheal Butz

Re: SYNC vs LINK

2011-08-23 Thread Micheal Butz
Does that mean sync doesn't have to be associated with a CDE Sent from my iPhone On Aug 22, 2011, at 11:07 AM, Binyamin Dissen > wrote: On Mon, 22 Aug 2011 08:35:06 -0400 Micheal Butz > wrote: :>Would any one the difference between the the SYNCH LINK. Macros both :>transfer

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