On 05/04/2023 17.15, Peter Maydell wrote:
The s390 private runner CI job ubuntu-20.04-s390x-all seems to have
started timing out a lot recently. Here's an example where it passed,
but with only 53 seconds left on the clock before it would have been
killed:
https://gitlab.com/qemu-project/qemu/-/
06.04.2023 09:48, Thomas Huth пишет:
..>> There's one minor caveat still, though: it is missing in the
"Full list of releases" for whatever reason. Dunno how that
happened, maybe that page hasn't been (re)generated yet.
FWIW, I can see it on https://download.qemu.org/ now.
I still can't, no
On 5/4/23 18:42, Taylor Simpson wrote:
Reducing the number of arguments reduces the overhead of the helper
call
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 4 ++--
target/hexagon/translate.h | 1 +
target/hexagon/op_helper.c | 4 ++--
target/hexagon/translate.c | 10 +
On 06/04/2023 08.33, Michael Tokarev wrote:
06.04.2023 00:06, Michael Roth пишет:
..
Re-packaged tarball based on your 7.2.1 tag is now uploaded:
https://www.qemu.org/download/
Thank you Michael! Finally it's there :)
There's one minor caveat still, though: it is missing in the
"Full lis
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by: Yang Zhong
R
06.04.2023 00:06, Michael Roth пишет:
..
Re-packaged tarball based on your 7.2.1 tag is now uploaded:
https://www.qemu.org/download/
Thank you Michael! Finally it's there :)
There's one minor caveat still, though: it is missing in the
"Full list of releases" for whatever reason. Dunno ho
Ping ...
On Wed, 29 Mar 2023, Ani Sinha wrote:
> i440fx machine versions 2.3 and newer supports dynamic ram
> resizing. See commit a1666142db6233 ("acpi-build: make ROMs RAM blocks
> resizeable") .
> Currently supported all q35 machine types (versions 2.4 and newer) supports
> resizable RAM/ROM
On Wed, 5 Apr 2023, Igor Mammedov wrote:
> with Q35 using ACPI PCI hotplug by default, user's request to unplug
> device is ignored when it's issued before guest OS has been booted.
> And any additional attempt to request device hot-unplug afterwards
> results in following error:
>
> "Device
Paolo Bonzini writes:
> Coroutine commands have to be declared as coroutine_fn, but the
> marker does not show up in the qapi-comands-* headers; likewise, the
> marshaling function calls the command and therefore must be coroutine_fn.
> Static analysis would want coroutine_fn to match between pro
Hello
You are so kind to tell me how can I use qmp to send colon character . I
speak about this character :
I tried:
{"execute":"send-key","arguments":{"keys":[{"type":"qcode","data":"shift-sem
icolon"}]}}
{"execute":"send-key","arguments":{"keys":[{"type":"qcode","data":"shift","d
ata
On Mon, Mar 27, 2023 at 04:03:54PM +0800, Yang, Weijiang wrote:
>
> On 3/27/2023 3:33 PM, Christian Ehrhardt wrote:
> > On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang
> > wrote:
> > >
> > > On 10/26/2022 7:57 PM, Zhong, Yang wrote:
> > > > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO
On Thu, Apr 6, 2023 at 1:02 PM liweiwei wrote:
>
>
> On 2023/4/6 10:24, Alistair Francis wrote:
> > On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
> >>
> >> On 2023/4/6 09:46, Alistair Francis wrote:
> >>> On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
> On 2023/4/6 08:43, Alistair Franci
>-Original Message-
>From: Michael S. Tsirkin
>Sent: Wednesday, April 5, 2023 3:13 AM
>To: Peter Maydell
>Cc: qemu-devel@nongnu.org; Duan, Zhenzhong
>; Peter Xu ; Jason Wang
>; Marcel Apfelbaum
>; Paolo Bonzini ;
>Richard Henderson ; Eduardo Habkost
>; David Hildenbrand ; Philippe
>Mat
On 2023/4/6 10:24, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP wil
On 2023/4/6 10:24, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP wil
On Sat, Mar 25, 2023 at 9:58 PM Richard Henderson
wrote:
>
> From: LIU Zhiwei
>
> Virt enabled state is not a constant. So we should put it into tb flags.
> Thus we can use it like a constant condition at translation phase.
>
> Reported-by: Richard Henderson
> Reviewed-by: Richard Henderson
> S
The translation ratio of host to guest instruction count is one of the
key performance factor of binary translation. TCG doesn't collect host
instruction count at present, it does collect host instruction size
instead, although they are not the same thing as instruction size might
not be fixed, ins
It's only valid when inline=false, otherwise it's default to 0.
Signed-off-by: Fei Wu
---
contrib/plugins/hotblocks.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/contrib/plugins/hotblocks.c b/contrib/plugins/hotblocks.c
index 062200a7a4..c9716da7
The translation ratio of host to guest instruction count is one of the
key performance factor of binary translation. It's better to have this
kind of information exported to plugin for analysis. As the host insn
size is not determined at guest->IR time, its address is recorded for
later dereference
On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
>
>
> On 2023/4/6 09:46, Alistair Francis wrote:
> > On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
> >>
> >> On 2023/4/6 08:43, Alistair Francis wrote:
> >>
> >> On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
> >>
> >> The MPP will be set to t
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
I don't
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
> ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
> device, which happens to be the parent device of every RISC-V cpu.
>
> The result is
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> There is no need to init timers if we're not even sure that our
> extensions are valid. Execute riscv_cpu_validate_set_extensions() before
> riscv_timer_init().
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: LIU Zhiwei
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> Let's remove more code that is open coded in riscv_cpu_realize() and put
> it into a helper. Let's also add an error message instead of just
> asserting out if env->misa_mxl_max != env->misa_mlx.
>
> Signed-off-by: Daniel Henrique
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> We're doing env->priv_spec validation and assignment at the start of
> riscv_cpu_realize(), which is fine, but then we're doing a force disable
> on extensions that aren't compatible with the priv version.
>
> This second step is b
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> All these generic CPUs are using the latest priv available, at this
> moment PRIV_VERSION_1_12_0:
>
> - riscv_any_cpu_init()
> - rv32_base_cpu_init()
> - rv64_base_cpu_init()
> - rv128_base_cpu_init()
>
> Create a new PRIV_VERSION_
On Thu, Mar 30, 2023 at 6:09 AM Daniel Henrique Barboza
wrote:
>
> The setter is doing nothing special. Just set env->priv_ver directly.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: LIU Zhiwei
> Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv
On Thu, Mar 30, 2023 at 6:09 AM Daniel Henrique Barboza
wrote:
>
> This setter is doing nothing else but setting env->vext_ver. Assign the
> value directly.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: LIU Zhiwei
> Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Alistair
>
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> The RVV verification will error out if fails and it's being done at the
> end of riscv_cpu_validate_set_extensions(), after we've already set some
> extensions that are dependent on RVV. Let's put it in its own function
> and do i
On Sun, Mar 12, 2023 at 10:07 PM Yi Chen wrote:
>
> - Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
> - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
> - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
> - Raise RISCV_EXCP_VIRT_INSTRUC
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
>
>
> On 2023/4/6 08:43, Alistair Francis wrote:
>
> On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
>
> The MPP will be set to the least-privileged supported mode (U if
> U-mode is implemented, else M).
>
> I don't think this is right, the spec i
On 2023/4/6 09:26, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
mstatus.MPP field is a WARL field, so we remain it unchanged if an
Only since version 1.11 of the priv spec and we do still support priv 1.10.
I think it's ok to make this change for all priv versio
On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
>
> ACT tests play an important role in riscv tests. This patch tries to
> add related support to run ACT tests.
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-act-upstream-v2
>
> The ACT tests can be run on qemu-sys
On Thu, Apr 6, 2023 at 11:02 AM liweiwei wrote:
>
>
> On 2023/4/6 08:36, Alistair Francis wrote:
> > On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
> >> Add signature and signature-granularity properties in spike to specify the
> >> target
> >> signatrue file and the line size for signature dat
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
>
> mstatus.MPP field is a WARL field, so we remain it unchanged if an
Only since version 1.11 of the priv spec and we do still support priv 1.10.
I think it's ok to make this change for all priv versions, as it won't
break any software running 1
On 2023/4/6 08:36, Alistair Francis wrote:
On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
Add signature and signature-granularity properties in spike to specify the
target
signatrue file and the line size for signature data.
Recgonize the signature section between begin_signature and end_s
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
I don't think this is right, the spec in section 8.6.4 says this:
Sorry, I didn't find this section i
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
>
> The MPP will be set to the least-privileged supported mode (U if
> U-mode is implemented, else M).
I don't think this is right, the spec in section 8.6.4 says this:
"MRET then in mstatus/mstatush sets MPV=0, MPP=0,
MIE=MPIE, and MPIE=1"
So i
On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
>
> Add signature and signature-granularity properties in spike to specify the
> target
> signatrue file and the line size for signature data.
>
> Recgonize the signature section between begin_signature and end_signature
> symbols
> when loading el
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This new version has a new patch (3) that removes the 'multi_letter'
> attribute from isa_ext_data that became redundant after the changes made
> in patch 2. The change was proposed by Weiwei Li in the v2.
>
> All patches b
On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
wrote:
>
> The function is now a no-op for all cpu_init() callers that are setting
> a non-zero misa value in set_misa(), since it's no longer used to sync
> cpu->cfg props with env->misa_ext bits. Remove it in those cases.
>
> While we're at
Hi all,
This series adds a couple QOM properties for retrieving and setting pin
state via qom-get and qom-get.
We ran into a situation in multi-SoC simulation where the BMC would need
to update its input pin state based on behavior from the other SoC. It
made the most sense to expose this over QM
In cases where the input pin is driven by an entity outside of the
machine, such as a machine the BMC is managing, we need a way to
update the pin state when the external machine drives it.
This allows us to do it via QMP.
For example, to set pin 20 on GPIO controller 0:
{"execute":"qom-set","argu
This goes along with input pin modification. In some cases it's easier
to know the state of all pins on the GPIO controller before modifying
input pins, rather than knowing only the state of input pins.
For example over QMP:
{"execute":"qom-get","arguments":{
"path":"/machine/soc/gpio[0]",
On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
wrote:
>
> We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
> the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
> property, remove the old "g" property, remove all instances of 'cfg.ext_g'
> and us
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> This CPU is enabling G via cfg.ext_g and, at the same time, setting
> IMAFD in set_misa() and cfg.ext_icsr.
>
> riscv_cpu_validate_set_extensions() is already doing that, so there's no
> need for cpu_init() setups to worry about se
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> This function was created to move the sync between cpu->cfg.ext_N bit
> changes to env->misa_ext* from the validation step to an ealier step,
> giving us a guarantee that we could use either cpu->cfg.ext_N or
> riscv_has_ext(env,N)
On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
wrote:
>
> Create a new "v" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
> replaced with riscv_has_ext(env, RVV).
>
> Remove the old "v" property and 'ext_v' from RISCV
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> Create a new "j" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
> replaced with riscv_has_ext(env, RVJ).
>
> Remove the old "j" property and 'ext_j' from RISCV
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> Create a new "h" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
> replaced with riscv_has_ext(env, RVH).
>
> Remove the old "h" property and 'ext_h' from RISCV
On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
wrote:
>
> Create a new "u" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
> replaced with riscv_has_ext(env, RVU).
>
> Remove the old "u" property and 'ext_u' from RISCV
On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
wrote:
>
> Create a new "s" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are
> replaced with riscv_has_ext(env, RVS).
>
> Remove the old "s" property and 'ext_s' from RISCV
On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
wrote:
>
> Create a new "m" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
> replaced with riscv_has_ext(env, RVM).
>
> Remove the old "m" property and 'ext_m' from RISCV
On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
wrote:
>
> Create a new "e" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
> replaced with riscv_has_ext(env, RVE).
>
> Remove the old "e" property and 'ext_e' from RISCV
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> Create a new "i" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are
> replaced with riscv_has_ext(env, RVI).
>
> Remove the old "i" property and 'ext_i' from RISCV
On Thu, Mar 30, 2023 at 3:30 AM Daniel Henrique Barboza
wrote:
>
> Create a new "f" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
> replaced with riscv_has_ext(env, RVF).
>
> Remove the old "f" property and 'ext_f' from RISCV
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> Create a new "d" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
> replaced with riscv_has_ext(env, RVD).
>
> Remove the old "d" property and 'ext_d' from RISCV
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> Create a new "c" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
> replaced with riscv_has_ext(env, RVC).
>
> Remove the old "c" property and 'ext_c' from RISCV
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> Create a new "a" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
> replaced with riscv_has_ext(env, RVA).
>
> Remove the old "a" property and 'ext_a' from RISCV
On Thu, Mar 30, 2023 at 3:29 AM Daniel Henrique Barboza
wrote:
>
> Ever since RISCVCPUConfig got introduced users are able to set CPU extensions
> in the command line. User settings are reflected in the cpu->cfg object
> for later use. These properties are used in the target/riscv/cpu.c code,
> mo
On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
wrote:
>
> We don't have MISA extensions in isa_edata_arr[] anymore. Remove the
> redundant 'multi_letter' field from isa_ext_data.
>
> Suggested-by: Weiwei Li
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alista
On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
wrote:
>
> The code that disables extensions if there's a priv version mismatch
> uses cpu->cfg.ext_N properties to do its job.
>
> We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
> the MISA related verifications in a ne
On Thu, Mar 30, 2023 at 3:29 AM Daniel Henrique Barboza
wrote:
>
> When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N
> properties updated. The same can't be said about env->misa_ext*, since
> the user might enable/disable MISA extensions in the command line, and
> env->misa_e
On Wed, Apr 5, 2023 at 6:59 PM Weiwei Li wrote:
>
> This patchset tries to simplify the RVH related check and fix some code style
> problems, such as problems for indentation, multi-line comments and lines
> with over 80 characters.
>
> The port is available here:
> https://github.com/plctlab/pl
On 4/5/23 14:09, Mark Cave-Ayland wrote:
I can certainly give this an R-B, however I'm fairly sure I tried this a couple of years
back and found that it introduced random hangs on qemu-system-sparc64 :/. Have you seen
any issues in the relevant avocado tests with this patch applied?
No issues.
Thanks for reviewing these patches!
"Kirill A. Shutemov" writes:
On Fri, Mar 31, 2023 at 11:50:39PM +, Ackerley Tng wrote:
...
+static int restrictedmem_create_on_user_mount(int mount_fd)
+{
+ int ret;
+ struct fd f;
+ struct vfsmount *mnt;
+
+ f = fdget_raw
Thanks for your review!
David Hildenbrand writes:
On 01.04.23 01:50, Ackerley Tng wrote:
...
diff --git a/include/uapi/linux/restrictedmem.h
b/include/uapi/linux/restrictedmem.h
new file mode 100644
index ..22d6f2285f6d
--- /dev/null
+++ b/include/uapi/linux/restrictedmem
On 4/5/23 11:30, Taylor Simpson wrote:
Remove the following macros (remnants of the old generator design)
READ_REG
READ_PREG
WRITE_RREG
WRITE_PREG
Modify macros that rely on the above
The following are unused
READ_IREG
fGET_FIELD
fSET_FIELD
fREAD_P3
f
On 4/5/23 09:42, Taylor Simpson wrote:
The following instructions are overriden
S2_ct0Count trailing zeros
S2_ct1Count trailing ones
S2_ct0p Count trailing zeros (register pair)
S2_ct1p Count trailing ones (register pair)
These inst
On 4/5/23 03:08, Philippe Mathieu-Daudé wrote:
Remove unused KVM/Aarch32 definitions.
Philippe Mathieu-Daudé (2):
target/arm: Remove KVM AArch32 CPU definitions
hw/arm/virt: Restrict Cortex-A7 check to TCG
target/arm/kvm-consts.h | 9 +++--
hw/arm/virt.c | 2 ++
target/a
Thanks again for your review!
Christian Brauner writes:
On Tue, Apr 04, 2023 at 03:53:13PM +0200, Christian Brauner wrote:
On Fri, Mar 31, 2023 at 11:50:39PM +, Ackerley Tng wrote:
>
> ...
>
> -SYSCALL_DEFINE1(memfd_restricted, unsigned int, flags)
> +static int restrictedmem_create(struc
From: Stacey Son
Implement do_sysctl_kern_proc_filedesc. This pulls kern.proc.filedesc
out of the host kernel and converts it to the guest's format.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 193 ++
bsd-user/qemu.h
From: Stacey Son
Implement do_sysctl_kern_proc_vmmap. This pulls kern.proc.vmmap out of
the host kernel and converts it to the guest's format.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 115 ++
bsd-user/qemu.h
This series is a number of misc cleanups.
First, this replaces my plans to remove netbsd and openbsd code entirely. I've
been in contact with the NetBSD folks that would like to make things work. The
plan is that I'll not remove it in qemu-project, and restore them in bsd-user
fork. These changes
Move the include of the system calls to os-syscall.h. Include that from
syscall_defs.h. Use target_time_t and target_suseconds_t instead of the
variant that has _freebsd_ in the name. Define these for OpenBSD and
NetBSD based on comments in the file.
Signed-off-by: Warner Losh
---
bsd-user/freeb
When a system call returns ENOSYS, send a SIGSYS to the process (to
generate a core dump).
Signed-off-by: Warner Losh
---
bsd-user/arm/target_arch_cpu.h | 8
1 file changed, 8 insertions(+)
diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index 517d0087644..
On BSD, all architectures have the same mmap flags. Since we don't
translate the flags, we don't need these defines here. We can't
cross-run different BSD binaries.
Signed-off-by: Warner Losh
---
bsd-user/syscall_defs.h | 36
1 file changed, 36 deletions(-)
From: Stacey Son
Use the recently committed conversion routines to implement all the
kern.proc flavors, except for the full path (the prereqs of which aren't
yet in qemu-project's master branch).
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 35 +
Nothing calls these routines now. In the bsd-user fork, though, they've
moved to openbsd/os-syscall.c, but those aren't ready for upstreaming.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 5 -
bsd-user/strace.c | 25 -
2 files changed, 30 deletions(-)
diff --g
From: Stacey Son
Converts host's rusage to the guest's rusage.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-proc.c | 48
bsd-user/meson.build | 1 +
bsd-user/qemu-bsd.h | 30 +++
3 files changed,
Make these functions public. Due to coming restructuring, we'll need to
call these from *bsd/os-syscall.c. Add declarations to qemu.h.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 20
bsd-user/strace.c | 29 +
2 files changed, 33 insertions(
The only diffs between bsd-user fork and qemu upstream is style. Make
mmap.c pass checkpatch.pl.
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 91 -
1 file changed, 60 insertions(+), 31 deletions(-)
diff --git a/bsd-user/mmap.c b/bsd-user/mmap.
From: Stacey Son
Implement do_sysctl_kern_getprocs to retrieve proc info from the kernel.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 165 +-
bsd-user/qemu.h | 3 +
2 files changed, 167 insertions(+), 1 d
SIGSYS creates a core by default if uncaught. Follow that here. Sort
with the same order as is in the kernel.
Signed-off-by: Warner Losh
---
bsd-user/signal.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index f4e078ee1da
Nothing calls these routines now. In the bsd-user fork, though, they've
moved to netbsd/os-syscall.c, but those aren't ready for upstreaming.
Signed-off-by: Warner Losh
---
bsd-user/qemu.h | 5 -
bsd-user/strace.c | 17 -
2 files changed, 22 deletions(-)
diff --git a/bsd-
From: Stacey Son
Bring in the code that was originally copied from linxu-user/elfload.c
and moved to elfcore.c. This code then removed the Linux specific bits,
replacing them with FreeBSD specific bits. The commit history for this
is not at all what we'd like (it was done in one go by sson in
227
MAP_GUARD, MAP_EXCL, and MAP_NOCORE are FreeBSD only. Add back the
ifdefs that I removed in 36d5d891559f (but only these ifdefs, the
rest of the commit is not reverted).
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/bsd-user/mmap.c
Move the system call table, and FreeBSD helper routines out of strace.c.
We do not support multiple BSD-types in one binary, so simplify things
by moving it.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-syscall.c | 19 +++
bsd-user/qemu.h | 5 -
bsd-user/
On 05/04/2023 19:59, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 137bdc5159..47940fd85e 100644
--- a/target/sparc/t
On Wed, Apr 05, 2023 at 01:57:20PM -0500, Michael Roth wrote:
> On Wed, Apr 05, 2023 at 05:16:33PM +0300, Michael Tokarev wrote:
> > 05.04.2023 16:58, Michael Roth wrote:
> > > On Wed, Apr 05, 2023 at 02:54:47PM +0300, Michael Tokarev wrote:
> > > > So let it be, with a delay of about a week.
> > >
On 04/04/2023 15:00, Thomas Huth wrote:
On 05/02/2023 23.12, Mark Cave-Ayland wrote:
On 30/01/2023 20:45, Alex Bennée wrote:
Daniel P. Berrangé writes:
On Mon, Jan 30, 2023 at 11:47:02AM +, Peter Maydell wrote:
On Mon, 30 Jan 2023 at 11:44, Thomas Huth wrote:
Testing 32-bit host OS
On 4/5/23 13:04, Philippe Mathieu-Daudé wrote:
These fields shouldn't be accessed when KVM is not available.
Signed-off-by: Philippe Mathieu-Daudé
---
RFC: The migration part is likely invalid...
kvmtimer_needed() is defined in target/riscv/machine.c as
static bool kvmtimer_needed(void
On Tue, Apr 04, 2023 at 11:32:37PM +0800, Sam Li wrote:
> A zone append command is a write operation that specifies the first
> logical block of a zone as the write position. When writing to a zoned
> block device using zone append, the byte offset of the call may point at
> any position within the
On Tue, Apr 04, 2023 at 11:32:36PM +0800, Sam Li wrote:
> Since Linux doesn't have a user API to issue zone append operations to
> zoned devices from user space, the file-posix driver is modified to add
> zone append emulation using regular writes. To do this, the file-posix
> driver tracks the wp
On 4/5/23 13:04, Philippe Mathieu-Daudé wrote:
The 'kvm_sw_tlb' field shouldn't be accessed when KVM is not available.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/cpu.h| 2 ++
target/ppc/mmu_common.c | 4
2 files changed, 6
On Mon, Mar 20, 2023 at 04:26:10PM +0100, Philippe Mathieu-Daudé wrote:
> Introduce the BdrvDmgUncompressFunc type defintion. To emphasis
> dmg_uncompress_bz2 and dmg_uncompress_lzfse are pointer to functions,
> declare them using this new typedef.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
On Fri, Mar 17, 2023 at 06:50:15PM +0100, Hanna Czenczek wrote:
> RFC:
> https://lists.nongnu.org/archive/html/qemu-block/2023-03/msg00446.html
>
> Thanks for the feedback on the RFC! Sounds like we agree that this is
> the right way to fix the bug.
>
> Here in v1, I’ve followed Vladimir’s sugge
This will facilitate adding additional tests in separate .c files
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.h | 178 ++
tests/tcg/hexagon/hvx_misc.c | 160 +--
tests/tcg/hexagon/Makefile.target | 1 +
3 files chan
On Wed, 5 Apr 2023 at 19:58, Michael Roth wrote:
> One thing I forgot to mention previously is updating the wiki with the
> release schedule once you have an idea of when you plan to push your tags.
On a slight tangent, do you have the process you use for
releases (main as well as stable-branch o
On 4/5/23 05:58, Weiwei Li wrote:
This patchset tries to simplify the RVH related check and fix some code style
problems, such as problems for indentation, multi-line comments and lines with
over 80 characters.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtf
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