On Tue, May 23, 2023 at 7:48 AM Xiang Xiao wrote: > Why not start the test infrastructure from sim/qemu? It's more simple to > set up and has unlimited resources. Once the sim/qemu test workflow is > ready, it isn't very hard to duplicate to the real boards.
Yeah, *:nsh should work that way, and should allow some runtime tests on various architectures that QEMU already provide :-) https://www.qemu.org/docs/master/about/emulation.html Emulation <https://www.qemu.org/docs/master/about/emulation.html#emulation> QEMU’s Tiny Code Generator (TCG) provides the ability to emulate a number of CPU architectures on any supported host platform. Both System Emulation <https://www.qemu.org/docs/master/system/index.html#system-emulation> and User Mode Emulation <https://www.qemu.org/docs/master/user/index.html#user-mode-emulation> are supported depending on the guest architecture. Supported Guest Architectures for Emulation <https://www.qemu.org/docs/master/about/emulation.html#id2> Architecture (qemu name) System User Notes Alpha Yes Yes Legacy 64 bit RISC ISA developed by DEC Arm (arm, aarch64) Yes <https://www.qemu.org/docs/master/system/target-arm.html#arm-system-emulator> Yes Wide range of features, see A-profile CPU architecture support <https://www.qemu.org/docs/master/system/arm/emulation.html#arm-emulation> for details AVR Yes <https://www.qemu.org/docs/master/system/target-avr.html#avr-system-emulator> No 8 bit micro controller, often used in maker projects Cris Yes Yes Embedded RISC chip developed by AXIS Hexagon No Yes Family of DSPs by Qualcomm PA-RISC (hppa) Yes Yes A legacy RISC system used in HP’s old minicomputers x86 (i386, x86_64) Yes <https://www.qemu.org/docs/master/system/target-i386.html#qemu-pc-system-emulator> Yes The ubiquitous desktop PC CPU architecture, 32 and 64 bit. Loongarch Yes Yes A MIPS-like 64bit RISC architecture developed in China m68k Yes <https://www.qemu.org/docs/master/system/target-m68k.html#coldfire-system-emulator> Yes Motorola 68000 variants and ColdFire Microblaze Yes Yes RISC based soft-core by Xilinx MIPS (mips*) Yes <https://www.qemu.org/docs/master/system/target-mips.html#mips-system-emulator> Yes Venerable RISC architecture originally out of Stanford University Nios2 Yes Yes 32 bit embedded soft-core by Altera OpenRISC Yes <https://www.qemu.org/docs/master/system/target-openrisc.html#openrisc-system-emulator> Yes Open source RISC architecture developed by the OpenRISC community Power (ppc, ppc64) Yes <https://www.qemu.org/docs/master/system/target-ppc.html#powerpc-system-emulator> Yes A general purpose RISC architecture now managed by IBM RISC-V Yes <https://www.qemu.org/docs/master/system/target-riscv.html#risc-v-system-emulator> Yes An open standard RISC ISA maintained by RISC-V International RX Yes <https://www.qemu.org/docs/master/system/target-rx.html#rx-system-emulator> No A 32 bit micro controller developed by Renesas s390x Yes <https://www.qemu.org/docs/master/system/target-s390x.html#s390x-system-emulator> Yes A 64 bit CPU found in IBM’s System Z mainframes sh4 Yes Yes A 32 bit RISC embedded CPU developed by Hitachi SPARC (sparc, sparc64) Yes <https://www.qemu.org/docs/master/system/target-sparc.html#sparc32-system-emulator> Yes A RISC ISA originally developed by Sun Microsystems Tricore Yes No A 32 bit RISC/uController/DSP developed by Infineon Xtensa Yes <https://www.qemu.org/docs/master/system/target-xtensa.html#xtensa-system-emulator> Yes A configurable 32 bit soft core now owned by Cadence A number of features are only available when running under emulation including Record/Replay <https://www.qemu.org/docs/master/system/replay.html#replay> and QEMU TCG Plugins <https://www.qemu.org/docs/master/devel/tcg-plugins.html#tcg-plugins>. Semihosting <https://www.qemu.org/docs/master/about/emulation.html#semihosting> Semihosting is a feature defined by the owner of the architecture to allow programs to interact with a debugging host system. On real hardware this is usually provided by an In-circuit emulator (ICE) hooked directly to the board. QEMU’s implementation allows for semihosting calls to be passed to the host system or via the gdbstub. Generally semihosting makes it easier to bring up low level code before a more fully functional operating system has been enabled. On QEMU it also allows for embedded micro-controller code which typically doesn’t have a full libc to be run as “bare-metal” code under QEMU’s user-mode emulation. It is also useful for writing test cases and indeed a number of compiler suites as well as QEMU itself use semihosting calls to exit test code while reporting the success state. Semihosting is only available using TCG emulation. This is because the instructions to trigger a semihosting call are typically reserved causing most hypervisors to trap and fault on them. Espressif adds their MCU support to qemu, they just added ESP32-C3 (RISC-V) :-) https://github.com/espressif/qemu/releases/tag/esp-develop-8.0.0-20230522 -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
