[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[gkm at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #4 from Greg McGary <gkm at rivosinc dot com> ---
Here is a smaller testcase:

typedef struct {
  int A[6];
  float b[];
} a;
int b(a *a) {
  int b = 0;
  for (; b < 3; b++) {
    a->A[2 * b] = a->b[b] - b + a->A[2 * b];
    a->A[2 * b + 1] = b * a->A[2 * b + 1];
  }
  return 0;
}

... which generates this ...

b:
.LFB0:
        .cfi_startproc
        lui     a5,%hi(.LC1)
        addi    a5,a5,%lo(.LC1)
        vsetivli        zero,16,e8,mf2,ta,ma
        vlm.v   v0,0(a5)
        addi    a3,a0,64
        vsetivli        zero,0,e32,m2,ta,ma
        vle32.v v12,0(a3)                   <--- VL=0, nop
        vsetivli        zero,6,e32,m2,ta,ma
        vle32.v v10,0(a0)

. . .

        vsetivli        zero,6,e32,m2,ta,ma
        vse32.v v8,0(a4)
        vsetivli        zero,0,e32,m2,ta,ma
        vse32.v v4,0(a3)                   <--- VL=0, nop
        ret