[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[gkm at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #5 from Greg McGary <gkm at rivosinc dot com> ---
I am seeing gimple pass cunroll emit MASK_LEN_LOAD calls with length zero.
These survive all the way to the end and are emitted to assembler output as
VL=0 vector ops, which are no-ops. Where is the proper place to remove these as
dead code?