[Bug target/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #2 from Robin Dapp <rdapp at gcc dot gnu.org> ---
At first sight it looks like dse just doesn't handle the constant-zero length
case separately and tries aliasing analysis nevertheless, thinking the store is
live.  I think we can still fix this in stage 3, now that we have the PR.