Re: [PATCH 12/17] target/ppc: Split the ISA 2.05 instruction feature group

Tue, 13 Oct 2026 00:34:58 -0700 


On 10/6/26 15:19, Bin Meng wrote:

The ISA 2.05 flag couples integer instructions to floating-point
instructions and extended FPSCR access. The e5500 and e6500 implement
cmpb and parity instructions but lack these floating-point features,
so enabling the entire group cannot describe their hardware.

Give byte comparison, parity, copy sign, integer word loads, paired
floating-point transfers and extended FPSCR access separate flags.
Keep the existing capabilities of POWER7 and later models, and include
all new flags in the TCG supported instruction mask.

Signed-off-by: Bin Meng <[email protected]>
---

  target/ppc/cpu.h                           | 20 ++++++++++++++++----
  target/ppc/cpu_init.h                      |  5 ++++-
  target/ppc/cpu_init.c                      | 10 ++++++++--
  target/ppc/translate.c                     | 10 ++++++----
  target/ppc/translate/fixedpoint-impl.c.inc |  6 +++---
  target/ppc/translate/fp-impl.c.inc         |  8 ++++----
  target/ppc/translate/fp-ops.c.inc          |  9 ++++++---
  7 files changed, 47 insertions(+), 21 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b716ccf540..78fa4653fb 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2568,8 +2568,8 @@ enum {
      PPC2_PRCNTL        = 0x0000000000000008ULL,
      /* Byte-reversed, indexed, double-word load and store                    
*/
      PPC2_DBRX          = 0x0000000000000010ULL,
-    /* Book I 2.05 PowerPC specification                                     */
-    PPC2_ISA205        = 0x0000000000000020ULL,
+    /* ISA 2.05 cmpb */
+    PPC2_CMPB_ISA205   = 0x0000000000000020ULL,
      /* POWER ISA 2.07                                                        
*/
      PPC2_ISA207        = 0x0000000000000040ULL,
      /* ISA 2.06B bpermd                                                      
*/
@@ -2602,15 +2602,27 @@ enum {
      PPC2_PPE42X        = 0x0000000000100000ULL,
      /* PPE42XM instructions                                                  
*/
      PPC2_PPE42XM       = 0x0000000000200000ULL,
+    /* ISA 2.05 prtyw and prtyd */
+    PPC2_PRTY_ISA205   = 0x0000000000800000ULL,

Hey,

You have skipped a bit in the flag here. PPC2_PRTY_ISA205 flag should 
be  0x0000000000400000ULL instead of 0x0000000000800000ULL.

+    /* ISA 2.05 fcpsgn */
+    PPC2_FCPSGN_ISA205 = 0x0000000001000000ULL,
+    /* ISA 2.05 lfiwax */
+    PPC2_LFIWAX_ISA205 = 0x0000000002000000ULL,
+    /* ISA 2.05 floating-point pair loads and stores */
+    PPC2_FP_PAIR_ISA205 = 0x0000000004000000ULL,
+    /* ISA 2.05 FPSCR access through the W and L fields */
+    PPC2_FPSCR_EXT_ISA205 = 0x0000000008000000ULL,

Please keep the '=' sign in the flag definitions aligned so as to help 
prevent error as the one pointed out above.

While we are at it, please keep the comment end '*/' aligned as well.

Thanks,
Chinmay

  
  #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \

-                        PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
+                        PPC2_CMPB_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
                          PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
                          PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_DFP | \
                          PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
                          PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
                          PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \
-                        PPC2_PPE42XM)
+                        PPC2_PPE42XM | PPC2_PRTY_ISA205 | \
+                        PPC2_FCPSGN_ISA205 | PPC2_LFIWAX_ISA205 | \
+                        PPC2_FP_PAIR_ISA205 | PPC2_FPSCR_EXT_ISA205)
  };

  
  /*****************************************************************************/

diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h
index 4ba559d8af..e70f1baa74 100644
--- a/target/ppc/cpu_init.h
+++ b/target/ppc/cpu_init.h
@@ -17,7 +17,10 @@
  #define PPC_INSNS_FLAGS2_POWER_COMMON                                \
      (PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |                 \
       PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 |      \
-     PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 |         \
+     PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 |                       \
+     PPC2_CMPB_ISA205 | PPC2_PRTY_ISA205 |                          \
+     PPC2_FCPSGN_ISA205 | PPC2_LFIWAX_ISA205 |                      \
+     PPC2_FP_PAIR_ISA205 | PPC2_FPSCR_EXT_ISA205 |                   \
       PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL |                   \
       PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206)

  
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c

index 5077f3300e..f2a342b076 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6220,7 +6220,10 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, const void *data)
                         PPC_SEGMENT_64B | PPC_SLBI |
                         PPC_POPCNTB | PPC_POPCNTWD |
                         PPC_CILDST;
-    pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
+    pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX |
+                        PPC2_CMPB_ISA205 | PPC2_PRTY_ISA205 |
+                        PPC2_FCPSGN_ISA205 | PPC2_LFIWAX_ISA205 |
+                        PPC2_FP_PAIR_ISA205 | PPC2_FPSCR_EXT_ISA205 |
                          PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
                          PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
                          PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
@@ -6381,7 +6384,10 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
      pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
                          PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
                          PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
-                        PPC2_FP_TST_ISA206 | PPC2_ISA205 | PPC2_FP_CVT_S64 |
+                        PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
+                        PPC2_CMPB_ISA205 | PPC2_PRTY_ISA205 |
+                        PPC2_FCPSGN_ISA205 | PPC2_LFIWAX_ISA205 |
+                        PPC2_FP_PAIR_ISA205 | PPC2_FPSCR_EXT_ISA205 |
                          PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
                          PPC2_BCDA_ISA206;
      pcc->msr_mask = (1ull << MSR_SF) |
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 467b8f3d4e..c00581fc36 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4403,7 +4403,7 @@ static bool trans_ICBIEP(DisasContext *ctx, arg_X_ea *a)
  static void gen_dform39(DisasContext *ctx)
  {
      if ((ctx->opcode & 0x3) == 0) {
-        if (ctx->insns_flags2 & PPC2_ISA205) {
+        if (ctx->insns_flags2 & PPC2_FP_PAIR_ISA205) {
              return gen_lfdp(ctx);
          }
      }
@@ -4415,7 +4415,7 @@ static void gen_dform3D(DisasContext *ctx)
  {
      if ((ctx->opcode & 3) == 0) { /* DS-FORM */
          /* stfdp */
-        if (ctx->insns_flags2 & PPC2_ISA205) {
+        if (ctx->insns_flags2 & PPC2_FP_PAIR_ISA205) {
              return gen_stfdp(ctx);
          }
      }
@@ -4429,9 +4429,11 @@ GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, 
PPC_NONE, PPC2_ISA300),
  GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
  GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
  /* handles lfdp, lxsd, lxssp */
-GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000,
+              PPC_NONE, PPC2_FP_PAIR_ISA205),
  /* handles stfdp, stxsd, stxssp */
-GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000,
+              PPC_NONE, PPC2_FP_PAIR_ISA205),
  GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
  GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
  GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc 
b/target/ppc/translate/fixedpoint-impl.c.inc
index c3d8bbf267..0c6ec91400 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -1545,7 +1545,7 @@ static bool trans_XOR(DisasContext *ctx, arg_XOR *a)

  
  static bool trans_CMPB(DisasContext *ctx, arg_CMPB *a)

  {
-    REQUIRE_INSNS_FLAGS2(ctx, ISA205);
+    REQUIRE_INSNS_FLAGS2(ctx, CMPB_ISA205);
      gen_helper_CMPB(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
      return true;
  }
@@ -1636,7 +1636,7 @@ static bool trans_PRTYW(DisasContext *ctx, arg_PRTYW *a)
      TCGv rs = cpu_gpr[a->rs];
      TCGv t0 = tcg_temp_new();

  
-    REQUIRE_INSNS_FLAGS2(ctx, ISA205);

+    REQUIRE_INSNS_FLAGS2(ctx, PRTY_ISA205);
      tcg_gen_shri_tl(t0, rs, 16);
      tcg_gen_xor_tl(ra, rs, t0);
      tcg_gen_shri_tl(t0, ra, 8);
@@ -1652,7 +1652,7 @@ static bool trans_PRTYD(DisasContext *ctx, arg_PRTYD *a)
      TCGv t0 = tcg_temp_new();

  
      REQUIRE_64BIT(ctx);

-    REQUIRE_INSNS_FLAGS2(ctx, ISA205);
+    REQUIRE_INSNS_FLAGS2(ctx, PRTY_ISA205);
      tcg_gen_shri_tl(t0, rs, 32);
      tcg_gen_xor_tl(ra, rs, t0);
      tcg_gen_shri_tl(t0, ra, 16);
diff --git a/target/ppc/translate/fp-impl.c.inc 
b/target/ppc/translate/fp-impl.c.inc
index e0d9fa2e24..fef770368a 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -324,7 +324,7 @@ TRANS(FNABS, do_move_b, 1ULL << 63, tcg_gen_ori_i64);
  static bool trans_FCPSGN(DisasContext *ctx, arg_FCPSGN *a)
  {
      TCGv_i64 t0, t1, t2;
-    REQUIRE_INSNS_FLAGS2(ctx, ISA205);
+    REQUIRE_INSNS_FLAGS2(ctx, FCPSGN_ISA205);
      REQUIRE_FPU(ctx);
      t0 = tcg_temp_new_i64();
      t1 = tcg_temp_new_i64();
@@ -592,13 +592,13 @@ static void gen_mtfsf(DisasContext *ctx)
      flm = FPFLM(ctx->opcode);
      l = FPL(ctx->opcode);
      w = FPW(ctx->opcode);
-    if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
+    if (unlikely(w & !(ctx->insns_flags2 & PPC2_FPSCR_EXT_ISA205))) {
          gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
          return;
      }
      if (!l) {
          t0 = tcg_constant_i32(flm << (w * 8));
-    } else if (ctx->insns_flags2 & PPC2_ISA205) {
+    } else if (ctx->insns_flags2 & PPC2_FPSCR_EXT_ISA205) {
          t0 = tcg_constant_i32(0xffff);
      } else {
          t0 = tcg_constant_i32(0xff);
@@ -627,7 +627,7 @@ static void gen_mtfsfi(DisasContext *ctx)
      }
      w = FPW(ctx->opcode);
      bf = FPBF(ctx->opcode);
-    if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
+    if (unlikely(w & !(ctx->insns_flags2 & PPC2_FPSCR_EXT_ISA205))) {
          gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
          return;
      }
diff --git a/target/ppc/translate/fp-ops.c.inc 
b/target/ppc/translate/fp-ops.c.inc
index 9bc9c3a3c3..e6a0d88dd4 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -1,14 +1,17 @@
  GEN_HANDLER_E(lfdepx, 0x1F, 0x1F, 0x12, 0x00000001, PPC_NONE, PPC2_BOOKE206),
-GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001,
+              PPC_NONE, PPC2_LFIWAX_ISA205),
  GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001,
+              PPC_NONE, PPC2_FP_PAIR_ISA205),

  
  #define GEN_STXF(name, stop, opc2, opc3, type)                                \

  GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),

  
  GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)

  GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206),
-GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001,
+              PPC_NONE, PPC2_FP_PAIR_ISA205),

  
  GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),

  GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),

























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