Where are the and characters? Read the example he gave.
- Original Message -
From: Jose Flores jflo...@gtsoftware.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Tuesday, December 09, 2014 9:32 AM
Subject: Re: Assembly of G-Type constants not working for me
Doesn't like it!
I edited
From: Paul Gilmartin 0014e0e4a59b-dmarc-requ...@listserv.uga.edu
Sent: Friday, November 28, 2014 4:25 AM
On 2014-11-26, at 18:16, John Ehrman wrote:
Micheal, Could you write DS 0CL(11*133) ?
I had thought length was limited to 256 (SS instruuction count or
control block field?),
From: Rzepka, Michael michael.rze...@commerzbank.com
Sent: Monday, November 17, 2014 8:34 PM
https://archive.org/details/bitsavers_ibm360refeystem360ReferenceData_662124
ibm :: 360 :: referenceCard :: GX20-1703-9 System360 Reference Data
Looks like the S/360 Reference card, not for the
From: zMan zedgarhoo...@gmail.com
Sent: Sunday, November 16, 2014 11:16 AM
If Adobe PDF wasn't such a crappy format, it would be easy to program it to
filter those grafs so you could select just the grande instructions (or
whatever), the number of columns, etc. In the meanwhile, great example!
From: John Ehrman ehr...@us.ibm.com
Sent: Friday, November 14, 2014 11:30 AM
Robin Vowels noted:
CVB and CVD have always been part of the fixed-point instruction
set (the basic set), and are not part of the decimal set.
That's what my antique Green Card says!
And so it has been since
From: DASDBILL2 dasdbi...@comcast.net
Sent: Saturday, November 15, 2014 2:03 AM
Eons ago, the decimal and floating point instruction sets, inter alia, were provided only for an
extra fee.
Except that the model 44 had the floating point instructions as standard.
The smaller models had only
From: Gary Weinhold weinh...@dkl.com
Sent: Saturday, November 15, 2014 2:33 AM
I have heard that only one machine was ever delivered without the
decimal set, but it may have just been rumour.
I know of at least one S/360 Model 30 that didn't have decimal instructions.
From: fred.van.der.wi...@mail.ing.nl
Sent: Saturday, November 15, 2014 5:34 AM
Could't agreement more: the two columns are a nightmare. They may have just fine in the printed
edition 20 years ago but they are no good in an electronic version...
I'm puzzled by the strong reactions this thread
From: glen herrmannsfeldt g...@ugcs.caltech.edu
Sent: Saturday, November 15, 2014 3:31 AM
Gary wrote:
I have heard that only one machine was ever delivered without the
decimal set, but it may have just been rumour.
All the 360/91's were delivered without the decimal instructions.
The OS
From: Tom Marchant 00a69b48f3bb-dmarc-requ...@listserv.uga.edu
Sent: Friday, November 14, 2014 2:11 AM
CVD is part of the Decimal Feature.
CVB and CVD have always been part of the fixed-point instruction set
(the basic set), and are not part of the decimal set.
That may not be important
From: Steve Hobson steve_hob...@uk.ibm.com
Sent: Tuesday, August 05, 2014 11:04 PM
As a counter example,I have actually seen:
NRx,=F'16777215'
For a masking operation, hex would be the automatic choice.
From: Frank M. Ramaekers framaek...@ailife.com
Sent: Wednesday, July 16, 2014 10:46 PM
Please excuse my inexperience, I need an EDIT mask for a floating minus
sign.
Value (hex)ED/EDMK
00123C 123
00123D -123
1C 1
1D -1
Sequence could be:
LA 1, Pattern+L'Pattern-1
The MVI should be MVI 0(1),'-' of course.
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From: Steve Comstock st...@trainersfriend.com
Sent: Wednesday, July 16, 2014 11:10 PM
There is no pattern that will do that simply: it takes some
code. Given your input looks like three bytes packed, lets
set up some fields:
Data_in ds PL3
Data_out ds CL7
Edpatdc x'40202020202060'
A typo: the MVI should read:
MVIDATA_OUT+6,' '
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, 2014 7:19 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: MVCL
On 5/21/2014 8:14 AM, Robin Vowels wrote:
From: Steve Hobson steve_hob...@uk.ibm.com
Sent: Wednesday, May 21, 2014 9:38 PM
For many years I've used this style which I was taught be the
legendary Pete Roberts:
MVC
From: Steve Hobson steve_hob...@uk.ibm.com
Sent: Wednesday, June 04, 2014 8:38 PM
I remember a fastest way to clear a register discussion on a BBS at
least twenty years ago.
After a while someone suggested looking for the slowest instead.
BCTG Ri,* is relatively slow, especially when Ri is
From: Rob van der Heij rvdh...@gmail.com
Sent: Tuesday, June 03, 2014 4:14 PM
On 3 June 2014 01:56, Robin Vowels robi...@dodo.com.au wrote:
XR Rn,Rn is faster than SR.
But does it matter?
Such an instruction should be executed only once, and once only.
It shouldn't be in the loop.
So why
From: Tony Harminc t...@harminc.com
Sent: Tuesday, June 03, 2014 11:52 AM
On 2 June 2014 20:14, Robin Vowels robi...@dodo.com.au wrote:
From: Rob van der Heij rvdh...@gmail.com
Sent: Tuesday, June 03, 2014 1:00 AM
My simplistic implementation was like this (for each byte, so wrapped
From: Tony Harminc t...@harminc.com
Sent: Tuesday, June 03, 2014 11:42 AM
On 2 June 2014 19:56, Robin Vowels robi...@dodo.com.au wrote:
From: Tony Harminc t...@harminc.com
Sent: Tuesday, June 03, 2014 3:30 AM
Is LHI Rn,0 faster than SR Rn,Rn? I'd expect them to be the same, but
SR is half
- Original Message -
From: Rob van der Heij rvdh...@gmail.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Tuesday, June 03, 2014 6:58 PM
Subject: Re: Out of Order and Superscalar - small experiment
On 3 June 2014 09:19, Robin Vowels robi...@dodo.com.au wrote:
On 2 June 2014 19:56
From: Rob van der Heij rvdh...@gmail.com
Sent: Tuesday, June 03, 2014 3:58 AM
On 2 June 2014 19:30, Tony Harminc t...@harminc.com wrote:
Is LHI Rn,0 faster than SR Rn,Rn? I'd expect them to be the same, but
SR is half the size, and so lessens the amount of i-cache used.
The effect of the
From: Tony Harminc t...@harminc.com
Sent: Tuesday, June 03, 2014 11:52 AM
On 2 June 2014 20:14, Robin Vowels robi...@dodo.com.au wrote:
From: Rob van der Heij rvdh...@gmail.com
Sent: Tuesday, June 03, 2014 1:00 AM
More recently I've been working on porting Linux gcc object code to CMS
- Original Message -
From: Jim Mulder d10j...@us.ibm.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Wednesday, June 04, 2014 3:34 AM
Subject: Re: Out of Order and Superscalar - small experiment
XR Rn,Rn is faster than SR.
But does it matter?
Such an instruction should be executed only
From: Tony Harminc t...@harminc.com
Sent: Tuesday, June 03, 2014 3:30 AM
On 2 June 2014 11:00, Rob van der Heij rvdh...@gmail.com wrote:
The optimized gcc code was more like this (for 3 bytes)
*ICR2,1(R5)LHI R3,0ARR2,R1
ARR0,R1
From: David Stokes sto...@interchip.de
Sent: Monday, May 26, 2014 5:47 PM
Binyamin Dissen wrote:
When it requires a base register is stated, it obviously means a CODE base
register. One wonders how that can be confused.
Why? (It's use of terminology, not confusion). Storage addresses in
From: Binyamin Dissen bdis...@dissensoftware.com
Sent: Monday, May 26, 2014 3:51 PM
When it requires a base register is stated, it obviously means a CODE base
register.
No it doesn't. A base register is a base register.
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From: Steve Hobson steve_hob...@uk.ibm.com
Sent: Wednesday, May 21, 2014 11:31 PM
: MVC TARGET(0),SOURCE
: EX Rx,*-6
: Requires a code base register.
Well, ish:
LARL Ry,*+6
MVC TARGET(0),SOURCE
EX Rx,0(,Ry)
This (MVC)
From: Binyamin Dissen bdis...@dissensoftware.com
Sent: Wednesday, May 21, 2014 10:03 PM
On Wed, 21 May 2014 12:38:09 +0100 Steve Hobson steve_hob...@uk.ibm.com
wrote:
: I tend to use MVCL like Tony does. The reason that I tend to not like
:doing
: a EX of an MVC is because the MVC needs to be
From: Gerhard Postpischil gerha...@charter.net
Sent: Wednesday, May 21, 2014 8:38 AM
On 5/20/2014 11:44 PM, Robin Vowels wrote:
Sounds like overkill.
MVC with EX would be simpler.
It depends very much on the requirement. For example, building a longer
string from several different sources
From: Steve Hobson steve_hob...@uk.ibm.com
Sent: Wednesday, May 21, 2014 9:38 PM
For many years I've used this style which I was taught be the legendary
Pete Roberts:
MVC TARGET(0),SOURCE
EX Rx,*-6
I imagine that
EX Rx,*+4
MVC
From: Tony Harminc t...@harminc.com
Sent: Friday, May 16, 2014 8:44 AM
I use MVCL a lot even for very small moves where the length is not
known at assembly time. But I know my environment and its performance
requirements, and often judge the relative elegance, generality, and
From: Tony Harminc t...@harminc.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Friday, May 16, 2014 8:44 AM
On 15 May 2014 15:00, Blaicher, Christopher Y. cblaic...@syncsort.com wrote:
The problem with TRT is it validates the whole TRT table before it starts to do
the TRT.
I think you are
From: Ed Jaffe edja...@phoenixsoftware.com
Sent: Wednesday, May 21, 2014 2:52 PM
On 5/20/2014 8:44 PM, Robin Vowels wrote:
I use MVCL a lot even for very small moves where the length is not
known at assembly time. But I know my environment and its performance
requirements, and often judge
- Original Message -
From: Tony Harminc t...@harminc.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Sunday, March 02, 2014 5:52 AM
Subject: Re: CamelCase (was: ASSEMBLER-LIST Digest ...)
On 1 March 2014 00:12, Robert A. Rosenberg a...@rarpsl.com wrote:
Making STUFF stuff Stuff sTuff
From: Steve Smith sasd...@gmail.com
Sent: Saturday, March 01, 2014 9:56 AM
English (and other Latin-alphabet languages) is mostly
case-INsensitive. There's sometimes a difference between Bill and bill,
but bILL, BILL, bIlL are just silly versions of the same word.
But iTunes isn't?
From: Paul Gilmartin paulgboul...@aim.com
Sent: Friday, February 21, 2014 5:07 PM
On 2014-02-20, at 20:50, John Gilmore wrote:
The appropriate distinction not bwteeen what may appear in macro and
outside them. It is that between the syntax of the macro language and
'vanilla' assembly
- Original Message -
From: Paul Gilmartin paulgboul...@aim.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Friday, January 10, 2014 2:29 AM
Subject: Re: OT: SI units and precision
On 2014-01-08, at 08:10, Andreas F. Geissbuehler wrote:
I need correcting before the picking starts :)
From: Robert A. Rosenberg a...@rarpsl.com
Sent: Thursday, January 09, 2014 2:37 PM
At 10:56 + on 01/08/2014, Mike Kerford-Byrnes wrote about SI
units and such:
A few years ago I attempted to purchase 225 yards of water pipe from a
plumbing merchant, only to be told (in no uncertain
From: Steve Smith sasd...@gmail.com
Sent: Wednesday, January 08, 2014 9:35 AM
This American colleague personally has no use for the metric system.
It's a completely arbitrary system that has no real advantage over our
ancient and traditional measurements. It makes no more sense than the
From: Rob van der Heij rvdh...@gmail.com
Sent: Saturday, January 04, 2014 11:03 PM
On 3 January 2014 17:26, Ray Mansell r...@mansell.org wrote:
Indeed, my post was intended to be tongue-in-cheek. My British sense of
humour often gets me in trouble here in the US.
They don't have any humour
From: Tony Thigpen t...@vse2pdf.com
Sent: Friday, October 25, 2013 12:16 PM
In XPL, each string is accessed via descriptor that contains in a single
word
the memory address and the length.
Your code is doing a binary search of the FIXED length POINTER table.
No it's not. The code
From: Tony Thigpen t...@vse2pdf.com
Sent: Friday, October 25, 2013 10:05 PM
Convert your PLX code to assembler and you will see that you are binary
searching a pointer table that has fixed length entries.
In PL/I , each string value (= each element of an array) occupies exactly the
same
From: glen herrmannsfeldt g...@ugcs.caltech.edu
Sent: Thursday, October 24, 2013 4:22 PM
From C28-6514-5 on bitsavers, on page 16:
What manual is that; for what system, and what date?
Division by zero is permitted and yields a zero result.
After that, (and presumably also earlier) it has
From: Rob van der Heij rvdh...@gmail.com
Sent: Thursday, October 24, 2013 9:35 PM
Ask someone for a web browser and type google.com ;-) OS assembler
language; 360, and december 1967
I have better things to do than do other people's research.
From: DASDBILL2 dasdbi...@comcast.net
Sent: Thursday, October 24, 2013 10:44 PM
The Assembler language book does not describe how processor instructions work.
Mine does. And most assembler langage books do also.
Processor instructions never have allowed division by zero.
Some early
From: Tony Thigpen t...@vse2pdf.com
Sent: Friday, October 25, 2013 3:45 AM
All entries will be fixed length. Can't really have variable length and
use a binary search. :-)
The code that I posted previously was for variable-length strings.
From: Tony Thigpen t...@vse2pdf.com
Sent: Friday, October 25, 2013 8:43 AM
After a couple of posts about my post, I will go back to my point.
You can only binary search a fixed length table.
Nonsense.
The table for the code that I posted previouisly consisted
of varying-length strings.
If
From: Tony Thigpen t...@vse2pdf.com
Sent: Friday, October 25, 2013 9:14 AM
On 2013-10-24 11:29, Blaicher, Christopher Y. wrote:
...
The second method used a binary chop of the data then scanned for
the next entry. It was ugly, but it did its job. There are lots of
limitations to it.
From: Tony Thigpen t...@vse2pdf.com
Sent: Friday, October 25, 2013 11:35 AM
Repost the code. Nothing I still have in my inbox shows code to perform
a binary search of a table where each row occurrence can be any length.
Array c has lower bound 0, upper bound n:
i = -1; k = n+1; /* pointers
From: Savor, Tom tom.sa...@fisglobal.com
Sent: Friday, October 25, 2013 11:40 AM
Robin,
InterestingI would have said the same thing (if asked), that you can't have
binary search on
variable length keys.
Is your code posted C+ ?? I don't know it at all.
The code is PL/I.
How would you
From: John Gilmore jwgli...@gmail.com
Sent: Tuesday, October 22, 2013 9:31 AM
PL/I was robbed of FIXEDOVERFLOW for binary fixed values.
Use SIZE instead.
It is still
available for PL/I decimal fixed, i.e., packed decimal values.
The LE does in fact make a facility available for
From: Rob van der Heij rvdh...@gmail.com
Sent: Wednesday, October 23, 2013 8:12 PM
Since the machine architectures that came to mind all have this 3-state
result after comparison, I expected the compiler to take advantage of it
when I write something like
if ( j k ) m = -1;
else if (j k) m
From: Dougie Lawson dl1...@gmail.com
Sent: Monday, October 21, 2013 10:32 PM
If I have a table of 3,500 entries of twelve bytes (I'm doing a compare of
eight bytes to find the entry I'm looking for and a check on a half word
marker for the end of the table to avoid running off the end) then is
From: John Gilmore jwgli...@gmail.com
Sent: Wednesday, October 23, 2013 10:02 PM
Interestingly, when I take your C example,
if ( j k ) m = -1;
else if (j k) m = 1;
else m = 0;
return m;
and rewrite it trivially modified in PL/I as
if j k then m = -1;
else if j k then m = 1;
From: Paul Gilmartin paulgboul...@aim.com
Sent: Thursday, October 24, 2013 2:28 AM
What are the representations of boolean values in PL/I?
A single bit.
True is 1, false is 0.
In Rexx, this could be written with no (explicit) branches
as:
m = ( j k ) - ( j k );
In PL/I,
m =
- Original Message -
From: John Gilmore jwgli...@gmail.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Thursday, October 24, 2013 8:09 AM
Subject: Re: signum
Boolean values are bits in PL/I.
Writing, say,
declare (a,b, d) signed binary fixed(63,0), signum signed binary fixed(7, 0),
From: Paul Gilmartin paulgboul...@aim.com
Sent: Tuesday, October 22, 2013 1:42 AM
On 2013-10-21, at 07:13, John Gilmore wrote:
Perhaps also worth noting explicitly is that the linear-search scheme
done well is not significantly less complex than the binary-search
one.
You've earlier
- Original Message -
From: Paul Gilmartin paulgboul...@aim.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Thursday, October 24, 2013 10:43 AM
Subject: Re: signum
On 2013-10-23 17:26, robin wrote:
In Rexx, this could be written with no (explicit) branches
as:
m = ( j k ) - ( j k
From: Paul Gilmartin paulgboul...@aim.com
Sent: Thursday, October 24, 2013 10:47 AM
On 2013-10-23 17:33, robin wrote:
What? Rexx'sm = ( j k ) - ( j k );
would be exactly the same in PL/I.
However, you would never write it like that. It's just obfuscation.
simplest (and trivial-est
From: Paul Gilmartin paulgboul...@aim.com
Sent: Thursday, October 24, 2013 11:51 AM
On 2013-10-23 18:36, robin wrote:
Any overflow is detected.
And anyway, how do you think that J K is computed?
The comparison is performed by subtracting K from J
(without changing either J or K, of course
From: Paul Gilmartin paulgboul...@aim.com
Sent: Thursday, October 24, 2013 11:30 AM
OK. Pure HLASM. I've long wondered why division by zero is permitted
It is? According to my manual, the operation is suppressed,
and an exception occurs.
in arithmetic expressions when otherwise
From: John Gilmore jwgli...@gmail.com
Sent: Monday, October 21, 2013 4:47 AM
TRT and TRTE are different, but TRTE and TRTRE provide you with
everything you need.
o RC=0, no [new] non-zero function byte
found (and input exhausted)
o RC=1, a non-zero function byte has
been found and input
Seems unduly and unnecessarily complicated to me.
I'm a believer in the KISS principle.
From: Andreas F. Geissbuehler afg0...@videotron.ca
Sent: Tuesday, 6 August 2013 12:30 AM
Duffy,
Assuing you meant concatenate as in appending 57 bits to the end of a
bitstring of say 395 bits which when
From: Robert A. Rosenberg a...@rarpsl.com
Sent: Monday, 5 August 2013 1:49 PM
What you are describing is not concatenation - It is altering bits in
the string. As you concatenate you need to increase the string length
and add the new bits to the end.
From his description, the work area is
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Paul Raulerson
Sent: Wednesday, July 24, 2013 7:31 PM
Is anyone aware of an XML parser written in HLASM? Ideally, I would like to
find a DOM like parser, but a SAX parser is better than having to write one
From: Steve Smith sasd...@gmail.com
Sent: Monday, June 24, 2013 12:24 PM
I've been converting some code to use full 64-bit registers lately, and
was greatly surprised that there appears to be no AGH (Add Halfword (to
64-bit register)). There's LGH, and even CGH, as well as AGHI (much
less
From: Scott Ford scott_j_f...@yahoo.com
Sent: Tuesday, June 18, 2013 2:47 AM
God, I remember half word instructions because I only had 16k to work in
..probably the 1401 guys
had less
Many early machines had less.
Pilot ACE and DEUCE had 384 words --
and of those, only 256 words could be
From: Ward, Mike S mw...@ssfcu.org
Sent: Thursday, 30 May 2013 1:09 AM
Hello friends, I was wondering if any of you know of any assembler teaching
tools that might be available for free.
Thanks in advance
Have you looked at Assembler Language with Assist?
From: DAL POS Raphael rdal...@generali.fr
Sent: Friday, 19 April 2013 11:53 PM
And according to Dr John, BCT/BCTG, BXLE/BXLEG are predicted to always branch.
They usually do (always branch).
From: Gerhard Postpischil gerh...@valley.net
Sent: Thursday, 18 April 2013 1:19 AM
On 4/17/2013 9:14 AM, DASDBILL2 wrote:
I learned how to multiply in the third grade. Sixty years later I
still remember how to multiply. It's also important to know when,
why, and what to multiply.
Simple
From: DASDBILL2 dasdbi...@comcast.net
Sent: Thursday, 18 April 2013 1:31 AM
I tried your algorithm with 13 multiplied by 81 and produced the correct answer.
And so it should. It's been around for centuries.
This algorithm is undoubtedly how the microcode for the M (multiply fullword)
From: Ed Jaffe edja...@phoenixsoftware.com
Sent: Friday, 29 March 2013 4:24 PM
On 3/28/2013 10:23 PM, robin wrote:
MVO can be used for quick multiplying/dividing by 10.
True, but I usually prefer SRP for that.
That's only good for up to 31 digits.
For a simple divide/multiply by 10, MVO
From: Martin Truebner mar...@pi-sysprog.de
Sent: Friday, 29 March 2013 9:08 PM
The S/360 and clones didn't have SRP.
So did the originals
So did the originals what?
It's unclear either from the description or from the diagrams
as to what you are trying to do.
How about a hex string of before, and another after?
Anyway, for shifting 4 bits to the left, MVO comes to mind.
For collecting the low order 4 bits of each byte, MVN comes to mind,
and ditto for the
From: esst...@juno.com
Sent: Friday, 29 March 2013 10:19 AM
Thanks To all who responded
MVZ and its counterpart MVN are two instructions I havent used un many Years.
I went back and Looked at POPs.
havent had a need to use them, untill now.
MVZ, MVN, and MVO are highly under-rated.
MVO can
From: Ed Jaffe edja...@phoenixsoftware.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Saturday, 16 March 2013 4:27 AM
In the original S/360, nearly all instructions that manipulated binary
integers treated them as signed quantities.
AL, SL, ALR, SLR come to mind.
These were intended to
From: Bernd Oppolzer
Sent: Sunday, 17 February 2013 8:03 PM
I'd like to second that, for some reasons:
a) other machines like RS/6000 etc borrowed the RR/RX/RS instruction set
from the S/370, and they are RISC in my opinion
Not really; see previous email regarding what constitutes a RISC
From: Tony Harminc
Sent: Sunday, 17 February 2013 11:17 AM
On 15 February 2013 21:33, Robin Vowels robi...@dodo.com.au wrote:
The S/360 is clearly definitely and unequivocably a CISC machine.
Think of instructions like ED, EDMK, TR, TRT, PACK, UNPK, CVB, CVD,
and of course all the decimal
From: Tony Harminc t...@harminc.com
Sent: Monday, 18 February 2013 12:05 PM
On 17 February 2013 18:45, robin robi...@dodo.com.au wrote:
From: Tony Harminc
One might better think of the mix of instruction encountered in a real
world instruction stream. ED and EDMK form a minuscule fraction
From: John R. Ehrman (408-463-3543 T/543-) ehr...@vnet.ibm.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Monday, 18 February 2013 2:09 PM
Subject: Load and Add
Someone (I forgot who...) said they'd like an instruction that would
load a number from memory, add to it, and store it back.
In
From: glen herrmannsfeldt
Sent: Saturday, 16 February 2013 7:51 AM
Instructions are hard to count, though instruction count isn't a
very good way to determine CISCness.
RISC tends to have a small number of instruction lengths, often 1.
S/360 through z/ have three lengths. Not too CISCy,
From: glen herrmannsfeldt
Sent: Saturday, 16 February 2013 7:51 AM
Instructions are hard to count, though instruction count isn't a
very good way to determine CISCness.
RISC tends to have a small number of instruction lengths, often 1.
S/360 through z/ have three lengths. Not too CISCy,
The
The main (but not the only reason) for having EX was to
enable a length to be supplied for SS character instructions.
A better design would be along the lines of MVCL.
Such a mechanism for an extra-special EX (EXS) should supply not only the actual
or true length, but automatically decrement by
From: Martin Truebner
Sent: Friday, 2 November 2012 5:23 AM
However named, this is a hashing scheme.
Okay - If converting a number from a system based on whatever to
a system based on a different number is hashing..
maybe my english needs amending
Long established number-theoretic
Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
l...@listserv.uga.edu] On Behalf Of Robin Vowels
Sent: Monday, August 27, 2012 8:27 PM
How about no registers?
TM X+3,3
BNZ ...
[mailto:ASSEMBLER-
l...@listserv.uga.edu] On Behalf Of Robin Vowels
Sent: Monday, August 27, 2012 8:27 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
How about no registers?
TM X+3,3
BNZ ...
From: Steve Hobson steve_hob...@uk.ibm.com
Sent: Wednesday, 29 August 2012 12:53 AM
Younger readers may like to know that years ago we would test the low two
bits of R15 for zero like this:
CLI *+1,B'1100'
EXR15,*-4
BNE error
Never necessary to do that:
STC
From: John Gilmore jwgli...@gmail.com
Sent: Tuesday, 28 August 2012 1:19 AM
Register contents that are a multiple of 4 are all of the form
x...xx00
Inclusive ORing such a value with the mask
1...1100
and testing the result for equality with this same mask then yields a
simple,
How about no registers?
TM X+3,3
BNZ ...
- Original Message -
From: Tony Thigpen t...@vse2pdf.com
Sent: Tuesday, 28 August 2012 3:19 AM
Your code requires 2 scratch registers. The following uses just 1
scratch register and does not require literal storage:
LA R0,3
NR R0,R15
From: McKown, John john.mck...@healthmarkets.com
Sent: Tuesday, 28 August 2012 1:34 AM
Destroys the contents of R15, so I guess I would load R15 into, say, R0 and do
the OR operation on R0. However, I'm on
a z9 and will likely never be on anything more advanced. So I'll need to load
the mask
From: Paul Gilmartin paulgboul...@aim.com
Sent: Tuesday, 28 August 2012 12:48 PM
On 2012-08-27 19:36, Robin Vowels wrote:
or, if worried about preserving R15
LR0,15
SLL 0,30
LTR 0,0
BNZ ...
Doesn't SLL set the condition code?
No.
But SLA does.
From: Watkins, Douglas douglas.watk...@compuware.com
Sent: Wednesday, 6 June 2012 11:28 PM
Here's one way to do standard EXecute without a base register:
AHI R2,-1 Minus 1 for EX
BTW,
BCTR 2,0 will do a better job.
From: Pesce, Andy andy.pe...@autozone.com
Sent: Thursday, 14 June 2012 3:21 AM
I was always taught:
LABELEQU*
to distinguish a label.
That really isn't a good idea for an instruction.
From: Watkins, Douglas
Sent: Wednesday, 6 June 2012 11:28 PM
Here's one way to do standard EXecute without a base register:
AHI R2,-1 Minus 1 for EX
Still need test for negative.
*!not yetEXRL R2,_EX_MVC_OUTPUT (Move data to output buffer)
LARL
From: Rob van der Heij
Sent: Monday, 4 June 2012 4:41 PM
Since most of the time you just new a few more bytes anyway ;-)
?? Doesn't make sense.
From: Rob van der Heij
Sent: Monday, 4 June 2012 4:41 PM
On Mon, Jun 4, 2012 at 2:45 AM, robin robi...@dodo.com.au wrote:
There's no need to be scared of an odd value.
It is, after all, the assembler that calculates displacements.
If it bothers you, make it 4092. Still no extra instruction
From: John Gilmore
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Tuesday, 5 June 2012 7:37 AM
As an optional usage in coded-arithmetic and hexadecimal constants,
where it is unambiguous, this is an excellent idea.
It has been available in PL/I for a long time, where I may write
Declare Fmax
that calculates displacements.
If it bothers you, make it 4092. Still no extra instruction needed.
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of robin
Sent: Saturday, June 02, 2012 8:12 AM
From: Robert A. Rosenberg
Sent: Saturday, 2
From: Robert A. Rosenberg
Sent: Saturday, 2 June 2012 7:04 AM
LAR11,2048(R12)
LAR11,2048(R11)
LA 11,4095(0,12)
requires only one instruction (adjust USING accordingly).
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