, September 18, 2024 at 7:38:52 PM UTC-4 Ken Semanov wrote:
> This is an issue of the System Generator. Removing the cache relieves the
> problem.
>
> On Wednesday, September 18, 2024 at 7:01:04 PM UTC-4 Ken Semanov wrote:
>
>> Anyone have troubleshooting tips for when Jasper c
This is an issue of the System Generator. Removing the cache relieves the
problem.
On Wednesday, September 18, 2024 at 7:01:04 PM UTC-4 Ken Semanov wrote:
> Anyone have troubleshooting tips for when Jasper compiles hangs at this
> stage?
>
> [image: Screenshot-20240918-18061
Anyone have troubleshooting tips for when Jasper compiles hangs at this
stage?
[image: Screenshot-20240918-180618.png]
I have already tried the following continuously for 90 minutes on several
different slx models. While these "fixes" used to work in the past, they no
longer work now.
AXI interface to
> the DRAM memory to the Zynq CPU so that you can read it directly without
> involving casperfpga? I would assume that there are many xilinx reference
> block diagrams which do something like this.
>
> Certainly doing something akin to "bulk read" would p
e an AXI interface to
> the DRAM memory to the Zynq CPU so that you can read it directly without
> involving casperfpga? I would assume that there are many xilinx reference
> block diagrams which do something like this.
>
> Certainly doing something akin to "bulk read&quo
The solution is to perform these commands while activated into the
environment.
sudo apt-get -y install expat
sudo apt install build-essential libssl-dev libffi-dev python3.8-dev
On Thursday, March 14, 2024 at 9:41:08 PM UTC-4 Ken Semanov wrote:
> The following error occurs during MAT
The following error occurs during MATLAB start up, after activating the
cfpga_env virtual environment and performing ./startsg
Starting Model Composer
Warning: Executing startup failed in matlabrc. This indicates a potentially
serious problem in your MATLAB setup, which should be resolved
Say the xdc file required this line
create_clock -period 3.000 -name A -waveform {0.000 1.500} -add [get_pins B]
Where would the A and B be placed in the constructor of ClockConstraint?
CC = ClockConstraint( signal=??, name=?? , freq=None , period=3.000,
port_en=False, virtual_en=False, wavef
YellowBlock classes have no access to the Jasper build directory. One
possible way around this is to override method add_build_dir_source() , as
is done in lines 110-111 in this file,
https://github.com/casper-astro/mlib_devel/blob/m2021a/jasper_library/yellow_blocks/axi4lite_interconnect.py
The following file appears to be the beginnings of a hardware testing flow
for AXI-Lite interface, in the spirit of the JTAG-to-AXI-Master IP. It
seems to be missing some key components (yellow blocks and .m mask).
https://github.com/casper-astro/mlib_devel/blob/m2021a/jasper_library/hdl_sou
Which part of the CASPER source code parses the "pins:" section of the yaml
files found in mlib_devel/jasper_library/platforms/*.yaml ?
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Is there an obvious way to migrate data from the PL into memory that is
mapped into the address space of the PS? Ideally I would use
axi_interconnect as shown
https://casper-toolflow.readthedocs.io/en/latest/axi4lite_documentation.html
A possible approach is to instantiate axi_dma within the
What is the command line syntax for prg_8a34001?
What kinds of file types are accepted as input by this utility?
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The ZCU216 has a 4 x 25.7 cage for a CAUI-4. In order to receive jumbo
frames at a receiving NIC that only has 100GbE ports, what kind of
hardware cable work would be appropriate?
I have attempted to work closely with a hardware manufacturer, but I feel
they are unreliable in their "advice".
UTC-4 Mitch Burnett wrote:
> By default, the tool will targeting the first CMAC location in this case
> it is the 4x25 SFP28 cage for the ZCU216.
>
> The 100G port option is the one you would want to select.
>
> Best,
>
> Mitch
>
> On Jul 24, 2023, at 3:40 PM, Ke
A simulink model appears below with the hosting github. Is this tutorial
intended to target a ZCU216 with a mezzanine card containing a 100GbE port,
or is it intended to target to the J29 4xSFP28 cage?
zcu216_tut_onehundred_gbe.slx
https://github.com/mitchburnett/tutorials_devel/tree/main/rfs
in the latest
> mlib_develrepo, not sure. It depends whether Xilinx made production silicon
> for this FPGA or left it as an engineering sample.
>
> Kind regards,
>
> Adam
>
> On Fri, Jul 14, 2023 at 3:13 AM Ken Semanov wrote:
>
>> I attempted to retrieve the ex
1, but it may be a production device in the latest
> mlib_develrepo, not sure. It depends whether Xilinx made production silicon
> for this FPGA or left it as an engineering sample.
>
> Kind regards,
>
> Adam
>
> On Fri, Jul 14, 2023 at 3:13 AM Ken Semanov wrote:
>
>> I at
Ken Semanov wrote:
> I am attempting to load the bitstream `zcu216_tut_spec.fpg` located here,
>
>
> https://github.com/casper-astro/tutorials_devel/tree/main/rfsoc/tut_spec/prebuilt/zcu216
>
> The call to `fpga.upload_to_ram_and_program()` causes
> transport_katcp
I am attempting to load the bitstream `zcu216_tut_spec.fpg` located here,
https://github.com/casper-astro/tutorials_devel/tree/main/rfsoc/tut_spec/prebuilt/zcu216
The call to `fpga.upload_to_ram_and_program()` causes
transport_katcp.py:654 to invoke an exception ,
RuntimeError: 132.177.
too, but I am
> not sure who may be working on this.
> >
> > Mitch
> >
> >
> >> On Jun 24, 2023, at 6:40 PM, Ken Semanov wrote:
> >>
> >> The ZCU216 board has 4 ports for SFP28 ethernet on J29. These are used
> for 25GbE
thedocs.io/projects/tutorials/en/latest/tutorials/rfsoc/tut_100g.html>
>
> Mitch
>
> On Jun 6, 2023, at 9:11 PM, Ken Semanov wrote:
>
> board = Zynq UltraScale+ RFSoC4x2board (Gen 3 ZU48DR)
> I am in contact with a manufacturer of 100Gbe optical transceivers. For
> trouble
board = Zynq UltraScale+ RFSoC4x2board (Gen 3 ZU48DR)
I am in contact with a manufacturer of 100Gbe optical transceivers. For
troubleshooting, they want to see connection logs and alarms for the 100Gbe
port. I am sending data from the 100Gbe ethernet leaving the 4x2 on IP
10.17.16.20. (I am us
tarted.html#setup-casperfpga>
>
> <https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/rfsoc/tut_getting_started.html#setup-casperfpga>
>
> Mitch
>
>
> On Jun 6, 2023, at 3:15 PM, Ken Semanov wrote:
>
> Dear Mitch Burnett,
>
> Thank you for th
loc: AH13
> ```
>
> With this added, and using a GPIO yellow block where the name in the
> configuration window for that block is any of `irig_*` names you are
> locking target, you should be getting these signals into your fabric design.
>
> Hope this helps,
>
> Mitch
This has been solved. The serial connection is available through the Micro
USB port, not the Micro USB 3.0 port.
On Saturday, May 13, 2023 at 4:11:59 PM UTC-4 Ken Semanov wrote:
> *RFSoC 2x2 kit University , Xilinx ZYNQ UltraScale+ RFSoC ZU28DR FPGA* model
> no. HTG-ZRF2-XUP
>
>
*board = Zynq UltraScale+ RFSoC4x2board (Gen 3 ZU48DR)*
*.*
[image: smlexternal_PPS.png]
The above shows an external PPS driving an ADC that is SPI's into the
XCZU48DR. In what manner would the FPGA fabric access these pins in a
design? Should the PLLs be programmed externally to align with
work. Silicon Labs Dual CP2105
USB to UART bridge Standard COM Port did not cause the computer to
recognize this board.)
What am I doing wrong here? Should I purchase a Xilinx Platform Cable II?
Or other?
Thank you and best regards,
Ken Semanov
# modinfo usbserial.ko filename:
/lib/mo
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