Hello everyone,
I'm quite new to Casper Tools and have just started playing around with
the tutorials. I am trying to compile tutorial 1 however casper_xps is
throwing up the following two errors:
1. Design Error: caught standard exception
standard exception: XNetlistEngine:
An exception was rai
To: David MacMahon
Cc: Michael D'Cruze; Casper Lists
Subject: Re: [casper] Compile error - Design Error "standard exception" and
Block Error
Hi All,
I had a separate email with Michael about this -- it's an issue that comes up
when not using a supported OS (namely Debian/
Hi everyone
I'm following the NFS setup guide, and have come across a problem with the
/srv/roach_boot/boot directory permissions. I restart the dnsmasq service and
receive the following error:
Starting dnsmasq:
dnsmasq: TFTP directory /srv/roach_boot/boot inaccessible: Permission denied
Hi Jack,
I'm running RHEL 6.6.
THanks
Michael
From: Jack Hickish
Sent: Tuesday, December 2, 2014 2:15 PM
To: Michael D'Cruze; casper@lists.berkeley.edu
Subject: Re: [casper] NFS setup: TFTP permissions problem
Hi Michael,
Do you have SELinux run
Dear all,
The problem seems to be specific to Red Hat... I'm seeing a lot of forum posts
complaining about dnsmasq being started as root then immediately dropping down
to 'nobody' privileges, which is why it can't access /srv/roach_boot/boot.
I'm speaking with a red hat engineer who is quite
Hello,
Just want to clarify a couple of things before I potentially trash my board.
1) NFS file system
On the NFS guide I'm linked to here:
http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/filesystem/ to get the
NFS. Is etch 2009-07-07 the latest one, or should I be downloading th
Hi everyone
I'm trying to connect to the board using the Corr and Matlab katcp clients,
however through both the connection times out. I think I have all the python
libraries installed, and I definitely have the ICT toolbox installed in Matlab.
I've tried disabling the firewall. Katcp does work
Hi Ross,
OK thanks for that, I plan to give that a try tomorrow. Any ideas about Corr?
Corr seems the more promising route.
BW
Michael
-Original Message-
From: Ross Williamson [mailto:rwilliam...@astro.caltech.edu]
Sent: 15 December 2014 22:51
To: Michael D'Cruze
Cc: c
Hello everyone
Does anybody know if there are any high speed (>10GS/s) samplers in
development, aside from the 4-bit sampler listed on the wiki? This would
ideally be >15GSps as we're looking to directly sample C-band. Is the ZDOK able
to handle such speeds?
Cheers
Michael
Work: +27 21 506 7300
On 12 Jan 2015, at 13:22, Michael D'Cruze
wrote:
> Hello everyone
>
> Does anybody know if there are any high speed (>10GS/s) samplers in
> development, aside from the 4-bit sampler listed on the wiki? This would
> ideally be >15GSps as we'r
Hello everyone,
We are considering using one of the 5 GS/s ADCs in our C-band system. We would
like to directly sample the C-band signal (which we would set at 5-7.5 GHz
using an anti-aliasing filter, so we'd operate in the third Nyquist zone),
however many of the documents available on the wik
Hi Casper,
I'm trying to black box some of my larger blocks (PFB, FFT), initially
following tutorial 6 and the memo on the wiki. Both say that, as soon as the
black box is dropped into the model, it should throw up a dialog box allowing
me to link to the pre-compiled code. However, this dialog
Hi Homin,
Thanks for coming back to me. The issue was that the VHD file selection dialog
box wasn’t coming up at all. It’s still unclear why this is…
Best,
Michael
From: Homin Jiang [mailto:ho...@asiaa.sinica.edu.tw]
Sent: 10 August 2015 04:24
To: Michael D'Cruze
Subject: [casper] VHDL
Behalf Of David MacMahon
Sent: 10 August 2015 03:16
To: Michael D'Cruze
Cc: 'casper@lists.berkeley.edu'
Subject: Re: [casper] VHDL black-boxing: basic issue
Hi, Michael,
That sounds very strange. Did you drag-and-drop the black box block into the
model from the library or did you rig
: Michael D'Cruze
Subject: [casper] VHDL black-boxing: basic issue
Hi Michael:
Which version of toolflow you are using ?
If V14.7, following is my own solution, hope that help:
* Or right click the "black box" on the library icon, then select the VHD
file, for example, amiba2_v147/
Hello,
I'm getting an error on compiling a spectrometer design which I'm having
trouble understanding. The following appears in the command line interface:
ERROR:PhysDesignRules:2506 - Incorrect placement for a BUFR component. BUFR
mdl_bbox_quant_asiaa_adc5g/mdl_bbox_quant_asiaa_adc5g/DIVBUF
Hi Jack, Primiani,
That seems to have worked – thanks.
Is this particular branch a beta-test version for fixes before they become
mainstream?
Cheers
Michael
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: 13 August 2015 19:06
To: Michael D'Cruze; casper@lists.berkeley.edu
Subjec
Hi everyone,
I'm having quite a lot of problems getting a particular design to compile, XPS
consistently reporting timing errors. The design is a wideband spectrometer,
somewhat similar to the tutorial 3 design. I'm running an iADC at 1024 MHz, and
the FPGA at 256 MHz. It is a two-polarisation
latency 0,
where DSP48 has been used wherever possible in the design.
Now I need to see if it still works if I use more FIR taps ;-)
Best wishes
Michael
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: 30 August 2015 21:57
To: Michael D'Cruze
Cc: casper@lists.berkeley.edu
Subject: Re: [c
Hi everyone,
I'm having quite a lot of trouble getting large-ish designs (16k channels) to
produce spectra. The spectra that are being produced are quite strange. I've
provided links below to a few examples. The first link is the spectrum produced
by the unmodified tut3 model (except for the AD
Hi all,
I had an odd problem while messing about with the FFT block today - on setting
a new combination of parameters and attempting a new compile, an error came up
which I've never seen before. Something along the lines of an initialisation
error in the FFT. On inspection, the component block
nout 1.
BW
Michael
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: 06 October 2015 15:50
To: Michael D'Cruze; casper@lists.berkeley.edu
Subject: Re: [casper] Weird FFT block problem
Hi Michael,
If the initialisation script fails half way through drawing then often you'll
be left
Dear all,
Following on from the email thread from Jonathan Kocz and Andrew Martens about
odd FFT outputs
I've been experiencing similar inexplicable problems for a while now. Every
other channel in my output is invariably a zero. I've tried everything I can
think of, including solutions al
. I say in the majority of
cases, because in one or two cases the design works correctly. I have not been
able to find a reason for this yet.
BW
Michael
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: 03 November 2015 01:01
To: Michael D'Cruze
Cc: casper@lists.berkeley.edu
Subjec
e FFT looks fine under the mask.
Cheers
Michael
-Original Message-
From: Madden, Timothy J. [mailto:tmad...@aps.anl.gov]
Sent: 03 November 2015 20:25
To: casper@lists.berkeley.edu
Cc: Michael D'Cruze
Subject: RE: casper Digest, Vol 96, Issue 1. FFT woes (Michael D'Cruze)
Mich
Hi Andrew, Jonathon,
Andrew: I was wondering if you'd kept a record of which precise counter (when
implemented in behavioural HDL) caused FFT output to be incorrect? I would like
to take a look and see if this is also my problem.
I also wondered if you knew which ISE versions you had tried...
D
…. This hasn’t worked for Andrew Martens et al., however.
BW
Michael
From: dan.werthi...@gmail.com [mailto:dan.werthi...@gmail.com] On Behalf Of Dan
Werthimer
Sent: 11 November 2015 18:38
To: Michael D'Cruze
Cc: Jack Hickish; casper@lists.berkeley.edu
Subject: Re: [casper] FFT woes
hi mi
Hi all,
As part of my attempts to narrow down the cause of the FFT problems I'm having
(well-documented), I'm trying different versions of ISE. I want to try most of
the 14.x versions plus some rather older versions.
I've installed the versions I want to try but when I change the startsg.local
ISE…
Thanks
Michael
From: Andrew Martens [mailto:and...@ska.ac.za]
Sent: 16 November 2015 06:36
To: Michael D'Cruze
Cc: Jonathon Kocz (jxk...@gmail.com); casper@lists.berkeley.edu
Subject: Re: casper Digest, Vol 95, Issue 3: FFT problems
Hi Michael
Sorry for the very late response.
The pr
Dear all,
First of all a happy new year to everyone!
I continue to chase the problem I've been having for some time now, i.e.
spectrometer designs accumulating using 64-bit vacc blocks output zeroes for
every other channel. This happens with the tut3_noquant tutorial design as well
which is wo
BW
Michael
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: 12 January 2016 21:28
To: Michael D'Cruze
Subject: Re: [casper] ROACH2 spectrum zeroes: request to verify my results
Hi Michael,
That's weird. The adc should be fine in either port. As long as the adc yellow
block zdo
Dear all,
I'm having a little trouble getting the 10GbE data output working correctly. I
have a spectrometer design which feeds the output of (for the moment) a single
vacc into the spead_pack block, which then outputs into the 10GbE block.
I can see from the mailing list that I'm not the first
Dear all,
I'm having a little trouble getting the 10GbE data output working correctly. I
have a spectrometer design which feeds the output of (for the moment) a single
vacc into the spead_pack block, which then outputs into the 10GbE block.
I can see from the mailing list that I'm not the first
full
are both low, b) other designs I’ve seen use much longer packet lengths (e.g.
8192) without a problem.
BW
Michael
From: Andrew Martens [mailto:and...@ska.ac.za]
Sent: 18 February 2016 06:56
To: Michael D'Cruze
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] Trouble getting
Hi Glenn,
I did not have that set at all in the ifcfg script for my eth port, and indeed
the packets do now flow! Great shout, thanks.
Cheers
Michael
From: G Jones [mailto:glenn.calt...@gmail.com]
Sent: 18 February 2016 09:05
To: Michael D'Cruze
Cc: casper@lists.berkeley.edu
Subjec
Dear all,
I'm trying to compile a relatively simple 64k-channel spectrometer. I'm getting
an error which indicates I'm overmapping in BRAMs, however the system map
report indicates I'm using circa 85% of them So the design should fit? Has
anyone else encountered this or could suggest a way
Hi Jack,
Ahh, that explains it. The sum exceeds 100%. I’ll adjust the design….
Thanks
Michael
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: 27 June 2016 16:48
To: Michael D'Cruze; casper@lists.berkeley.edu
Subject: Re: [casper] Design overmapping error
Is that 85% including
Dear all,
During debugging for the new ROACH2 Lovell spectrometer, I've found a potential
issue with the snapshot block that I'm hoping is a control issue.
The snapshot block is intended to take a 4096-channel slice of spectrum, and
display it via a GUI at intervals around 1 second. The spectrum
Dear all,
I've been chasing the cause of some nasty artefacts in my spectra recently. The
first turned out to be a known bug in the Xilinx compiler, activated when the
BRAM_sharing optimisation in the FFT is checked, however the artefacts I'm
seeing since seem to be activated by the RAM blocks
[mailto:jackhick...@gmail.com]
Sent: 18 September 2016 22:27
To: Michael D'Cruze; casper@lists.berkeley.edu
Subject: Re: [casper] Spectrum woes
Hi Michael,
Is this actually the optimisation parameter of the xilinx bram block, or an
optimisation of a casper block which completely changes
For the benefit of the casper list
From: Andrew Vdb [mailto:avd...@gmail.com]
Sent: 19 September 2016 14:19
To: Michael D'Cruze
Subject: Re: [casper] Spectrum woes
Hi Michael,
Sure - it's the FFT BRAM optimization. The coefficient bug was that we were
incorrectly applying the co
Heystek,
Do you have the DSP System Toolbox installed in Matlab?
Michael
September 2016 21:24
To: Michael D'Cruze
Cc: Casper Lists
Subject: Re: [casper] Help with Casper Tutorial 3
Hi Michael
This is the toolboxes that I have:
MATLAB Version: 8.0.0.783 (R2012b)
MATLAB License Number: 724504
Operating System: Linux 3.19.0-68-generic #76~14.04.1-Ubuntu SMP Fri Aug 12
11:
Dear all,
I have a somewhat serious issue in that my adc5g seems to have become stuck in
test mode...
I've messed around a bit with the very many functions within the
calibrate_all_delays top-level function, and can see that the spi_registers are
acknowledging set_test_mode and unset_test_mode,
it out of my python install and grabbing
the latest version (from the disentangle branch), it’s all working again.
Cheers
Michael
From: Primiani, Rurik [mailto:rprimi...@cfa.harvard.edu]
Sent: 07 December 2016 17:17
To: Michael D'Cruze
Cc: casper@lists.berkeley.edu
Subject: Re: [casper]
IODelay cal and MMCM can take place with the adc5g in test mode, not
requiring an input tone?
Thanks
Michael
From: Jack Hickish [mailto:jackhick...@gmail.com]
Sent: 08 December 2016 23:26
To: Michael D'Cruze; Primiani, Rurik; casper@lists.berkeley.edu
Subject: Re: [casper] adc5g stuck in
Dear all,
I'm planning to use a 0.5Hz square wave, generated from the FPGA and output via
sync_out, to eventually fire our cal diode (via much cabling). A quick hardware
test today shows the sync_out port driving at circa 7V (!). This is a bit
higher than I was expecting. Does this venture as a
...@gmail.com] On Behalf Of Dan
Werthimer
Sent: 18 May 2017 15:36
To: Zhu, Yan
Cc: Michael D'Cruze; casper@lists.berkeley.edu
Subject: Re: [casper] ROACH2 sync_out
hi zhu yan and michael,
to bring the roach2 sync output voltage down to 0 to 5 volts when driving 50
ohms,
you could
Hi Franco,
Just curious, but have you considered using SmartXplorer to assist in getting
your design to meet timing, if this is the eventual goal? Usually I find that
with a medium or large design, if I can adjust the latencies in Simulink to get
within a timing score of, say, 1, then runni
Hi Yunpeng, all,
I recently wrote a memo which describes how you can use Xilinx SmartXplorer to
help with timing issues. Have a look on the casper wiki in the Memos section:
https://casper.berkeley.edu/wiki/images/f/f8/SmartXplorer_memo.pdf . It isn’t a
free pass – you need to get fairly close
Hi Heystek,
If a bit file is created – and I think it is (someone correct me if I’m wrong?)
– you can use the following code to generate a bof file from it:
mkbof -o system.bof –s core_info.tab -t 3 system.bit
where core_info.tab is in XPS_ROACH2_base/.
If that doesn’t work you can use the ISE
Dear all,
Does anyone know if the "adc5g" board in its broadly existing form can be
operated using all four inputs independently? I have in mind that a minor
rework of the HDL code and yellow block, and additional SMA connectors could be
installed, without requiring a completely new board to be
Rolando,
This is a shot in the dark but I’d suggest checking your MTU size hasn’t been
changed during whatever updates/upgrades you alluded to in your original
message. I recall having issues such as the one you described and it turned out
to be that.
Good luck!
From: Rolando Paz [mailto:flx.
+1!
From: Brad Dober [mailto:do...@sas.upenn.edu]
Sent: 26 August 2019 22:21
To: Casper Lists
Cc: Michael D. Niemack
Subject: [casper] Spare ROACH2 Boards?
Hi Casper Community,
With the upcoming retirement of ROACH2 production, I was interested in seeing
if any groups were retiring their boards
Hi everyone,
I'm clutching at straws a little, but I've recently obtained a RHEL7 system for
use with the Vivado toolflow. What we'd really like is to be able to compile
models using the "old" ISE toolflow on this new machine. I wondered if anyone
had been able to make this happen? I've got RHE
Hi Heystek,
I’ve seen a similar thing recently installing ISE on a Linux 7 machine. It
looks like a complaint about the naming convention of your primary NIC. You can
force a name-change if you want using the network manager (I did it in RHEL,
unsure about Ubuntu) but better to find a solution
e elegant solution to this.
Thanks for the help!
Heystek
On 18 Aug 2020, at 12:44, Michael D'Cruze
mailto:michael.dcr...@manchester.ac.uk>> wrote:
Hi Heystek,
I’ve seen a similar thing recently installing ISE on a Linux 7 machine. It
looks like a complaint about the naming co
Hi Heystek,
I haven’t seen this before. Is there anything in your working directory that
the import statement could be confusing with your desired module? Perhaps try
changing your working directory.
GL
Mike
From: Heystek Grobler [mailto:heystekgrob...@gmail.com]
Sent: 04 September 2020 11:37
Lots of cores, lots of RAM, and an SSD primary!
I worked with a six-core i7 running at 4.xxGHz and 64GB RAM, which seemed fine,
but I was clearly bottlenecked by my HDDs. Definitely have an SSD...
fortunately multi-TB NVMe drives are affordable now.
Best,
Mike
-Original Message-
From:
Hi,
Following a system upgrade under duress from our local IT, I've installed a
fresh set of mlib_devel, casperfpga libraries. Installation was suspiciously
successful until an attempted program... when casperfpga hanged with no return.
After a bit of digging this seems to be because git_write_
Hello everyone,
I'm experiencing some issues getting my data acquisition going again after
being forced to upgrade my OS from RHEL6 to Rocky 8, specifically: there's an
issue getting the python implementation of spead2 to capture packets from the
stream. On RHEL6 I operated spead2-0.5.x (I thin
Hi Wang,
😬
I did use netboot for a while on my roach2 way back in the day, but it was
easier especially following various updates to the board to just use soloboot.
I hate to ask but is there a reason you need to use netboot?
I assume you're using a roach2, and not a roach1?
BW
Michael
_
am currently trying to use Ubuntu14 for netboot and also getting an error
about exportfs -a.
I have also considered trying other boot methods, are there any related
tutorials？All I can find is netboot.
Thank you very much for your reply！
Wang
Michael D'Cruze
mailto:michael.dcr...@postgrad.manc
Hi Wang,
You might consider running Centos 6.X, Ubuntu, or Fedora as Virtual Machines
within e.g. some other common Linux distro (with which your computer is
compatible). This is what I'm currently doing: I have Rocky 8.6 as my main OS
then Centos 6.10 in a VM for developing with roach2, and Ub
M. Do I need to set up some extra files to make
ROACH2 work?
What does your main operating system do, and what does it do when ROACH2 works?
I am sorry to take up your precious time.
BW
Wang
Michael D'Cruze
mailto:michael.dcr...@postgrad.manchester.ac.uk>>
于2022年6月13日周一 20:38写道：
Hi
Hi Wang,
The memos are on github now. See:
https://github.com/casper-astro/publications/blob/master/Memos/files/p011.quant.pdf
BW
From: casper@lists.berkeley.edu on behalf of Wang
Sent: 24 June 2022 15:32
To: casper@lists.berkeley.edu
Subject: [casper] PAPE
Hi Grace,
Some things to check:
-- are you definitely using the correct eth port on the roach?
-- are you using a crossover eth cable? you'll need a crossover to get it to
talk straight to a PCI-E NIC, but if you can put a switch between them I think
it'll work
-- to check the IP (unsure whethe
From: casper@lists.berkeley.edu on behalf of 王钊
Sent: 01 August 2022 16:57
To: casper@lists.berkeley.edu
Subject: Re: [casper] Copy .fpg file to ROACH2 server
Hi Michael,
I can't use the casperfpga function.Now I am using Corr.
I don't quite understand what you mean by
Although I have expressed interest in these boards as well, it may be of
interest to anyone in desperate need of more roach2s (and with money to pay for
them) that Digicom are manufacturing these boards again, albeit only a small
run of ten or so...
BW
Michael
F
Hello,
Does anyone have any spare katADCs they might be prepared to donate, or sell
for some notional fee? We're in need of at least one, after our spare was found
to be damaged, but a handful would be good.
Thanks
Michael
--
You received this message because you are subscribed to the Google
FYI, this role has recently been advertised at SKAO:
https://recruitment.skao.int/vacancy/signal-processing-engineer-504661.html
Best,
Michael
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