Hi all,
casper.berkeley.edu will be down from around midday on Sunday 25th June
until ~9am Monday morning (Pacific time), owing to maintenance at
Berkeley's Space Science Lab.
Sorry for the inconvenience,
Jack
--
You received this message because you are subscribed to the Google Groups
"caspe
g
> flow execution...gmake: *** [__xps/system_routed] Error 1ERROR:EDK -
> Error while running "gmake -f system.make bits".: XPS failed.*
>
> Any idea what I could be doing wrong?
> Has anyone worked with that "yellow block" recently?
> Is there any example availa
CPU Rx" option requires further selection in the
> configuration panel to work properly. i.e.: I am configuring the block
> wrong, or the "yellow block" has a problem.
>
> If it is of any help, I am using mlib_devel master branch commit
> 225aa9ed21aa914078546d2256c56f77f9
This should be fixed in commit
https://github.com/casper-astro/mlib_devel/commit/0c3f3349e0ea5b135015f247cdae3f1b71af8c86
Let me know if you have any problems.
Thanks for the error report,
Jack
On Thu, 22 Jun 2017 at 12:46 Jack Hickish wrote:
> Hi Xavier,
>
> Yeah, that's a bu
Hi Adam,
Some months ago I tried to get the ddr in the casper-astro library working,
using code provided by people on this list. Needless to say, I failed. I'm
not sure what was wrong, but my spare time to debug got exhausted, and I
haven't looked at this since.
However, for your particular probl
Hi Colin,
I don't think many people are supporting windows, though there was an email
from a few hours ago --
https://www.mail-archive.com/casper@lists.berkeley.edu/msg06862.html --
which had a link to a windows-friendly repo version. Perhaps this would be
useful to you.
Jack
On Wed, 28 Jun 2017
Hi Xavier,
I believe all the "snap" blocks have been deprecated, in favour of the
newer "snapshot" block, which has integration in the software control
libraries. If you are having this problem in a collaboration supplied model
(it sound like you're doing tut2?) it will be updated in due course pr
these
> interfaces work and I feel I am missing something.
>
> thanks,
> XB
>
>
>
> On Thu, Jun 22, 2017 at 12:46 PM Jack Hickish
> wrote:
>
>> Hi Xavier,
>>
>> Yeah, that's a bug. I'll have a fix shortly, but for now I would just
>> l
On Wed, Jul 5, 2017, 6:56 AM Schoenwald, Adam J. (GSFC-5640) <
adam.schoenw...@nasa.gov> wrote:
> Hi All,
>
> I’ve abandoned my attempt to use the DRAM for now and moved on to QDR.
>
> I’m somewhat confused by the wiki at https://casper.berkeley.edu/wiki/Qdr
> .
>
>
>
> The “issuing commands sect
ical Engineer
> Office: 301.286.4175 | Cell & Text: 631-241-0003
>
>
>
> -Original Message-
> From: Jason Manley [mailto:jman...@ska.ac.za]
> Sent: Wednesday, July 5, 2017 10:55 AM
> To: Jack Hickish
> Cc: Schoenwald, Adam J. (G
Hi Xavier,
At 2.5GHz sampling frequency you might need to calibrate each IO lane
individually, rather than just sweeping the global clock phase. I don't
know where you're getting your calibration code from, but if you have a
calibrate_all_delays method (like at
https://github.com/jack-h/adc_tests/
Hi Sam,
I'm not familiar with the music board, but I wonder if it would benefit
from tuning the clock vs data skew on the adc->fpga links to tune the data
capture for reliability.
Are you coming to the CASPER workshop? If so I suggest bringing a music
board and maybe somebody can donate some time
ck,
>
> Would that be akin to the calibration routine which was written for the
> ADC5G? I will be at the workshop, and can definitely bring a test setup.
>
> Thanks,
> Sam
>
> On Thu, Aug 3, 2017 at 2:08 PM, Jack Hickish
> wrote:
>
>> Hi Sam,
>>
>> I
Hi Beatriz,
Welcome to the CASPER mail list!
There is no formal membership of the collaboration. Whatever you are using
CASPER hardware or software for, this mail list is the place to post
questions, get help, or announce things you've built or are willing to
share.
Having said that, manufacture
Hi Xavier,
Using an adapter might be possible in principle, but it definitely won't
work out the box. It's probably about three orders of magnitude more design
effort to get this working vs using the on-board 1gbe :)
Sorry!
Jack
On Thu, Aug 10, 2017, 1:33 PM Xavier Bosch
wrote:
> Ryan,
> Thank
Weird. I'm guessing that is a software register? if you select the block
that's throwing the error, then in matlab type "update_casper_block(gcb)"
(which will delete that block and replace it with a fresh copy from the
library) does that help at all.
Cheers
Jack
On Fri, 25 Aug 2017 at 04:21 Heyst
Hi Anshu,
To add to John's comments -- this isn't an "error" in the sense there's
anything wrong with your code or the tools. It's a failure of the Xilinx
placer/router to find a way of implementing your design which will run at
the speed you requested (250 MHz(?)).
Probably these are specific par
Hi all,
In the aftermath of the workshop, there is going to be a fair bit of
development to the CASPER website, documentation, software, and tools. To
avoid spamming the list, I've just created a new mail list:
casper-...@lists.berkeley.edu
for announcements for that may interest developers (sched
Hi Indrajit,
In would appear a file was declared deprecated and removed in a previous
commit. I've re-added this file in the casper-astro roach2 branch --
https://github.com/casper-astro/mlib_devel/tree/roach2
It appears there is also an issue with some IP core having an uppercase
name, which I'm
u need. I've no idea if XAUI ever worked on ROACH2 with CX4 cards
Cheers
Jack
On Mon, 9 Oct 2017 at 15:47 Jack Hickish wrote:
> Hi Indrajit,
>
> In would appear a file was declared deprecated and removed in a previous
> commit. I've re-added this file in the casper-as
Hi Mugundhan,
Is the boffile that fails to program executable? I.e., if you log into the
roach and run "ls -la /boffiles/" do the working and not-working boffiles
have the asme permissions.
(I don't actually know if roach1 still requires boffiles to be executable,
but it used to, so maybe it's wor
t;
> Thank to you and James :)
>
> Regards,
>
> Mugundhan
>
> On Fri, Oct 13, 2017 at 10:34 AM, Jack Hickish
> wrote:
>
>> Hi Mugundhan,
>>
>> Is the boffile that fails to program executable? I.e., if you log into
>> the roach and run "ls -la /bo
Hi Vijay,
If you scroll up through the compile output do you see another, more
helpful, error.
As a guess, is it possible that your capture RAMs are so deep that you've
used up all the memory on the chip?
Cheers
Jack
On Tue, 31 Oct 2017 at 08:43 Vijay Kumar wrote:
> Hello Casperites,
> I need
in the bram size limits. Moreover, I
> am able to successfully compile the design using 16 blocks.
>
>
>
> On Tue, Oct 31, 2017 at 12:21 PM, Jack Hickish
> wrote:
>
>> Hi Vijay,
>>
>> If you scroll up through the compile output do you see another, more
>&g
Hi Carl,
What branch / git hash of mlib_devel are you using?
Cheers
Jack
On Tue, 31 Oct 2017 at 13:40 Felten, Carl (382F)
wrote:
> Hi,
>
>
>
> I am trying to generate an HDL Netlist of a design that includes the
> fft_wideband_real block. I get an error that “initialization commands
> cannot b
7; as
> prefix.
>An address value with no prefix is assumed to be a decimal number.
> WARNING:EDK - IPNAME: opb_bram_if_cntlr, INSTANCE: adc16_snap_h - ADDRESS
>PARAMETER C_HIGHADDR has 20-bit value. Mpd specifies 32-bit value -
>/home/indrajit/Downloads/sbp_32_2/XPS_RO
he coeff_gen block get erased
> when I try to Generate:
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* Tuesday, October 31, 2017 1:48 PM
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] missing "cosin" block inside fft_wideband_real
On Thu, 2 Nov 2017 at 10:51 Felten, Carl (382F)
wrote:
> Looks like that works.
>
>
>
> Thanks Jack!
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* Wednesday, November 1, 2017 4:18 PM
>
>
> *To:* casper@lists.berkeley.edu
>
Working on getting it back up. Sorry for the inconvenience.
Jack
--
You received this message because you are subscribed to the Google Groups
"casper@lists.berkeley.edu" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to casper+unsubscr...@lists.berkeley.
Website/wiki back up now (thanks Jeff Cobb!).
Cheers
Jack
On Wed, 15 Nov 2017 at 16:07 Jack Hickish wrote:
> Working on getting it back up. Sorry for the inconvenience.
>
> Jack
>
--
You received this message because you are subscribed to the Google Groups
"casper@lists.be
Hi all,
Just a heads up in case anyone is in need of a 32-port 40GbE switch.
The Arista 7050QX-32 is super-cheap on ebay
eg.
https://www.ebay.com/itm/FIRE-SALE-Arista-DCS-7050QX-32-R-32x-Port-40G-QSFP-Layer-3-Switch-10G-Switch/272949806199?epid=662262969&hash=item3f8d138477:g:DtQAAOSwlyJaFaZ0
h
More spam from me (sorry not sorry).
The Berkeley SETI group is a major user and developer of CASPER stuff, and
I'm sure could find uses for the skills of undergrad CASPERites.
Cheers
J
-- Forwarded message -
From: Steve Croft
Date: Mon, 4 Dec 2017 at 14:43
Subject: Berkeley SETI
Hi CASPERites,
Here at UC Berkeley we are in the process of putting together some job
adverts for CASPER research positions at UC Berkeley. We are hoping to
advertise positions for those with batchelors, masters, or doctoral degrees
to help develop next-gen CASPER tools and software/hardware infra
cores –
> i.e. JESD204B interface..) and #3 (testing new hardware). I would be
> interested in the “ working remotely” option below.
>
> Thanks
>
> Raoul
>
>
>
>
>
> *From:* Jack Hickish [mailto:jackhick...@gmail.com]
> *Sent:* Tuesday, December 05, 2017 10:4
Hi Xavier,
For what it's worth, our SNAP2 collaborators in China made an FMC card with
the 12 bit version of the ASIAA ADC chip. This might be a reasonable
starting point if you don't want to go to wild with JESD.
The post-Virtex6 version of the toolflow (i.e., that used by SNAP / SKARAB)
began l
If you're using Ubuntu, you might want to check the tweaks at
https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.x_and_Matlab_2012b,
which include the dash vs bash issue Dave mentioned.
Cheers
Jack
On Wed, 3 Jan 2018 at 19:16 David MacMahon wrote:
> Hi, Roberto,
>
> I suspect that your
Hi pei xin,
The short answer is, "yes". But there's clearly some work to be done on
making the error handling cleaner.
After those warnings, does the CasperFpga instance actually work? The first
warning is the client attempting to connect using the microblaze interface
(for SNAPs without RPIs) and
ave me "True" when I ran
> "fpga.is_connected()". But it launched an error when I loaded the .fpg file.
> fpga.upload_to_ram_and_program('snap_tut_intro.fpg')
> RuntimeError: progremote request(Request to client snap failed.) on host
> snap failed
>
> Best wishes,
&
Hi Homin,
No-one replied to this, so i'll bite.
In principle you could do this, but there is no canned way to
obtain/save/reload the calibrations. They are implemented by stepping some
MMCMs (rather than a register containing fixed offsets) so you'd have to
count the steps during calibration, and
Hi Bela,
You might try increasing the Java heap size -
https://www.mail-archive.com/casper@lists.berkeley.edu/msg04642.html -
that's been known to help in some cases.
Cheers
Jack
On Mon, Jan 29, 2018, 11:50 PM James Smith wrote:
> So updating the diagram at the moment produces no error, and yo
On Tue, Jan 30, 2018 at 1:23 PM, Jack Hickish
> wrote:
>
>> Hi Bela,
>>
>> You might try increasing the Java heap size -
>> https://www.mail-archive.com/casper@lists.berkeley.edu/msg04642.html -
>> that's been known to help in some cases.
>>
>&g
Hi Paolo,
If I'm reading the code correctly --
https://github.com/casper-astro/mlib_devel/blob/roach2/xps_library/%40xps_adc_mkid/xps_adc_mkid.m
--
I believe that none of the SPI pins are driven. I have no idea whether any
of these pins are pulled in any particular direction on the hardware since
Howdy,
Partly motivated by a search for RAM savings, and partly for fun, I'm
looking through the innards of the fft_biplex_real_4x block. Can someone
tell me, using short words and/or pictures, what the the relationship
between the inputs (pol1, pol2) and the outputs (out1, out2) on the
biplex_cor
irst N/2 clocks out
> both output ports, even channels on top (in bit reversed order) and odd on
> bottom (also bit reversed order). Pol2 outputs follow for the next N/2
> clocks, same order.
>
> On Wed, Feb 21, 2018 at 6:04 PM Jack Hickish
> wrote:
>
>> Howdy,
>>
biplex fft algorithm:
> https://www.amazon.com/Multirate-Digital-Signal-Processing-Crochiere/dp/0136051626
>
> I agree with Aaron's memory of the output ordering.
>
> Glenn
>
> On Feb 21, 2018 18:04, "Jack Hickish" wrote:
>
>> Howdy,
>>
>> P
ive inputs simultaneously.
>
> Dave
>
> On Feb 21, 2018, at 18:04, Jack Hickish wrote:
>
> Howdy,
>
> Partly motivated by a search for RAM savings, and partly for fun, I'm
> looking through the innards of the fft_biplex_real_4x block. Can someone
> tell me, using
I am quite use to verilog and SPI (I did something
> similar for an I2C interface) but I can't say the same for OPB bus,
> power-pc's and so on... it will take me a while I guess. I will contact you
> when I will be on it.
>
> Cheers,
> Paolo
>
> 2018-02-20 19:57
lt;2>" LOC = N15 | IOSTANDARD = LVCMOS33 | S | PULLUP;
>
> NET "eth_rx_d<3>" LOC = P18 | IOSTANDARD = LVCMOS33 | S | PULLUP;
>
>
>
> Given that the ROACH flow is mostly automated, this last option might be
> the simplest. Just add the SPI constrai
Hi CASPER folk,
I'm in the midst of buying lots of 10/40GbE transceivers for HERA, and
thought I'd throw out some names of suppliers who we use / made attractive
quotes.
Fiberstore (fs.com) has been our go-to for a while for optics purchases,
and we've had good luck (admittedly with some early te
d pol2 being presented
> at the respective inputs simultaneously.
>
> Dave
>
> On Feb 21, 2018, at 18:04, Jack Hickish wrote:
>
> Howdy,
>
> Partly motivated by a search for RAM savings, and partly for fun, I'm
> looking through the innards of the fft_biplex_real_4x block
Hi Arash,
It's awesome that you're doing this.
I only have experience bringing up the 10GbE core on SNAP, but a few things
you might try are:
- Make sure all the (many!) clocks are running at the correct speed -- easy
to misconfigure.
- Check and double check resets
- Setting the transceivers int
Hi Rolando,
This sort of channel number offset issue usually indicates a misalignment
between the sync pulse in the design and data where your data goes through
an operation that has some latency, and this latency isn't compensated for
in the sync signal.
One clue is that there is usually a spike
there any way to find the place and value of the latency that I must
> remove or add, to the synchronization pulse inside my design?
>
> Regards
>
> Rolando
>
>
> 2018-03-10 18:47 GMT-06:00 Jack Hickish :
>
>> Hi Rolando,
>>
>> This sort of channe
Hi Karl,
On Thu, 15 Mar 2018 at 21:59 Karl Warnick wrote:
> Hi all,
>
> I have a non-astronomical comms antenna array project that does not have
> detailed specs for bandwidth and number of antenna elements. I need to
> build a programmable platform that I can use for multichannel sampling
> and
Hi Andrea,
On Wed, 21 Mar 2018 at 13:22 Andrea Mattana wrote:
> Hi all,
>
> after many months of working on another board (SKA TPM for LFAA) today I'm
> back to a project using the ROACH-1 but I figured out that my "longterm"
> Matlab R2009b license expired, therefore I decided to try to install
Hi all,
tl;dr -- We're trying to figure out if there is any interest in free,
cloud-hosted CASPER tools: please fill out the survey at
https://docs.google.com/forms/d/e/1FAIpQLSeetuYWr3WPnUDGjdTznEFVptY_Y0mFXaTsKrDEAEAKSBVRbA/viewform?usp=sf_link
--
For as long as I can remember, people have
ption in OFFER/ACK: 28
> *** Unhandled DHCP Option in OFFER/ACK: 28
> DHCP client bound to address 192.168.10.121
> Using ppc_4xx_eth0 device
> TFTP from server 192.168.10.5; our IP address is 192.168.10.121
> Filename '/roach2/boot/uImage-r2borph3'.
> Load address: 0x400
t; infrastructure for the last workshop or who is going to do for the coming
> > workshop.
> >
> > I will update on progress as well maybe changing the subject of the this
> > thread that can be considered closed ;)
> >
> > Cheers,
> > Andrea
> &
Hi Vijay,
Are you trying to black box a system generator model, or plain
verilog/vhdl? In the latter case, any error in the HDL syntax or issues
with port declarations will probably cause the tools to implode like you
see.
Do you still get this error with the latest (14.7) of the xilinx tools, an
_write_register(self.fpga, 0, addr[i],
> val[i])
> corr.katadc.spi_write_register(self.fpga, 1, addr[i],
> val[i])
>
> Note that at higher clock speeds, the value of the second register is
> changed (commented third line), as determined by Jack Hickish. If you want
>
On 04/19/2018 11:20 AM, Jack Hickish wrote:
> > The clock should trigger capture of the values on the data lines when
> > they are stable, so putting the clock edges out of phase with the data
> > transitions makes sense. Having said that, the controller HDL may or
> > may
case?
Cheers
Jack
On Thu, 19 Apr 2018 at 14:59 Tom Kuiper wrote:
> On 04/19/2018 11:52 AM, Jack Hickish wrote:
> > Thinking about this a moment longer -- I don't think an incorrect
> > clock phase will be related to reported board clock problems. You can
> > comp
Hi Franco,
Late reply, but did you ever get to the bottom of this?
When the compile finished did it appear to generate a new .bin file? If so
maybe the binary is fine and it's just the bin->bof generation that's
broken.
Cheers
Jack
On Mon, 9 Apr 2018 at 12:43 Franco Curotto wrote:
> Dear all,
ectly.
>
> Thanks anyways.
>
> Franco
>
>
> Original Message
> Subject: Re: [casper] Unable to run SmartXplorer inside CASPER toolflow
> From: Jack Hickish
> To: casper@lists.berkeley.edu
> CC:
>
>
> Hi Franco,
>
> Late reply, but di
Hi Jake,
That's interesting, I don't think I've seen this failure mode before. If
you plug a mini usb connector into the SNAP, you can read debug messages
over this port, using it as an 8N1 115200 baud serial interface. If you
have a xilinx programmer, you could also burn the flash manually with
v
nit FAIL
> # JAM starting
> using ethernet core gbe_port0
> MAC 0x004089411302
> IP NM GW
> link is UP
> FPGA at 33.6 C [ms 1]
> FPGA at 33.6 C [ms 2]
> ...
>
>
> Cheers,
> Jake Jones.
>
> On Tue
erver ready
>> but there is no network traffic or logs suggesting that this IP was
>> obtained by the DHCP server. Nonetheless, I tried connecting to it using
>> this IP but had no success there either.
>> fpga = casperfpga.CasperFpga('169.254.3.19', port=69)
ing this new golden image the SNAP board
> obtained an IP address and I was able to talk to it with no problems.
>
> Cheers,
> Jake Jones.
>
>
>
>
>
> On Wed, May 23, 2018 at 3:44 PM, Jack Hickish
> wrote:
>
>> Hi Jake,
>>
>> I've seen that
sorry again
Hi Ramesh,
Late response to your email, but, did you investigate using that switch
with one of the free non-iCOS operating systems (for those of us who are
super-cheap)?
Cheers
Jack
On Tue, 12 Jun 2018 at 08:12 Ramesh Karuppusamy
wrote:
> Hi Homin,
>
> We have had very good experience with the
Hi Alex,
I don't know if there's a way to avoid generating the full spectra prior to
taking the fft (I suspect if there is, it just pushes the buffering
somewhere else), but it certainly seems like you should be able to do FFTs
of two streams, A, B, in parallel. I would think this would work by (a
which might be useful.
>
> As a sidelight, I’ve been trying to find a venerable paper I recall Aaron
> Parsons et al. wrote on the CASPER Biplex FFT. I can’t seem to find the
> one I recall, this is the closest I have come, but doesn’t have the
> singular focus on the FFT I recall in an
Sounds like you do have the official image I'll upload it to the wiki!
tcpborphserver is a server which runs on the RPI and speaks katcp (the
protocol the roaches use). It basically receives katcp read/write/program
commands over a TCP socket and then actions them on the FPGA using the
chip's
Hi All,
There is currently an opening for an Assistant Researcher in UC Berkeley's
Radio Astronomy Lab "in the area of radio astronomy instrumentation,
computer systems and networks, and data analysis."
This is *not* specifically a CASPER position (the advert does not come from
me) though there w
Hi David,
I'll also add that later this week I'll be vetting all the snap tutorials
for the workshop, so if there is an issue hopefully by the end of the week
it'll be fixed.
Cheers
Jack
On Tue, 18 Sep 2018, 5:02 pm Brian Bradford, wrote:
> Hi David,
>
> Since you are new to CASPER, I would r
Hi All,
Thanks to all those who made the trip to China to attend our annual
workshop. I hope you've all have made it safely back home.
I was reminded at the workshop to re-advertise the CASPER developer mail
list. This email list is used to organize monthly developer meetings (to be
chaired by Am
Hi Peix Xin,
That should work. What mlib_devel are you using?
Is your ADC card a demux 1 version?
What ADC yellow block settings?
What snap MSSGE block settings (should be clocking from adc0_clk)
Are you applying a clock to the ADC card - you can't use the on-board
synthesiser with an external A
m?
> And the mlib_devel is the same one we used for Crab design.
>
> The ADC yellow block and MSSGE block settings see attach 2 and 3 .
>
> The clock signal is from Valon 5008 and inject to the Clock SMA connector
> of ADC.
>
> Best wishes,
> Pei Xin
>
>
> *From:
Hi all,
Another job is available in Berkeley's Radio Astronomy Lab which people on
this list might be interest in.
See details below.
Thanks
Jack
Postdoctoral Scholar - Radio Astronomy Lab.
https://aprecruit.berkeley.edu/apply/JPF01918
The Radio Astronomy lab (RAL) at the University of Califor
6-(0)991-3689471 <+86%20991%20368%209471>
> 传真(Fax): +86-(0)991-3838628 <+86%20991%20383%208628>
> ==
>
>
> *From:* Jack Hickish
> *Date:* 2018-10-09 21:26
> *To:* pei...@xao.ac.cn
> *CC:* casper
> *Subject:* Re: [CASS SPAM]Re: [casper] ADC5G on SNAP
>
> Hi
at 18:37 Jack Hickish wrote:
> Hi Pei Xin,
>
> What mlib_devel library are you using?
>
> Are you using any python code to configure your ADC after programming the
> FPGA?
>
> Cheers
> Jack
>
> On Mon, 15 Oct 2018 at 23:08 pei...@xao.ac.cn wrote:
>
>> Hi
Seconded -- thanks for all the hard work, Ran & organizing committees.
On Wed, 17 Oct 2018 at 02:26 Colm Bracken wrote:
> Dear Ran,
>
> Thank you so much for sharing the lovely pictures from CASPER 2018.
> Also, thank you once more to yourself and the rest of the LOC and the SOC
> for such an en
Hi Jake,
I don't think anyone has done quite what you're planning. In HERA we have
no FPGA fans and only external airflow, but in our case we place the SNAP
boards in RFI-enclosures, with the FPGA thermally coupled to the enclosure
case via aluminium blocks and thermal compound. Our experience wit
;+86%20991%20368%209471>
> 传真(Fax): +86-(0)991-3838628 <+86%20991%20383%208628>
> ==
>
>
> *From:* Jack Hickish
> *Date:* 2018-10-17 09:37
> *To:* pei...@xao.ac.cn
> *CC:* casper
> *Subject:* Re: Re: [CASS SPAM]Re: [casper] ADC5G on SNAP
>
> Hi Pei Xin,
>
&g
; 中国科学院新疆天文台
> Xinjiang Astronomical Observatory, CAS
> 新疆乌鲁木齐市科学一街150号
> <https://maps.google.com/?q=%E7%A7%91%E5%AD%A6%E4%B8%80%E8%A1%97150%E5%8F%B7&entry=gmail&source=g>
> (邮编: 830011)
> 150, Science 1-Street
> Urumqi, Xinjiang 830011
> China
> 电话(Tel): +
Hi Nitish,
Hope you don't mind, but I'm taking this back on the list.
Your understanding of the PPS signal is correct.
If you with to use the on-board SNAP ADCs, you have two clocking options,
both of which require an external signal to be provided.
1) Provide a timing reference (usually, but n
Hi Franco,
Thanks for this. I don't *think* such a block exists in the library, though
I could be wrong. One thing high on the agenda is to reorganize the
libraries in mlib_devel to make it easier to add blocks in without git
conflicts.
Hopefully we (cough, Brian) will get round to this soon[ish].
Hi Nitish,
Because you mentioned SDRAM, I'm assuming you're talking about SNAP 2 (
https://casper.berkeley.edu/wiki/SNAP2).
For SNAP2, you'll find some constraints (although not in xdc format) here
--
https://github.com/shlean/mlib_devel/blob/master/jasper_library/platforms/snap2.yaml
@Lin Shu
Howdy all,
You may have noticed that the CASPER wiki/website server, which lives in a
closet in Berkeley, is becoming increasingly unreliable. In the interests
of making a more stable site, with lower sys-admin overhead, we'll be
slowly migrating to a cloud-hosted service.
The first step in this
Dear CASPERites,
The CASPER collaboration has, over more than a decade, created a friendly,
vibrant, and successful community or astronomers and engineers. Many of us
have CASPER to thank for our instruments, scientific papers, and careers.
In the interests of making sure our collaboration is wel
Hi All,
Since many of you are interested in Xilinx's new RFSoC chips, please be
aware that a memo about characterization of the ZCU111 RFSoC board ADC
performance is available at
https://casper.ssl.berkeley.edu/wiki/images/d/dc/Zcu118-memo.pdf .
This memo was generously shared by Paul Roberts at
Hi David,
What type of transceiver are you using on the snap, and which port are you
using?
Cheers
Jack
On Tue, 11 Dec 2018, 1:06 pm David Marsh, wrote:
> Hi all,
>
> I am having a similar issue (to
> https://www.mail-archive.com/casper@lists.berkeley.edu/msg07245.html)
> when trying to progra
fixed in firmware. Sorry it's taking so
long.
On Tue, 11 Dec 2018, 2:13 pm David Marsh, wrote:
> Jack,
>
> We are using the 10GbE SFP+ port P1 on the SNAPv1 board. The cable that we
> have between the snap and the server is XFP-SFP+
>
> Thanks,
> David
>
> On T
Hi Arash,
Great work!
I can probably send a SNAP or 2 your way on load if you think that'd be
helpful.
And/or I could probably get you a Red Pitaya?
Also, I'm experimenting with cloud-hosted compile environments and am
close-ish to having something here which might work. Is this something
which
Hi CASPERites,
Welcome to 2019. If anyone is interested in headed into the lion's den, see
below.
Cheers
Jack
-- Forwarded message -
From: Pieter Mosterman
Date: Mon, 7 Jan 2019 at 07:27
Subject: [CFP] MathWorks Summer Research Internships
To:
Dear All,
My sincere apologies
Hi Franco,
Good catch, thanks -- try now.
Cheers
Jack
On Mon, 7 Jan 2019 at 10:02 Franco wrote:
> Hi all,
>
> I was searching for some memos in the CASPER wiki (
> https://casper.ssl.berkeley.edu/wiki/Memos) and I noticed that some of
> the links are broken (they give me 404 Not Found Error).
Hi Zhang,
Sorry for the late reply, your mail somehow went to my spam folder.
Installing from https://github.com/casper-astro/casperfpga should work via:
pip install -r requirements.txt
python setup.py install
For corr, our set up in berkeley uses using katcp 0.5.5 (
https://pypi.org/project/kat
Hi CASPERites,
I know a few of you have been playing around with the VCU118 Virtex
Ultrascale Plus dev board. For a while the toolflow has been able to
compile designs for this board, but without any support for accessing the
software registers / brams in the generated bitstream (making the toolfl
brian ?
>
> dan
>
>
> On Mon, Jan 14, 2019 at 7:23 PM Jack Hickish
> wrote:
>
>> Hi CASPERites,
>>
>> I know a few of you have been playing around with the VCU118 Virtex
>> Ultrascale Plus dev board. For a while the toolflow has been able to
>
_to_ram_and_program() caveat.
> >
> > Kind regards,
> >
> > Adam Isaacson
> > South African Radio Astronomy Observatory (SARAO)
> > Hardware Manager
> > Cell: (+27) 825639602
> > Tel: (+27) 215067300
> > email: aisaac...@ska.ac.za
> >
&g
201 - 300 of 607 matches
Mail list logo
