The Simulink warnings I'd be inclined to ignore.
"*Warning: git not found" *probably indicates that the toolflow is trying
to use git to determine the repository state but can't. Do you have git
installed? I would have thought you did, if you cloned the mlib_devel
repository from github, but maybe
Hmmm. Well, my guess is, if the bof file looks like it's working, then
everything is fine. You'd have to dig through the underlying code to see
when/where/how various binaries get created and figure out which ones
matter.
Cheers
Jack
On Tue, 30 Aug 2022 at 04:54, Bartholemew Kuma wrote:
> Hi Ja
Hi Wang,
If you haven't seen it already, this memo is probably useful --
https://github.com/casper-astro/publications/blob/master/Memos/files/Black_box_memo.pdf
The PCORE yellow block doesn't contain anything because it doesn't actually
do anything in FPGA logic. All it does is tells the toolflow
On Sun, 25 Sept 2022 at 15:54, Wang wrote:
> Hi CASPER，
>
> I am currently operating as described in the PAPER Correlator Manifest.
> This is my first time using Ruby.
> I get the source code by way of 'git clone
> http://astro.berkeley.edu/~davidm/rb-katcp.git' failure.Then I used
> 'wget' comma
Hi Nurzhan,
Have you seen the Getting started wiki page --
https://casper.astro.berkeley.edu/wiki/Getting_Started_with_ROACH2 -- and
tutorials --
https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/roach/tut_intro.html
?
These are probably the right places to start. From
On Wed, 30 Nov 2022 at 17:18, 'Jonathan Weintroub' via
casper@lists.berkeley.edu wrote:
> Hi Mitch,
>
> Your answer helps a lot, thanks! I think the existence of the old 100
> standard explains conflicting information found on google search.
>
> To constrain the scenario a bit: we don’t want to
Hi Jason,
If you look underneath the RFDC yellow block, the gateways should have
names which include a prefix which is the model name + RFDC block name. Are
these correct in your broken models, or do they reflect a previous model
name?
If they are wrong, does creating a new RFDC block and reconfig
Hi Wang,
This is strange and concerning (the ROACH2 branch of mlib_devel should be
the reliable one!) but glad you found a fix (and thanks for posting a link
to the repo that worked for you)
Cheers
Jack
On Wed, 7 Jun 2023 at 10:32, Wang wrote:
> Hi everyone,
>
> I solved this problem by using
ou for the help!
>
> Heystek
>
> -
> Heystek Grobler
>
> 0832721009
> heystekgrob...@gmail.com
>
>
> On 01 Oct 2023, at 14:12, Jack Hickish wrote:
>
> Not quite sure what to make of this, but I don't see anything for SysGen /
> M
iversity gets the
> Xilinx ML Enterprise Edition and SysGen or should something else be added
> to it?
>
> Thank you for the help!
>
> Heystek
> -
> Heystek Grobler
>
> 0832721009
> heystekgrob...@gmail.com
>
This seems like a fun "discuss at the workshop" topic!
I have a couple of applications where I think this functionality would be
useful, so I'd definitely be interested in helping out.
>From a toolflow side I think getting the automated instantiation of the DMA
IP should be relatively straightforw
Hi Kaj,
I have KRM support at https://github.com/realtimeradio/mlib_devel/tree/souk
if that's useful.
I've probably diverged a bit from the main mlib repo though - probably some
of the hacks I used to support the board are no longer required now the
rfdc block is increasingly mature
Cheers
Jack
he visible differences is in
> RFDC only.
>
> Have you succeeded to port casperfpga and RFDC drivers to Petalinux/Pynq?
>
I use casperfpga, but not pynq. But I do have a viable Linux image, which
obviously you are welcome to.
Cheers
Jack
> Thanks!
>
> Kaj
>
> On 11.10.20
Howdy,
I think probably the first thing to do is make sure the board really is
booting, and running a katcp server on port 7147.
If the board side of the connection is working, you should be able to
connect to the ROACH over telnet:
```
telnet 10.42.0.226 7147
?help
```
If this does not connect
Hi casperites,
I'm hoping someone can help me out of a JESD204C subclass 1 synchronization
hell. There is a long version of this story, but the short version is:
1. I have an AD9082-FMCA-EBZ development board (hosting an AD9082 ADC+DAC
chip) being used with an iWave ZU11 development board.
2. I'm
if
the receiver isn't being used.
It looks like this was fixed in the ADI linux drivers a while back, but
alas not in the version I was using.
Thanks to everyone who reached out with suggestions / commiserations.
Cheers
Jack
On Sat, 24 Feb 2024 at 17:30, Jack Hickish wrote:
> Hi ca
I think this might be a mismatch between the Ethernet memory map compiled
into the firmware vs expected by casperfpga. What version of casperfpga are
you using?
Cheers
Jack
On Wed, 28 Feb 2024 at 15:25, Sivakumar Sivasankar
wrote:
> Dear Caspers,
> I am a research student at FIU, curren
.dev1336+py38.276ee44
>
> Do I need to change the casperfpga version?
>
> Sivasankar.S
>
> On Wed, Feb 28, 2024 at 9:28 PM Jack Hickish
> wrote:
>
>> I think this might be a mismatch between the Ethernet memory map compiled
>> into the firmware vs expected by cas
attached
> the ss of the error below. Is this error also coming because of the
> casperfpga version? Could you please give any suggestions regarding this
> issue?
> Thank you so much for your valuable time
>
> Sivasankar.S
>
> On Wed, Feb 28, 2024 at 11:45 PM Jack Hickish
&
Hi all,
For anyone interested, there are two postdoc scholarships at the SETI
Institute currently accepting applications. One is in astrobiology, the
other in technosignatures.
See https://www.seti.org/postdoctoral-fellowships-seti-institute for more
info!
Cheers
Jack
--
You received this mess
On Mon, 11 Mar 2024 at 08:47, Kaj Wiik wrote:
> Hi all,
>
> Somewhat related to the previous question: how to define and use (RFSoC)
> pins as GPIOs via the gpio block?
>
> I noticed that group 'led' is in both gpio block mask and in .yaml but
> e.g. there is 'pmod' group in rfsoc4x2.yaml but it
Hi Will,
Sure -- how about 10am toronto time tomorrow?
Cheers
Jack
On Tue, 21 May 2024 at 21:21, Will Taylor
wrote:
> Hi,
>
> I'm starting a project to add the tool-chain support for the 16-bit ADC,
> 50Ohm version of Red Pitaya. I will need to add support for the board
> itself and the ADC pe
Hi Steve,
Is 11.5 actually unsupported, or is it just a case statement that needs
adding to the bee_xps.m file. I remember Griffin had a similar problem when
he set up our first 11.4 machine -- he just added the last case in that
switch. (Detailed here http://casper.berkeley.edu/wiki/Xilinx_ISE_11
Hi all,
I'm experimenting with some black boxed state machines to simplify some of
the control logic in my designs. I thought I had it sussed, until I tried a
black box with a 64 bit wide input bus. The HDL seems unable to see the top
32 bits of the input, and simulink refuses to recognise any of
e and black boxing that also
seemed to solve the problem.
All mighty suspicious, but semi-solved, at least.
Cheers,
Jack
On Mon, Apr 26, 2010 at 8:20 PM, Jack Hickish wrote:
> Hi all,
>
> I'm experimenting with some black boxed state machines to simplify some of
> the control
Hi Jason
1) Hope SA is treating you well
2) Sorry to send this to you and not the maillist, but I thought before I
demonstrate my complete lack of knowledge about ethernet/switches to the
world, I should float the idea with you first.
Quick correlator question --
Am I right in thinking the loopb
And that folks, did not go to plan.
:-(
Regarding multirate support from the toolflow - the system generator token
seems to have various options for multirate implementation (the default of
which is clock enables).
On reading the system generator help file, my take is that the "hybrid
DCM-CE" mode will instantiate a DCM that can drive u
Hi all,
I've been playing around with the GPIO on a ROACH, and just to ease my
curiosity, can anyone tell me what the pins that are driven by the
gpiox_oe_n blocks actually *do*?
Anyone with an answer will surely save me many sleepless nights of idle
wondering...
Cheers,
Jack
different I/O banks, so
> they are all at different voltages. To make them all a uniform 3.3V,
> they go through unidirectional level translators; the gpiox_oe_n
> signals control the drive directions of these translators.
>
> Cheers,
> Henry
>
>
> On 8/27/2010 5:50
Hi,
After a compile fails, it's worth checking the timing report in the compile
directory /XPS_ROACH_BASE/implementation/system.twr
Whilst a little bit cryptic, the report should at least give you some idea
of which bits of the design are causing timing failure. It becomes
reasonably clear if
Hi,
Have you tried the old 'set the clock pin location to d7' trick?
See here: http://casper.berkeley.edu/astrobaki/index.php/CasperTutorial01 --
Section 2.1
Cheers,
Jack
On 3 September 2010 18:34, wrote:
> I am sorry I didn't provide more detail. I
> have Matlab 2009a, Xilinx 11.4 (upgr
Hi Dave,
I remember an issue with borph hanging on read/writes, which the mail
archive suggests you may have solved. Could you just confirm -- does the
current version of 10.1 in the git repo successfully create bof files that
work with the BEE2?
Cheers,
Jack
On 14 October 2010 12:09, David Ma
mble to
> read out in the expected order. I'll think about this a little more. Thanks
> for bringing it to my attention.
>
> Jason
>
> On 19 Oct 2010, at 22:37, Jack Hickish wrote:
>
> > Hi All,
> >
> > After some bizarre cross-pol results in a recent o
Hi Glenn,
I noticed the same thing as you re. DSP use in the X-engine, and went about
making a new complex multiply block which performs two 4x4 bit multiplies
per DSP slice by concatenating inputs together, and therefore uses 2 DSPs
per Cmult. This was pretty simple, though I suspect the adders n
Hi Patrick,
You should be able to configure the xport IP address from the "Network"
section of the web interface -- I think the default address is
http://192.168.4.20 -- You should be able to log in as root without a
password.
Cheers,
Jack
On 23 March 2011 19:10, Patrick Brandt wrote:
> H
Hi Casperites,
After a long day of debugging an FFT spectrum yesterday, I got down to
basics and compared the output of the 8-pt direct fft block with matlab's
fft function. When I used random numbers as the inputs it quickly became
apparant that they didn't match.
After a little more investigati
Hi Miguel,
I think the "General ROACH Instructions" that you're reading were written
specifically for the CASPER workshop in Harvard last year, where there were
some servers / ROACHs already set up. If you're trying to run your design on
a ROACH in your own setup, a few of the details may be sligh
Hi Jesús,
If you're using the dac_4x block, which is designed for a DAC running at 4x
the "simulink clock", you're going to have problems if you want to run both
the FPGA and the DAC at 150MHz.
If you really want to do this, I guess you can make a new yellow block (
https://casper.berkeley.edu/wik
oot
> >> attached).
> >> The matlab command windows shows "Running mask script for adc083000
> >> untitled/adc083000x2", but the block pins are not updated and the
> >> error still there.
> >>
> >> cheers,
> >>
> &g
Hi Louis,
The error you describe sounds similar to that encountered when trying to
compile on Ubuntu -- see here:
http://www.mail-archive.com/casper@lists.berkeley.edu/msg01224.html
Are you using Centos/RHEL/one of the supported OSs?
Cheers,
Jack
On 13 July 2011 23:10, Louis Dartez wrote:
>
'm thinking CentOS...
>
> - Louis Dartez
> (956) 372-5812
>
> Arecibo Remote Command Center Scholar
> Center for Gravitational Wave Astronomy
> University of Texas at Brownsville
>
>
> On 7/13/11 5:32 PM, Jack Hickish wrote:
>
> Hi Louis,
>
> The error yo
Hi All,
Just a quick update on this issue which I discovered about a year ago. It
would seem that black-boxed verilog inputs over 32 bits wide work fine in
System Generator 13.2.
I hope this brings some others as much joy as it brings me.
Cheers,
Jack
On 28 April 2010 16:57, Jack Hickish
Hi Nimish,
Is there a chance that your toolflow is not set up with the "new" pin
mapping, mentioned in the bottom of the GPIO page. If you're on the old
mapping then I guess the SMAs will map to GPIOs 4 and 5. Might be worth
checking to see if your pulse which should be on 7 is coming out on 4.
I
Hi Srikanth,
You can find it in the xps_library at:
http://www-astro.physics.ox.ac.uk/~FosterG/casper/oxford_devel.git which is
the Oxford repo (and includes relatively recent pulls from all the public
mlib_devel branches at various institutions.
I'll try and get the block included in the github r
Hi Devon,
Just had a quick look at your mdl file. Looks like you're holding the
qdr_vacc write enable signal high - I'm pretty sure the block only lets you
read out an accumulation on the cycles when the qdr_vacc input isn't valid.
On the clocks when the input data is valid, the qdr read cycles ar
Hey Ricardo,
Can't say I've tried, but it looks like changing (or adding a new case) to
mlib_devel/xps_library/xps_xsg_conf_mask.m should achieve what you
want. The sx95t speed grade looks to be set on line 93.
Cheers,
Jack
On 12 April 2012 23:49, Ricardo Finger wrote:
> Hello All,
>
> D
Hi all,
After a fair bit of tutorial related pain on the mailist recently, I've
just forked the tutorial-devel repo to
https://github.com/jack-h/tutorials_devel and recompiled tutorials 1-3 with
Sysgen 11.5 and the libraries in the main casper github repo.
The tutorials in the 2011 directory *sho
>
> XPS% Evaluating file run_xps.tcl
> ERROR:EDK - Load a MHS or XMP file first
> Error using ==> gen_xps_files at 686
> XPS failed.
>
> -
>
> Looks like something in the BRAM block is causing the hiccups.
> Thanks for looking into this.
>
> Best
On 11 May 2012 03:07, Gopal Narayanan wrote:
> Hi Jack,
>
> All is well now. I indeed had placed the pcore files in the wrong
> directory, one above the required pcores subdirectory. Now it compiles
> all the way through. My mistake!
>
> Thanks a lot for your help.
>
> Best Regards,
> Gopal
>
>
>
Hi Devon,
You should be able to (at least in the latest casper libs) access aux0_clk
and aux1_clk with the GPIO yellow block, though I can't say I've actually
ever used this functionality. No reason to expect it won't just do what it
says on the tin, though :-)
Cheers,
Jack
On 15 June 2012 16:1
Hi Alexander,
On 20 July 2012 00:21, Alexander Mouschovias wrote:
> Hi guys,
>
> I'm working with tutorial 4 from the 2011 workshop (available at
> https://github.com/jack-h/tutorials_devel). In the get_data function from
> poco_plot_cross.py, it seems to me that a_0r=b_0r, a_1i=b_1i, etc. At le
Hi Matt,
Looking at your model, you have write enable pulses coinciding with every
second address location. Even though a write enable pulse writes two 36 bit
values, each address location addresses a full 72 bit data burst, so if you
want to write the entire qdr you need to increment the address
Hi All,
On 17 September 2012 09:34, Jason Manley wrote:
> It does seem odd that this happens every X accumulations. That almost
> sounds like a problem with the readout software. There's nothing I can
> think of in the design that changes on those timescales, unless there is a
> beat frequency b
I've just pushed a fix (and boffile) to the tutorials-devel git repo
On 17 September 2012 13:03, Jason Manley wrote:
> On 17 Sep 2012, at 11:45, Jack Hickish wrote:
> > 2^27 isn't a valid sync period for tut3, which has an FFT ending in a
> 10th order reorder (https://cas
appreciated.
>
> Thanks,
>
> Jason Castro
> NRAO
>
>
>
>
> On 9/17/2012 8:03 AM, Jason Manley wrote:
>
>> On 17 Sep 2012, at 11:45, Jack Hickish wrote:
>>
>>> 2^27 isn't a valid sync period for tut3, which has an FFT ending in a
>>> 1
ASPER/Spectrometer/Tutorial_3_sliding_spectrum1.PNG
> >
> ftp://ftp.cv.nrao.edu/NRAO-staff/jcastro/CASPER/Spectrometer/Tutorial_3_sliding_spectrum2.PNG
> >
> > I'll dive into this and try to figure out what's going on, but extra
> > eyes are appreciated.
> >
> > Thanks
Ki Kaz,
running "yum provides libexpat.so.0" suggests that (at least on my Fedora
install) the libexpat.so.0 is available in the compat-expat1-1.95.8-7.i686
package, so a "yum install compat-expat1-1.95.8-7.i686" would get it.
I think on ubuntu there is no source of libexpat.so.0 (it's an old
lib
Hi Katty,
It seems there's a block not linking properly to your casper libraries. I'd
suggest the first thing to try is just to delete the FFT blocks from your
model and drop fresh ones back in from the CASPER library.
Cheers,
Jack
On 9 November 2012 20:54, katherine viviana cortes urbina <
kat
I believe an initialization failure amounts to an error whilst running the
block mask script. If you run the mask script manually on your new yellow
block from the matlab command line, if it fails, it should at least tell
you something useful.
On 14 November 2012 09:59, Alex Zahn wrote:
> Hi al
clock/simple_
>trigger/XPS_ROACH_base/system.mhs line 279 - cannot find MPD for the
> pcore
>
> Any ideas?
>
> -Alex
>
>
> On Wed, Nov 14, 2012 at 3:54 AM, Jack Hickish wrote:
>
>> I believe an initialization failure amounts to an error whilst running
>&
Hey Jeff, Ioana
Probably worth mentioning that that python script mainly existed because
the ROACH 1 didn't have access to a 100mb Ethernet connection except via
the powerPC. ROACH 2 has a dedicated fpga-side 1000(?)mb/s interface.
Depending on your application, you might consider using this for o
Hi Ioana,
I'm attaching a model and python script that Guy Kenfack and I knocked
together worked on at the Green Bank workshop. We sent a counter and saw
the data at the right IP/port in wireshark.
A question to anyone in the know: is there a runtime way to configure the
source IP/mac settings on
Excellent. Thanks for the info.
Jack
On Jan 22, 2013 5:01 AM, "Henno Kriel" wrote:
> Hi
>
> The 1GbE core is configured to work in the same way as the 10GbE core with
> regards to tgtap.
>
> Regards
> Henno
>
> On Mon, Jan 21, 2013 at 3:52 PM, Marc Welz wrote:
>
>> Hello
>>
>> > A question to a
Hey David,
That controller address was used for the software calibration of the ROACH
2 QDR interface. It appears that hardware calibration has since been
implemented on ROACH 2, leaving that register superfluous for all of the
ROACH platforms.
However, digging through the library, calibration fla
of the oxfork github repository. I've left the full 64KB mapped for
now.
On 31 January 2013 17:24, David MacMahon wrote:
> Hi, Jack,
>
> Thanks for your helpful reply!
>
> On Jan 31, 2013, at 2:01 AM, Jack Hickish wrote:
>
> > However, digging through the library, calibrati
Hi All,
Is someone able to confirm that the size of the QDR chips on ROACH 1 boards
depends solely on the board version? If this is indeed the case, does
anyone know the QDR specs for the different board iterations?
Cheers,
Jack
; Hope this helps,
> Dave
>
> On Mar 1, 2013, at 12:27 AM, Jack Hickish wrote:
>
> > Hi All,
> >
> > Is someone able to confirm that the size of the QDR chips on ROACH 1
> boards depends solely on the board version? If this is indeed the case,
> does anyone know the QDR specs for the different board iterations?
> >
> >
> > Cheers,
> > Jack
>
>
Hi All,
In case it is of interest to any of you (or those you know), this July
Oxford University will be hosting the first of a series of annual
summer schools covering the complete signal processing chains found in
21st century scientific instrumentation. The series aims to be cross
disciplinary,
Hi all,
Sorry to spam, but I thought this may be of interest to some of those on
the maillist. Cambridge University are looking for a research associate in
astronomical DSP. See the link below for details.
http://www.mrao.cam.ac.uk/jobs/research-associate-in-digital-signal-processing/
Cheers,
Ja
Hi Ross,
Have you looked upstream at, eg, the FFT output, to check there is a single
spike coming out of that? Might also be worth making sure that you are
simulating a sync pulse, and waiting long enough for data after the sync to
propagate all the way through the design.
Cheers,
Jack
On 15 Ma
Hey Katty, Laura
> If you produced this bof file from a Simulink model, you can look in the
> model to find the correct register.
>
> Alternatively, you can log into your roach and run your .bof file as an
> executable. When you see the process id, you can actually navigate to a
> folder that w
> > 3) Is there A Better Way not involving 10 gbe?
>
> Switch to ROACH2? :-)
>
>
How hard would it be to knock up an ethernet connection over GPIO? :)
Hullo,
So first of all -- That appears to be my commit, so sorry. I'll fix it in
the vanilla fork of the oxford github repo when i get into work this
morning.
FWIW, I believe core_info.tab on ROACH2 also has control addresses which
are wrong. Or rather, are out of date now the ROACH2 QDR module h
out of both QDR blocks.
FWIW, the qdrX_ctrl addresses were already updated a few months ago (there
was an email thread about it iirc) but never propagated to casper-astro.
Cheers,
Jack
On 4 June 2013 09:40, Jack Hickish wrote:
> Hullo,
>
> So first of all -- That appears to be my commit,
Hey David,
The verilog for the yellow block is available but (as far as i know)
untested on ROACH 2. The code / block is all available in
https://github.com/oxfork/mlib_devel/
Feel free to improve it :-)
Cheers,
Jack
On 5 June 2013 17:39, David Saroff wrote:
> Does anyone have experience an
On 10 June 2013 17:07, David Saroff wrote:
> Short of compiling a design, can the resource usage of a PFB yellow block
> be seen?
> If the data rate is some submultiple of the FPGA clock, say 50 MSPS and
> 200 MHz is there a natural way to share resources?
>
> The question's context:
> 38 dipol
Hey David,
What libraries and tool versions are you using, and what error do you get?
Cheers,
Jack
On 4 July 2013 21:00, David Saroff wrote:
> Casper folks,
>
> A fresh copy of tut3.mdl from the wiki does not build, in the
> matlab/simulink/casper_xps setup given to me by our system administrat
Hey Jeff,
Quick and easy check -- have you the clock speed by looking at the DCM
instantiation in system.mhs
If you're using arb_clk to make 202MHz then the tools will find an
integer multiplier and divisor to match close to your target speed. I
don't know what the criteria for this selection is
Hi John,
I doubt this is your problem if it doesn't show up in simulation, but
in the past I've had problems when using the cmult_dsp48 multiplier
block (in addition to what danny mentioned). I don't know about the
current CASPER libraries, but I've seen some FFT-related blocks in the
past configu
Hi Rich,
In hoping to get a yellow block tutorial up and running (there is a
tutorial Dave George wrote a few years ago which I'll use as a starting
point), probably based around a bidirectional gpio block. But if you (or
anyone else) have any thoughts or requests, do get in touch.
Cheers,
Jack
O
On 22 Jul 2013 18:00, "John Ford" wrote:
>
> > Hi Rich,
> >
> > In hoping to get a yellow block tutorial up and running (there is a
> > tutorial Dave George wrote a few years ago which I'll use as a starting
> > point), probably based around a bidirectional gpio block. But if you (or
> > anyone el
Hi David,
Just duplicating the email I sent you off list on the offchance it's
useful to someone on the maillist in the future.
My versions for the ADC64x64-12 (64 inputs, 64 MSa/s, 12 bits) are
(https://casper.berkeley.edu/wiki/64ADCx64-12)
(https://casper.berkeley.edu/wiki/X64_adc)
MATLAB -- 2
Hi Tim,
The ska-sa repo is *much* more up-to-date than the casper-astro repo,
which still uses the old file naming conventions / directory
structures.
With the casper conference coming up in a couple of weeks, the
tutorials are being updated to work with the ska-sa master branch. The
official cas
Hi David,
The block should have an initialization script which renames the
underlying gateway blocks to have the correct names. It would appear
this isn't working as it should.
The script should live in the xps_library subdirectory in mlib_devel,
and should be referenced in the "initialization" s
If you're really desperate, presumably someone on this list with a license
can precompile the fft block for you, which you could then black box? Or
generate the block, disable the init script, and send it to you?
Not necessarily suggesting that this is a better strategy than just
reverting your li
;
> Nimish
>
>
> On Thu, Sep 26, 2013 at 9:28 AM, Jack Hickish wrote:
>
>> If you're really desperate, presumably someone on this list with a
>> license can precompile the fft block for you, which you could then black
>> box? Or generate the block, disable the i
Hi all,
We were using 14.3 at the JBO workshop a few weeks ago -- partly because of
cautionary tales I heard about 14.4, and partly because of license expiry
date constraints (i.e. 14.3 was the latest version the spare Oxford
licenses supported).
Cheers,
Jack
On 1 Oct 2013 12:56, "Jason Manley"
Hey Andrea,
I think (http://www.xilinx.com/support/answers/23165.html) the ngc
file is all you're going to get, unless you run the compile again with
the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to 1.
Your error is some specific component that has impossible timing
constraints -- it's not just ge
Hi all,
I'm considering an application for ROACH2 which would require a load
of point-to-point 10Gb/s connections. Has anyone got XAUI running on
ROACH2 with either of the available mezzanine cards? If not, are there
likely to be any major obstacles to getting this working?
Cheers,
Jack
Thanks, all,
Food for thought...
(I'm trying to weigh up the pros and cons of using a cheaper
switchless correlator but having to make more custom firmware vs just
using a switch and participating in mass IP theft from various CASPER
github repos)
Cheers,
Jack
On 6 November 2013 13:45, Andrew M
Hi Bodow,
Are you using the Casper libraries linked at the top of the tutorials wiki
page? If not, you may find that some blocks in the tutorial are out of date
compared to the library you are using.
The simplest way to fix this is to replace the offending block in the model
(the error message sh
Howdy,
I've seen a few old documents (eg.
https://casper.berkeley.edu/wiki/images/3/30/3ghz_spec_library_design.pdf)
which suggest that somewhere there might exist an automated floor
planner for some version of the CASPER FFT.
Does such a marvellous thing actually exist in (partially?) working
fo
imitives on the FPGA fabric. I really thank Ryan for sending his memo, but
> I want to say to him that I'm using it to understand this kind of works
> since a couple of weeks. Therefore, I want to say that my goals are: make
> the speed optimization to closing timing on an FPGA de
Hi all,
Like Weiwei, I'm trying to use the ADC5g at 5 Gsps. I've played with a
simple ADC to snap model, and (as Rurik warned) getting reliable data
capturing is difficult at this speed. I've tried per-bit calibration
of input data streams via IODELAYs in conjunction with phase-shifting
of the sam
f times but in the
> end I've just eaten that 500MHz of BW as too much effort for the
> little gain it gives in receiver noise. I would say that on a
> Roach-1, two boards at 5GSPS (4-bit) works fine if you are just
> dumping data to a snapshot. I believe a ROACH-2 is harder to
erged quite a lot, but I've attached a
patch to peruse/edit/merge at your leisure. Obviously, YMMV :)
Cheers,
Jack
>
> Thanks!
> Rurik
>
> On Wed, Jan 15, 2014 at 7:51 AM, Jack Hickish wrote:
>> Hi Ross,
>>
>> Thanks for the info -- I've actually got a 5 Gsps
modification. That would be a BIG help for my
> project. Thanks!
>
> Best,
>
> Weiwei
>
>
> On Wed, Jan 15, 2014 at 9:53 AM, Jack Hickish wrote:
>>
>> On 15 January 2014 16:28, Primiani, Rurik
>> wrote:
>> > Hi Jack,
>> >
>>
Hi all,
I expect many of you know about and may be using this feature, but
every time you save a model, Simulink can be configured to prompt you
to enter a changelog comment.
See
http://www.mathworks.co.uk/help/simulink/ug/managing-model-versions.html#f4-140406
for details
On the off chance tha
I'm not sure what, if any, difference a subsystem will make to the
mapped design (I thought none), but I believe it's the case that
changing module names etc. can affect the place and route algorithm's
start seed. I seem to remember seeing this mentioned in a Xilinx doc
under the heading "I've save
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