f focuded FS implementation would get
it done (given you have the other models for reference).
On Wed, Mar 2, 2011 at 12:55 PM, Ali Saidi wrote:
On Wed, 02 Mar 2011 12:20:52 +, Timothy M Jones <
timothy.jo...@cl.cam.ac.uk> wrote:
Hi Korey (primarily),
Could you give me a brief summary
Hi Korey (primarily),
Could you give me a brief summary of which ISAs work with inorder CPU in
full-system mode, to the best of your knowledge? I'm just starting a
new project and the inorder CPU would be a good fit for it, but I need
to know the constraints on it.
Cheers
Tim
--
Timo
changeset 4a59661d3fd1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4a59661d3fd1
description:
O3CPU: Fix iqCount and lsqCount SMT fetch policies.
Fixes two of the SMT fetch policies in O3CPU that were returning the
count
of instructions in the IQ or LS
Hi Ali,
Could you tell me roughly what the status of ARM support is for
full-system simulation? I'm thinking of using M5 ARM for a future
project (which won't start until sometime next year) and I will want a
simulator that I can run Linux on.
Cheers
Tim
--
Timothy M.
I can.
Cheers
Tim
On Wed, 27 Oct 2010 01:16:16 -0400, Ali Saidi wrote:
Hi Tim,
You have several changes on review board that have been there for about
three months. Are these changes still pending/valid? What do we need to
get them committed?
Thanks,
Ali
--
Timoth
oo
much about it at the time.
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
___
m5-dev mailing list
m5-dev@m5sim.org
h
.
Cheers
Tim
On Wed, 04 Aug 2010 23:36:25 -0400, Korey Sewell wrote:
I havent brushed up on the O3CPU code in awhile but why the 1st thing
that
seems suspicious is "Squashing from PC 0"... How is that happening? Is a
branch at "PC 0" really committing?
On Wed, Aug 4, 2010 at
e stage?) and
I'll write a fix for it.
Cheers
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
___
m5-dev mailing l
On Mon, 02 Aug 2010 23:16:15 -0400, Ali Saidi wrote:
On Aug 2, 2010, at 8:08 PM, Timothy M Jones wrote:
Hi everyone,
On 18/07/2010 10:46, Korey Sewell wrote:
That seems odd... I assume you're suggesting that Tim switch the
InOrderCPU to pass the PC instead, right?
Yep
e original code was using
inst->readPC() for the DPRINTFs.
Shall I fix up the interface so it's a little more clear what's required
and alter both CPUs to pass in the current PC, not next PC?
Cheers
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The Univer
On Thu, 22 Jul 2010 16:35:10 -0400, Steve Reinhardt
wrote:
On Thu, Jul 22, 2010 at 1:12 PM, Timothy M Jones
wrote:
So, after all this, which version do you want me to implement? TID or
ASID?
I'll have a go at either.
I think you should go with the TID since that's
ame asid or maybe some type of allocation of BTB
entries
per thread, but it would be interesting to see what (if anything) people
do
for this.
So, after all this, which version do you want me to implement? TID or
ASID? I'll have a go at either.
Cheers
Tim
--
Timothy M. Jones
http://h
hu, 22 Jul 2010 14:30:56 -0400, Gabe Black
wrote:
I think you missed my point. If the check of TheISA::HasUnalignedMemAcc
is redundant, we shouldn't be checking it at all. It's a free, though
very small, performance bump, but more significantly it removes a direct
dependence o
few other changes I noticed wraps to the second line
which is a no-no. In the future, please keep it to one line even if you
have to leave out details, and then be complete with the other lines.
Gabe
Timothy M. Jones wrote:
changeset ffac9df60637 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd
changeset ffac9df60637 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ffac9df60637
description:
Power: The condition register should be set or cleared upon a system
call
return to indicate success or failure.
diffstat:
src/arch/power/miscregs.hh | 7 ++-
changeset bd104adbf04d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bd104adbf04d
description:
LSQ Unit: After deleting part of a split request, set it to NULL so
that it
isn't accidentally deleted again later (causing a segmentation fault).
diffstat:
src/cp
changeset fb7fc9aca918 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fb7fc9aca918
description:
Port: Only indicate that a SimpleTimingPort is drained if its send
event is
not scheduled, as well as the transmit list being empty.
diffstat:
src/mem/cache/cache_
changeset 3bd51d6ac9ef in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3bd51d6ac9ef
description:
O3CPU: Fix a bug where stores in the cpu where never marked as split.
diffstat:
src/cpu/o3/lsq_unit.hh | 6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diffs
changeset 02b471d9d400 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=02b471d9d400
description:
Syscall: Don't close the simulator's standard file descriptors.
diffstat:
src/sim/syscall_emul.cc | 5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diffs (15 li
changeset b1ac6773e83d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b1ac6773e83d
description:
O3CPU: O3's tick event gets squashed when it is switched out. When
repeatedly
switching between O3 and another CPU, O3's tick event might still be
scheduled
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ * Stephen Hines
+ * Timothy M. Jones
+ */
+
+#include "arch/power/utility.hh"
+
+namespace PowerISA {
+
+void
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
___
bear this in mind.
Cheers
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
.org/r/57/
Does that sound ok to everyone?
Cheers
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
ing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
___
m5-dev mail
__
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of
d on the review board) and you can try out the sampling for
yourselves too :-)
Cheers
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
__
Hi all,
Can anyone tell me how to retrieve my password for the review board? I've
just accidentally logged out and can't find any sort of 'Forgotten
password' link or anything of that kind. My user name is tmjones, if that
helps.
Cheers
Tim
--
T
On 06/07/2010 17:43, Ali Saidi wrote:
On 7/6/10 1:22 PM, "Timothy M Jones" wrote:
Hi everyone,
For a while now I've been trying to implement SMARTS-like simulation
within M5. I'm almost there now but am stuck on one particular part.
For SMARTS simulation we repeatedly
ll the relevant queues are empty would be the right thing to
do).
On Tue, Jul 6, 2010 at 2:22 PM, Timothy M Jones mailto:tjon...@inf.ed.ac.uk>> wrote:
Hi everyone,
For a while now I've been trying to implement SMARTS-like simulation
within M5. I'm almost there now but a
switching from Atomic to O3. Since Atomic
doesn't have a drain function, it simulates forever.
Are either of these solutions the best way to solve this problem and if
so, which is the path I should continue to pursue? Or, is there a third
option that I haven't thought about?
changeset 91994f36de7f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=91994f36de7f
description:
O3ThreadContext: When taking over from a previous context, only assert
that
the system pointers match in Full System mode.
diffstat:
src/cpu/o3/thread_context_impl
Cheers
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
out, and run with that. I'm not sure how Gabe selected the x86
platform. For the ARM platform that I'm working on at the moment, I'll
be selecting a platform ARM developed.
Ali
On May 3, 2010, at 2:24 PM, Timothy M Jones wrote:
Hi everyone,
I'm (slowly) trying to get f
start!
Cheers
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
ependent on how complex these items
>> are
>> in Power and how similar some are to existing ISAs support, and half
>> dependent on your strategy for validating your implementation. With
>> SPARC
>> we used the golden brick method from the start, with Alpha/Tsunami w
different
> properties? For instance, what if someone reads at a page boundary
> where one page is cacheable and the other isn't?
>
> Gabe
>
> Quoting "Timothy M. Jones" :
>
>> changeset a06e95c99294 in /z/repo/m5
>> details: http://repo.m5sim.org/m5?
ould give me a rough estimation
of the time they expect it to take too, then that would be great. That
would influence when/if I started to work on it.
Thanks
Tim
--
Timothy M. Jones
http://homepages.inf.ed.ac.uk/tjones1
The University of Edinburgh is a charitable body, registered in
Scotlan
changeset a06e95c99294 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a06e95c99294
description:
CPU: Added comments to address translation classes.
diffstat:
1 file changed, 62 insertions(+), 2 deletions(-)
src/cpu/translation.hh | 64
>
> On Nov 25, 2009, at 3:20 PM, Timothy M. Jones wrote:
>
>> # HG changeset patch
>> # User Timothy M. Jones
>> # Date 1259064162 0
>> # Node ID 77dffd16710c4ad8e308b7dfee75cce4219b30a0
>> # Parent b431ed08a6b7d809df9bfed51365e4d3bdf81f93
>> Cpu: Make
; passed.
>>> *
>>>
>> build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
>>> passed.
>>> * build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
>> passed.
>>> * build/X86_SE/tests/fast/long/2
repository and the
tests failed there too, so I guess there were problems before I introduced
my own!
Cheers
Tim
On Mon, 22 Feb 2010 09:45:41 -0500, Timothy M. Jones
wrote:
> changeset 862a31349d43 in /z/repo/m5
> details: http://repo.m5sim.org/m5?cmd=changeset;node=862a3
changeset 862a31349d43 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=862a31349d43
description:
BaseDynInst: Preserve the faults returned from read and write.
When implementing timing address translations instead of atomic, I
forgot to preserve the fault
my patches that I want to push. Can you look
into
it?
Thanks,
Lisa
On Fri, Feb 12, 2010 at 12:52 PM, Timothy M. Jones
wrote:
changeset 4d4903a3e7c5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4d4903a3e7c5
description:
O3PCU: Split loads and stores that cr
s that I want to push. Can you look
> into
> it?
>
> Thanks,
> Lisa
>
> On Fri, Feb 12, 2010 at 12:52 PM, Timothy M. Jones
> wrote:
>
>> changeset 4d4903a3e7c5 in /z/repo/m5
>> details: http://repo.m5sim.org/m5?cmd=changeset;node=4d4903a3e7c5
>> descriptio
Redistribution and use in source and binary forms, with or without
@@ -26,6 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Timothy M. Jones
*/
#ifndef __CPU_BASE_DYN_INST_HH__
@@ -45,6 +47,7 @@
#include "cpu/in
changeset 4d4903a3e7c5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4d4903a3e7c5
description:
O3PCU: Split loads and stores that cross cache line boundaries.
When each load or store is sent to the LSQ, we check whether it will
cross a
cache line bound
changeset b6482c4c89e3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b6482c4c89e3
description:
Power ISA: Add an alignment fault to Power ISA and check alignment in
TLB.
diffstat:
3 files changed, 48 insertions(+), 2 deletions(-)
src/arch/power/faults.hh | 16 +
far as I can see,
> assuming they still apply cleanly and the regressions pass.
>
> Gabe
>
> Timothy M Jones wrote:
>> Hi everyone,
>>
>> I just realised that I didn't ever actually commit these patches. Does
>> anyone have any problems with them, or can I go ah
else do it once I've pushed the
patch?
Thanks
Tim
On Tue, 15 Dec 2009 05:06:55 -0500, Timothy M Jones
wrote:
> Thanks Kevin. No problem for the delay. I'll update the stats with
> this new patch and then push it. Hopefully that will be in the next
> couple of
heers
Tim
On Mon, 14 Dec 2009 10:10:39 -0500, Timothy M. Jones
wrote:
> These are the updated patches that perform timing TLB translation
> (instead
> of atomic) in base_dyn_inst.hh and then split O3 memory accesses into two
> reads or writes when they cross a cache line bound
pefully it'll help sway
> you one way or another.
>
Yes, definitely, thanks! I'll try to make it a simulation object like you
describe.
Cheers
Tim
> Kevin
>
> Quoting Timothy M Jones :
>
>> Hi all,
>>
>> As I've previously mentioned, I'd l
. I think Kevin would have to speak up to
>> say if there's any intended behavior here or if this is truly a bug.
>>
>> Steve
>>
>> On Tue, Dec 1, 2009 at 7:33 AM, Timothy M Jones
>> wrote:
>>> Hi everyone,
>>>
>>> I'
Hi all,
As I've previously mentioned, I'd like to run simulations using SMARTS
methodology. To do this, I will switch between O3CPU and AtomicSimpleCPU
repeatedly. I need to be able to keep the branch predictor warm when
using Atomic, but at the moment this can't be done.
Does anyone have
# HG changeset patch
# User Timothy M. Jones
# Date 1260799510 0
# Node ID 38f6c527423a57c6fdfbba7ec9533ee68e258045
# Parent 5704723e27609a54c45a7e1ff573c2e5f819044d
O3PCU: Split loads and stores that cross cache line boundaries.
When each load or store is sent to the LSQ, we check whether it
# HG changeset patch
# User Timothy M. Jones
# Date 1260363501 0
# Node ID 5704723e27609a54c45a7e1ff573c2e5f819044d
# Parent 9cc6ac1398a79b7a7e717c42da1fbc2ee6ad8f15
BaseDynInst: Make the TLB translation timing instead of atomic.
This initiates a timing translation and passes the read or write
These are the updated patches that perform timing TLB translation (instead
of atomic) in base_dyn_inst.hh and then split O3 memory accesses into two
reads or writes when they cross a cache line boundary. All regression tests
pass without problems.
Changes from last time:
* Alterations to TimingSi
On Wed, 02 Dec 2009 15:33:27 -, Steve Reinhardt
wrote:
> On Wed, Dec 2, 2009 at 2:01 AM, Timothy M Jones
> wrote:
>> Well, the problem is when you get speculative memory accesses. Even in
>> the ISAs that don't need split loads and stores, an address on a
On Wed, 02 Dec 2009 11:27:47 -, Gabe Black
wrote:
> Timothy M Jones wrote:
>> On Wed, 02 Dec 2009 01:31:03 -, Gabriel Michael Black
>> wrote:
>>
>>
>>> Quoting Timothy M Jones :
>>>
>>>
>>>> Thanks Gabe.
>>>
On Tue, 01 Dec 2009 20:37:57 -, Steve Reinhardt
wrote:
> It looks like you lost the initialization of isUncacheable... is that
> safe?
>
Hm, yes I'll fix that.
> Actually I'm not sure why we need that variable, and don't just have
> BaseDynInst::uncacheable() call req->isUncacheable() di
On Tue, 01 Dec 2009 20:31:09 -, Steve Reinhardt
wrote:
> Looking at just the part I've left below, it looks like you're
> separating out the split vs non-split calls at the top, and then they
> combine back into common functions at the bottom... I think it would
> be cleaner if we got rid o
Hi Steve,
Thanks for the comments.
On Tue, 01 Dec 2009 20:12:19 -, Steve Reinhardt
wrote:
> I'd say the main thing that could be cleaned up here is that you want
> to extend the "ExecContext" interface (see
> http://m5sim.org/wiki/index.php/ExecContext) with the
> finishTranslation() func
On Wed, 02 Dec 2009 01:31:03 -, Gabriel Michael Black
wrote:
> Quoting Timothy M Jones :
>
>> Thanks Gabe.
>>
>> I've run all regressions and there are some that fail. I've checked the
>> differences and it's mainly changes in the number of
Hi everyone,
I've noticed a slight problem in using the branch predictor that's causing
it to update its state with the incorrect outcome of the branch. I'm
looking at O3CPU here. The problem comes in bpred_unit_impl.hh in
predict(). If the BTB doesn't supply a target address, then pred_
; Since changes to the CPUs can affect all ISAs in potentially subtle,
> obscure ways, please run all of the regressions once before submitting
> if you haven't already. Please also give Steve a chance to look this
> over if possible.
>
> Gabe
>
> Timothy M. Jones wrote:
>&
Hi everyone,
I'd like to commit these patches fairly soon. If anyone has any
comments on them, can they get them to me soonish. I'd like to commit
next Monday (7th) if no-one's got any issues with this?
Thanks
Tim
On 25/11/09 15:23, Timothy M Jones wrote:
> I should have s
I should have said, this patch is to be applied on top of these patches:
http://m5sim.org/mailman/private/m5-dev/2009-November/007714.html
Tim
On Wed, 25 Nov 2009 15:20:01 -, Timothy M. Jones
wrote:
> # HG changeset patch
> # User Timothy M. Jones
> # Date 1259064162 0
&g
# HG changeset patch
# User Timothy M. Jones
# Date 1259064162 0
# Node ID 77dffd16710c4ad8e308b7dfee75cce4219b30a0
# Parent b431ed08a6b7d809df9bfed51365e4d3bdf81f93
Cpu: Make TimingSimpleCPU use new DTB translation code.
This patch removes the duplicate code from cpu/simple/timing.hh and makes
Hi everyone,
I'd like to be able to simulate benchmarks using SMARTS. Does anyone have
any experience doing this with M5? From what I can see, there needs to be
the following changes made to get this working correctly. Please can you
let me know if any of this is already available!
1) Allowing th
remain? I'd prefer not to have to copies of
> the same code floating around.
>
> Nate
>
> On Mon, Nov 9, 2009 at 5:30 AM, Timothy M. Jones
> wrote:
>> # HG changeset patch
>> # User Timothy M. Jones
>> # Date 1257772288 0
>> # Node ID
# HG changeset patch
# User Timothy M. Jones
# Date 1257772288 0
# Node ID 1c63ee4b8afa271d3ae645419e37913bbb97fe6b
# Parent da27e67385cca6cf4dd6d18cdead5cfd54559afb
O3PCU: Split loads and stores that cross cache line boundaries.
When each load or store is sent to the LSQ, we check whether it
# HG changeset patch
# User Timothy M. Jones
# Date 1257772288 0
# Node ID da27e67385cca6cf4dd6d18cdead5cfd54559afb
# Parent 861198113ecaf172b6d1e874cda4d13c92bdb38a
BaseDynInst: Make the TLB translation timing instead of atomic.
This initiates a timing translation and passes the read or write
# HG changeset patch
# User Timothy M. Jones
# Date 1257772283 0
# Node ID 861198113ecaf172b6d1e874cda4d13c92bdb38a
# Parent e9f450b4b4f276dd3ed69dd63a540dda2796de60
Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
diff --git a/src/arch/power/faults.hh b/src/arch/power
These patches enable Power ISA benchmarks to run on O3CPU through the
following changes:
1) An alignment fault is added to the Power ISA.
2) The TLB translation mechanism is altered from atomic to timing.
3) Loads and stores are split in half if they cross a cache line boundary.
The majority of t
On Wed, 28 Oct 2009 07:09:57 -, Gabe Black
wrote:
> I was going to push the arguments-as-a-stack patch with Vince's
> fixes, but I couldn't build power because there were no default scons
> options. Is there something I'm missing, or was a file left out?
>
There should be a POWER_SE fil
OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
changeset a3c85a29b838 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a3c85a29b838
description:
test: Hello world test program for Power
includes reference outputs for the Hello World tests on simple-atomic
and o3-timing.
diffstat:
8 files changed, 979
On Sat, 24 Oct 2009 22:06:56 +0100, Vince Weaver
wrote:
>
>> +// I'm not sure why, but the length argument is in arg reg 3
>> +loff_t length = process->getSyscallArg(tc, 3);
>
> The reason for this is that on various architectures, if you are passing
> a
> 64-bit value on a 32-bit arc
On Mon, 26 Oct 2009 19:35:08 -, Ali Saidi wrote:
>
> On Mon, 26 Oct 2009 14:52:34 -0400, Gabriel Michael Black
> wrote:
>> Quoting Ali Saidi :
>>
>>>
>>> On Mon, 26 Oct 2009 01:59:14 -0700, Gabe Black
>>> wrote:
Ali Saidi wrote:
> I believe that the rules are as follows (from some
Hi Gabe,
On Mon, 26 Oct 2009 09:22:25 -, Gabe Black
wrote:
> Sorry for taking a while to get back to you. The translation used to be
> instant, so it was probably not really important where it happened.
Ok. In that case I'll probably move it into the CPU because that will help
with spli
changeset 67d980fcbc7a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=67d980fcbc7a
description:
syscall: Addition of an ioctl command code for Power.
diffstat:
5 files changed, 5 insertions(+)
src/arch/alpha/linux/linux.hh |1 +
src/arch/alpha/tru64/tru64.hh |1
changeset af13eb1b7f81 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=af13eb1b7f81
description:
syscall: Implementation of the ftruncate64 system call.
diffstat:
2 files changed, 21 insertions(+)
src/sim/syscall_emul.cc | 16
src/sim/syscall_emul.hh |
changeset 9e2f25dcf8c8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9e2f25dcf8c8
description:
syscall: Zero out memory that already exists during the brk system call.
Glibc often assumes that memory it receives from the kernel after a brk
system call w
changeset db7e5f2778cf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=db7e5f2778cf
description:
syscall: Fix conversion of the stat64 buffer during system calls.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/sim/syscall_emul.hh |2 +-
diffs (12 lines)
changeset 04cba5a03e2e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=04cba5a03e2e
description:
syscall: Implementation of the time system call.
diffstat:
2 files changed, 20 insertions(+)
src/kern/linux/linux.hh |1 +
src/sim/syscall_emul.hh | 19
changeset 5e0fcc528fe5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5e0fcc528fe5
description:
syscall: Implementation of the times system call
diffstat:
2 files changed, 35 insertions(+)
src/kern/linux/linux.hh | 11 +++
src/sim/syscall_emul.hh | 24 ++
On Thu, 22 Oct 2009 09:36:49 +0100, Gabe Black
wrote:
If you'd be willing,
making it into a timing translation while you're allowing split accesses
would be helpful for x86 in the future.
I've made an initial patch by copying some of the code from
TimingSimpleCPU and have attached it here
On Thu, 22 Oct 2009 09:36:49 +0100, Gabe Black
wrote:
> Timothy M Jones wrote:
>> On Wed, 21 Oct 2009 18:12:59 +0100, Gabe Black
>> wrote:
>>
>>
>>> In the simple CPU, the requests are all translated before any are sent,
>>> so you can't have
On Wed, 21 Oct 2009 18:12:59 +0100, Gabe Black
wrote:
> In the simple CPU, the requests are all translated before any are sent,
> so you can't have something half in the memory system and then take a
> fault on it. I don't know exactly how that would map to O3. I believe
> it's fine to do 3 byt
On Wed, 21 Oct 2009 22:14:43 +0100, Steve Reinhardt
wrote:
>> I believe that unaligned data accesses may be fairly common. There is no
>> restriction on their use. At the very least they are causing failures in
>> several benchmarks. If I were to implement a similar thing in O3 would
>> this be
Power, hacking up O3 to do the
> same
> thing may be necessary to get it running there.
>
> Steve
>
> On Wed, Oct 21, 2009 at 8:05 AM, Ali Saidi wrote:
>
>>
>> Hi Tim,
>>
>> I think x86 handles this by micro-coding loads that aren't aligned.
&
e misspeculated.
>
> Steve
>
> On Mon, Oct 19, 2009 at 7:10 AM, Timothy M Jones
> wrote:
>
>> Hi everyone,
>>
>> I'm getting an assertion failure in the top of
>> PageTable::translate(RequestPtr req) when running one of my PowerPC
>>
turns out to be misspeculated.
>
> Steve
>
> On Mon, Oct 19, 2009 at 7:10 AM, Timothy M Jones
> wrote:
>
>> Hi everyone,
>>
>> I'm getting an assertion failure in the top of
>> PageTable::translate(RequestPtr req) when running one of my PowerPC
&
On Mon, 19 Oct 2009 19:23:39 +0100, nathan binkert
wrote:
>> To be honest, I'm not fussed! I think that Daniel has summed it all up
>> rather nicely and the guide that I've used is the Power ISA so 'power'
>> would probably be the best name.
>
> Ok, I'm going to make this change and fold some
Hi everyone,
I'm getting an assertion failure in the top of
PageTable::translate(RequestPtr req) when running one of my PowerPC
binaries on O3CPU. This is the offending assertion:
assert(pageAlign(req->getVaddr() + req->getSize() - 1)
== pageAlign(req->getVaddr()));
If I com
To be honest, I'm not fussed! I think that Daniel has summed it all up
rather nicely and the guide that I've used is the Power ISA so 'power'
would probably be the best name.
Cheers
Tim
On Sat, 17 Oct 2009 19:03:11 +0100, nathan binkert
wrote:
> Seems relatively definitive.
>
> Any opinio
SE/m5.fast
> build/ARM_SE/m5.fast
> build/MIPS_SE/m5.fast
> build/POWERPC_SE/m5.fast
> build/SPARC_FS/m5.fast
> build/SPARC_SE/m5.fast
> build/X86_FS/m5.fast
> build/X86_SE/m5.fast
>
>
>
> On Thu, Oct 8, 2009 at 5:37 AM, Timothy M. Jones
> wrote:
>>
# HG changeset patch
# User Timothy M. Jones
# Date 1255700967 -3600
# Node ID 223f58dbdc54f2ea227d1e796c1d66fe8f2e6b50
# Parent 4f0ed3f5c62aea9094aef48a680466893776e4ba
Add the TCSETAW_ ioctl code to all ISAs that require it.
diff --git a/src/arch/alpha/linux/linux.hh b/src/arch/alpha/linux
# HG changeset patch
# User Timothy M. Jones
# Date 1255701144 -3600
# Node ID b597490ff2d78ba56e4ffe7464b369474b9a174b
# Parent 223f58dbdc54f2ea227d1e796c1d66fe8f2e6b50
Fix compiler errors relating to PowerPC miscregs.
There are no miscregs currently defined in PowerPC, so the compiler was
This set of patches allows the PowerPC ISA to be incorporated into M5. It
fixes the compiler errors that were generated with gcc 4.3 and includes
an ioctl code into other ISAs that was only present in PowerPC.
--
The University of Edinburgh is a charitable body, registered in
Scotland, with regis
1 - 100 of 143 matches
Mail list logo
